WO2000008768A1 - Decodeur de viterbi equipe d'une memoire de metrique de chemin de taille reduite - Google Patents

Decodeur de viterbi equipe d'une memoire de metrique de chemin de taille reduite Download PDF

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Publication number
WO2000008768A1
WO2000008768A1 PCT/US1999/017658 US9917658W WO0008768A1 WO 2000008768 A1 WO2000008768 A1 WO 2000008768A1 US 9917658 W US9917658 W US 9917658W WO 0008768 A1 WO0008768 A1 WO 0008768A1
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Prior art keywords
state
signal
address signal
read
acs
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David Hansquine
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Qualcomm Inc
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Qualcomm Inc
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Priority to AU53356/99A priority Critical patent/AU5335699A/en
Publication of WO2000008768A1 publication Critical patent/WO2000008768A1/fr
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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0262—Arrangements for detecting the data rate of an incoming signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4107—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing add, compare, select [ACS] operations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
    • H04L1/201—Frame classification, e.g. bad, good or erased
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
    • H04L1/208—Arrangements for detecting or preventing errors in the information received using signal quality detector involving signal re-encoding

Definitions

  • the invention generally relates to serial Viterbi decoders and in particular to serial Viterbi decoders for use within Code Division Multiple Access (CDMA) wireless communication systems.
  • CDMA Code Division Multiple Access
  • FIG. 1 is an illustrative block diagram of a variable rate CDMA transmission system 10 described in the Telecommunications Industry Association's Interim Standard TIA/EIA/IS-95-A Mobile Station-Base Station Compatibility Standard for Dual-Mode Wideband Spread Spectrum Cellular System.
  • This transmission system may be provided, for example, within a base station of a cellular transmission system for use in transmitting signals to mobile telephones within a cell surrounding the base station.
  • An input line 11 provides a speech or data signal which may be analog or digital.
  • the input line may be an analog or digital public switched telephone network (PSTN) line or other speech signal source.
  • PSTN public switched telephone network
  • a variable rate data source 12 receives the digitized samples of the speech signal and encodes the signal to provide packets of encoded speech of equal frame lengths.
  • Variable rate data source 12 may, for example, convert the digitized samples of the input speech to digitized speech parameters representative of the input voice signal using Linear Predictive Coding (LPC) techniques.
  • LPC Linear Predictive Coding
  • variable rate data source 12 is a variable rate vocoder as described in detail in U.S. Patent No. 5,414,796.
  • Variable rate data source 12 provides variable rate packets of data at four possible frame rates 9600 bps, 4800 bps, 2400 bps and 1200 bps, referred to herein as full, half, quarter, and eighth rates. Packets encoded at full rate contain 172 information bits, samples encoded at half rate contain 80 information bits, samples encoded at quarter rate contain 40 information bits and samples encoded at eighth rate contain 16 information bits.
  • the packets regardless of size all are one frame length in duration, i.e. 20 ms. Other systems may employ other data rates or packet sizes.
  • frame and "packet” may be used interchangeably.
  • the packets are encoded and transmitted at different rates to compress the data contained therein based, in part, on the complexity or amount of information represented by the frame. For example, if the input voice signal includes little or no variation, perhaps because the speaker is not speaking, the information bits of the corresponding packet may be compressed and encoded at eighth rate. This compression results in a loss of resolution of the corresponding portion of the voice signal but, given that the corresponding portion of the voice signal contains little or no information, the reduction in signal resolution is not typically noticeable. Alternatively, if the corresponding input voice signal of the packet includes much information, perhaps because the speaker is actively vocalizing, the packet is encoded at full rate and the information bits of the packet are not compressed at all.
  • This compression and encoding technique is employed to limit, on the average, the amount of signals being transmitted at any one time to thereby allow the overall bandwidth of the transmission system to be utilized more effectively to allow, for example, a greater number of telephone calls to be processed at any one time.
  • variable rate packets generated by data source 12 are provided to packetizer 13 which selectively appends cyclic redundancy check (CRC) bits and tail bits.
  • CRC cyclic redundancy check
  • the variable rate packets from packetizer 13 are then provided to encoder 14 which encodes the bits of the variable rate packets for error detection and correction purposes.
  • encoder 14 is a rate 1/3 convolutional serial Viterbi encoder.
  • the convolutionally encoded symbols are then provided to a modulator 16 which generates a modulated signal.
  • An implementation of a CDMA modulator is described in detail in U.S. Patent Nos. 5,103,459 and 4,901,307.
  • FIG. 2 illustrates pertinent components of a mobile telephone 28 or other mobile station receiving the transmitted signal.
  • the signal is received by antenna 30, downconverted and amplified, if necessary, by receiver 31 and demodulated by a demodulator 32 into a stream of symbols which remain convolutionally encoded.
  • the signal is then provided to a serial Viterbi decoder 34 which decodes a convolutionally encoded stream of symbols.
  • the decoder also subdivides the received signal into packets and determines the corresponding frame rate for each packet. The frame rate may be determined, for example, by detecting the duration of individual bits of the frame. Aspects of an exemplary serial Viterbi decoder are described in co- pending U.S. Patent Application 08/126,477 filed September 24, 1993, assigned to the assignee of the present invention and incorporated by reference herein.
  • decoder 34 To decode the stream of symbols, decoder 34 employs a branch error metric block 36 which receives symbols from the demodulator and an Add Compare Select block (ACS) 38 which produces decision bits based upon the symbols using two separate RAM's 40 and 41. To generate the decision bits the ACS is configured to emulate the memory elements of the encoder (encoder 14 of FIG. 1) by cycling through all states. To this end the ACS determines from which encoder state metric each new encoder state metric was arrived from. To enhance performance, the decoder chains back from what it considers the best state metric using a chainback block 42 which processes the decision bits received from ACS 38. Ultimately, decoder 34 provides a decoded packet along with a signal identifying a detected frame rate for the packet.
  • ACS Add Compare Select block
  • frame quality check unit 43 which attempts to verify that no transmission errors or frame rate detection errors occurred.
  • frame quality check unit 43 performs a CRC, a symbol error rate check and a Yamamoto metric check.
  • symbol error rate check frame quality check unit 43 re- encodes symbols found in the decoded packet and compares the re-encoded symbols with symbols input to the frame quality check unit to detect any differences.
  • Yamamoto metric check frame quality check unit 43 applies the received frames to a trellis path decoder and determines whether a resulting metric is acceptable.
  • Acceptable frames are routed to a speech decoder 44 for conversion back to digitized voice signals.
  • the digitized voice signals are converted to analog signals by a digital to analog converter (not shown) for ultimate output through a speaker 46 of the mobile telephone such that an operator of the telephone can hear the speech signal that had been originally input to the overall system along line 11 of FIG. 1.
  • the mobile telephone of FIG. 2 may have additional components for inputting an analog speech signal from the operator of the mobile telephone and for processing and transmitting the signal using CDMA techniques.
  • the additional components of the mobile telephone may be similar to the components shown in FIG. 1.
  • the transmission system of FIG. 1 may have additional components provided for receiving the transmitted signal from the mobile telephone and for processing and outputting the signal as an analog or digital speech signal, perhaps onto a PSTN line.
  • the additional components of the system of FIG. 1 may be similar to the components shown in FIG. 2.
  • the decoder employs an ACS which emulates the memory elements of the encoder used to encode the signals by cycling through all states in order from 0 through to 2 K_1 -1 wherein K is the constraint length of the code employed by the encoder. More specifically, the constraint length K is equal to one more than the number of delay elements in the encoder.
  • K is the constraint length of the code employed by the encoder. More specifically, the constraint length K is equal to one more than the number of delay elements in the encoder.
  • the order in which the states are cycled through is functionally irrelevant as long as long as the cycling is consistent.
  • FIG. 3 shows all possible state transitions.
  • the notation xO as used herein indicates that the least significant bit of the state is 0 while the upper bits are represented by x.
  • Ox indicates that the most significant bit is 0 while the lower bits are x.
  • the incoming information bit determines which transition is made from a given state and will in fact form the most significant bit of the target state. Starting in state 0, it is only possible to transition to states 0 and hex 80.
  • a transition to state 0 means that the input bit is a 0 (the bit that gets shifted into the leftmost bit of the target state), while if the input bit is a 1, then it is only possible to transition to state hex 80 (lx in FIG. 3.)
  • states are calculated out of order vs. the order in which the states were read.
  • the ACS employs the aforementioned separate RAM's 40 and 41 and pages between the two RAM's.
  • the newly calculated metrics are written to a different memory from the one from which the metrics were read.
  • the function of the two memories are swapped.
  • Each RAM memory must store 2 K ⁇ 1 metrics.
  • the serial Viterbi decoder could be configured to use only a single memory storing 2 metrics. In either case, though, the need to store a total of 2 metrics is an inefficient use of memory that results in a larger amount of circuit area being required for implementation than would otherwise be desirable.
  • an improvement is provided within a serial Viterbi decoder for decoding a convolutionally encoded stream of symbols using an add-compare-select (ACS) unit configured to 1 store only 2 " metrics wherein K is a constraint length previously utilized in encoding the stream of symbols.
  • ACS add-compare-select
  • the serial Viterbi decoder includes a branch error metric block, an ACS, and a chainback block.
  • the ACS generates a plurality of decision bits from a convolutionally encoded stream of symbols received from the branch error metric block during each of plurality of process cycles, wherein one cycle of all encoder states is one process cycle. Each decision bit is representative of an error metric of a corresponding encoder state.
  • the ACS has one or more memories storing state metrics for each of the encoder states and is configured to both read from and write to the memories. The memories collectively store only 2 metrics.
  • the ACS includes a left rotator for cyclically generating a read address signal specifying addresses to be read from the memories; a set of delay elements connected to an output of the left rotator for delaying the read address signal to generate a write address signal specifying addresses to be written to within the memories; and a multiplexor for receiving the read address signal and the write address signal and generating a single address signal and for applying to an address input of the memories.
  • the left rotator receives an input signal specifying an encoder state and a rotate signal specifying the amount of rotation, wherein the rotate signal is changed each time the ACS has cycled through all encoder states.
  • the rotate signal is equal to the number of the process cycle modulo K-l-log 2 N wherein N is the number of state metrics stored per memory location. Hence, with differing values of N, a variety of configurations are supported.
  • FIG. 1 is an block diagram illustrating pertinent components of a variable rate CDMA transmission system
  • FIG. 2 is an block diagram illustrating pertinent components of a mobile telephone or other mobile station receiving the signal transmitted by the CDMA transmission system of FIG. 1 and decoding the signal using a serial Viterbi decoder having an ACS with two separate RAM's;
  • FIG. 3 is a state diagram illustrating the permissible state transitions for the ACS.
  • FIG. 4 is an block diagram illustrating, at a high level, pertinent components of a mobile telephone or other mobile station configured in accordance with an exemplary embodiment of the invention wherein a serial Viterbi decoder having an ACS with only a single state RAM is employed.
  • FIG. 5 is an schematic illustrating an exemplary embodiment of the ACS with single state RAM of FIG. 4.
  • FIG. 4 illustrates pertinent components of a mobile telephone 128 or other mobile station receiving a transmitted CDMA signal. Portions of mobile telephone 128 operate in the same manner as the mobile telephone of FIG. 2 and will be only briefly described.
  • the CDMA signal is received by antenna 130, downconverted and amplified, if necessary, by receiver 131 and demodulated by a demodulator 132 into a stream of convolutionally encoded symbols.
  • the convolutionally encoded symbols are then provided to a modified serial Viterbi decoder 134 which decodes the stream of symbols using a branch error metric block 136, an ACS 138, a chainback block 140.
  • the ACS produces decision bits based upon the symbols received from the branch error metric block.
  • the ACS emulates the memory elements of the encoder used to encode the data (e.g. encoder 14 of FIG. 1). To this end, the ACS cycles through all states in order from 0 through to 2 " -1 and determines the previous encoder state metric from which each new metric was derived.
  • the ACS includes a single RAM 141 for storing the state metrics by writing new state metrics into the memory locations of the states previously read.
  • the ACS reads the states in a consistent order (e.g. state order). Hence, the ACS first determines where each state is stored.
  • a process cycle counter is provided within the ACS which increments each time the ACS has cycled through 2 " states. The counter is used to rotate the state number of interest to derive the memory address for that state.
  • decoder 134 provides a decoded packet along with a signal identifying a detected frame rate for the packet a frame quality check unit 143 which attempts to verify that no transmission errors or frame rate detection errors occurred using a CRC, a symbol error rate check and a Yamamoto metric check. Acceptable frames are routed to a speech decoder 144 for conversion back to digitized voice signals. The digitized voice signals are converted to analog signals by a digital to analog converter (not shown) for ultimate output through a speaker 146 of the mobile telephone.
  • the mobile telephone of FIG. 4 may have additional components for inputting an analog speech signal from the operator of the mobile telephone and for processing and transmitting the signal using CDMA techniques. The additional components of the mobile telephone may be similar to the components shown in FIG. 1.
  • FIG. 4 illustrates, at a high level, a serial Viterbi decoder having an ACS with only a single RAM storing 2 K metrics.
  • the ACS and ACS RAM of FIG. 4 may be implemented using any of variety of specific configurations. Some specific exemplary configurations adapted for use with IS-95 mobile telephone specifications will now be described.
  • a left rotator 150 (or re-circulating shift register) receives an acs_cycle(7:l) signal identifying the current encoder state of the ACS.
  • the 7:1 refers to all bits of the encoder state except the least significant bit and the current information bit.
  • the state is composed of the bits stored in the K-l latches and the current data bit.
  • the 7:1 thereby strips off the least significant bit (i.e. the oldest data bit) and the most significant bit (i.e. the newest data bit).
  • Left rotator 150 also receives a "rotate by" signal pcycle modulo 7 which is a counter incremented each time the ACS has cycled through all 2 1 states, pcycle thereby tracks the process cycle number.
  • pcycle modulo 7 is a counter incremented each time the ACS has cycled through all 2 1 states, pcycle thereby tracks the process cycle number.
  • Left rotator 150 calculates a read address for reading the correct state metric corresponding the current encoder state from a state RAM 152.
  • the read address is output as a rdaddr signal.
  • Read address signal rdaddr is routed through three delay registers 154, 156, and 158 (each driven by an oddclk signal which pulses every other clock cycle) to generate a delayed signal wraddr.
  • Signals rdaddr and wraddr are both routed into a multiplexor 159, the output of which is applied as the actual read or write address-input addr of state RAM 152.
  • the state RAM also receives an acsen signal as its cs_n input.
  • the acsen signal disables the ACS when the ACS is not in use.
  • the acsen signal is also routed into a NAND gate 160 which also receives the oddclk signal inverted by an inverter 162.
  • the output of NAND gate 160 is applied to the state RAM as the ⁇ e_n input.
  • the state RAM also receives new state metrics as data input din.
  • • acs_cycle is the encoder state that the ACS is cycling through.
  • • pcycle is a counter that is incremented each time the ACS has cycled through all 2 " states. It keeps track of the process cycle number.
  • state metrics are assumed to be stored in state RAM 152 in their correct state order (i.e. memory location 0 contains state 0's metric, location 1 contains state l's metric, etc.) and are read from the state RAM in that order.
  • the ACS reads states 00 and 01 and can then calculate new values of states 00 and hex 80. Then the ACS reads states 02 and 03 and calculates new metrics for states 01 and hex 81. (All state numbers used herein are in hexadecimal format.)
  • the values therein are no longer needed and the memory location is then available to store a new metric for a different state.
  • left rotator 150 determines the new memory location for each state.
  • Delay elements 154, 156 and 158 operate to delay writing into the memory locations until after the previous values have been read until after the previous values have been read and the new ones calculated.
  • Table I illustrates the states that are present in the state RAM at the beginning of each process cycle.
  • K 9 so there are 2 " or 256 states.
  • This particular architecture also assumes that two consecutive states are stored in each memory location, so that there are actually 128 memory words.
  • the states are in order, but new state metrics are calculated out of order resulting in the states being ordered as they are for process cycle 1.
  • the states are then read in state order and new metrics are stored resulting in the states being ordered as indicated under process cycle 2. This process continues cyclically until the new metrics are again stored in normal order. For this example, the order of the metrics cycles back to the original order in process cycle 7.
  • FIG. 5 and Table I together illustrate an embodiment wherein two consecutive states are stored in each memory location of the state RAM.
  • the state RAM may be configured to store more or fewer states in each memory location as needed to permit the ACS to handle limited memory bandwidth or to reduce the number of cycles required to compute 2 " states.
  • the memory is configured to store only half the number of words but where each word contains twice as many bits. In this case, four consecutive states are stored in each memory location. The number of delay stages differs from that of FIG. 5 as appropriate to provide the proper delay to the read address.
  • circuitry is provided to subtract " 3 " from the acs_cycle using a subtractor and to then feed the modified acs_cycle through a second left rotator to generate the write address.
  • an additional left rotator and a subtractor are employed rather than registers 154 - 158.
  • Still other circuit variations may be employed as well.
  • Each cell specifies the state # that is stored at the State RAM address provided in the corresponding entry of the left-most column of the table at the beginning of the process cycle shown at the corresponding entry of the top row of the table.
  • Table II shows that state 0 is stored at address 0, state 1 is at address 1, etc.
  • the new state metrics are calculated, the new metrics are written such that they reflect what is shown under Process cycle 1, hence state O's new metric is written to address 0, state 80's new metric is written to address 1, state l's new metric is written to address 2, state 81's new metric is written to address 3, etc.
  • N is the number of states stored per memory location. N is dependent on the particular architecture. Faster decoders may need to store more states per memory location.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Artificial Intelligence (AREA)
  • Quality & Reliability (AREA)
  • Error Detection And Correction (AREA)

Abstract

L'invention concerne un décodeur sériel de Viterbi pour téléphone mobile, qui comprend une RAM de stockage des métriques d'état, laquelle RAM ne nécessitant le stockage que des métriques 2k-1 (k étant la longueur de contrainte du code) au lieu des métriques 2k comme l'exigeaient les modes d'exécution antérieurs dans lesquels les nouvelles métriques d'état et les anciennes métriques d'état étaient stockées dans deux mémoires différentes. Les ACS incluent un rotateur gauche qui reçoit un signal identifiant l'état courant de l'encodeur de l'ACS et un signal de compteur incrémenté chaque fois que l'ACS a accompli un cycle passant en revue tous les états autorisés. Le rotateur gauche calcule une adresse lue en vue de déterminer, à partir de la RAM d'état, la métrique d'état correcte correspondant à l'état courant de l'encodeur. L'adresse lue est acheminée à travers un ensemble de registres de temporisation commandés chacun par un signal d'horloge qui impulse tous les autres cycles d'horloge. Le signal lu et le signal temporisé lu sont tous deux acheminés vers le multiplexeur, dont la sortie est utilisée comme l'entrée-adresse de lecture ou d'écriture de la RAM d'état. Un signal d'autorisation d'écriture est appliqué à la RAM d'état au moyen du système d'horloge inversé. Ainsi, la RAM d'état lit et écrit des métriques d'état à partir de la même adresse mémoire, l'adresse étant déterminée par le rotateur gauche et l'opération d'écriture étant temporisée par rapport à l'opération de lecture.
PCT/US1999/017658 1998-08-04 1999-08-04 Decodeur de viterbi equipe d'une memoire de metrique de chemin de taille reduite Ceased WO2000008768A1 (fr)

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AU53356/99A AU5335699A (en) 1998-08-04 1999-08-04 Viterbi decoder with reduced size path metric memory

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US12902198A 1998-08-04 1998-08-04
US09/129,021 1998-08-04

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10010238A1 (de) * 2000-03-02 2001-09-27 Infineon Technologies Ag Verfahren zum Speichern von Pfadmetriken in einem Viterbi-Decodierer
WO2001078239A3 (fr) * 2000-04-06 2002-03-14 Qualcomm Inc Procede et dispositif servant a lire et memoriser des parametres d'etat pour mise en application d'un decodeur viterbi acs tres rapide
CN100428636C (zh) * 2004-09-27 2008-10-22 普天信息技术研究院 一种计算累加路径度量值的加比选装置和方法
US20140129908A1 (en) * 2012-11-06 2014-05-08 Texas Instruments, Incorporated Viterbi butterfly operations

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Publication number Priority date Publication date Assignee Title
US4979175A (en) * 1988-07-05 1990-12-18 Motorola, Inc. State metric memory arrangement for a viterbi decoder
US5416787A (en) * 1991-07-30 1995-05-16 Kabushiki Kaisha Toshiba Method and apparatus for encoding and decoding convolutional codes
JPH07336239A (ja) * 1994-06-07 1995-12-22 Japan Radio Co Ltd ビタビ復号器
EP0720303A2 (fr) * 1994-12-29 1996-07-03 AT&T Corp. Registres en place état présent/état suivant

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Publication number Priority date Publication date Assignee Title
US4979175A (en) * 1988-07-05 1990-12-18 Motorola, Inc. State metric memory arrangement for a viterbi decoder
US5416787A (en) * 1991-07-30 1995-05-16 Kabushiki Kaisha Toshiba Method and apparatus for encoding and decoding convolutional codes
JPH07336239A (ja) * 1994-06-07 1995-12-22 Japan Radio Co Ltd ビタビ復号器
EP0720303A2 (fr) * 1994-12-29 1996-07-03 AT&T Corp. Registres en place état présent/état suivant

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1996, no. 604 30 April 1996 (1996-04-30) *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10010238A1 (de) * 2000-03-02 2001-09-27 Infineon Technologies Ag Verfahren zum Speichern von Pfadmetriken in einem Viterbi-Decodierer
DE10010238C2 (de) * 2000-03-02 2003-12-18 Infineon Technologies Ag Verfahren zum Speichern von Pfadmetriken in einem Viterbi-Decodierer
US7062701B2 (en) 2000-03-02 2006-06-13 Infineon Technologies Ag Method for storing path metrics in a viterbi decoder
WO2001078239A3 (fr) * 2000-04-06 2002-03-14 Qualcomm Inc Procede et dispositif servant a lire et memoriser des parametres d'etat pour mise en application d'un decodeur viterbi acs tres rapide
US6757864B1 (en) 2000-04-06 2004-06-29 Qualcomm, Incorporated Method and apparatus for efficiently reading and storing state metrics in memory for high-speed ACS viterbi decoder implementations
CN100428636C (zh) * 2004-09-27 2008-10-22 普天信息技术研究院 一种计算累加路径度量值的加比选装置和方法
US20140129908A1 (en) * 2012-11-06 2014-05-08 Texas Instruments, Incorporated Viterbi butterfly operations
US8943392B2 (en) * 2012-11-06 2015-01-27 Texas Instruments Incorporated Viterbi butterfly operations

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