WO2001097281A3 - Verfahren zur bearbeitung eines wafers - Google Patents

Verfahren zur bearbeitung eines wafers Download PDF

Info

Publication number
WO2001097281A3
WO2001097281A3 PCT/DE2001/002150 DE0102150W WO0197281A3 WO 2001097281 A3 WO2001097281 A3 WO 2001097281A3 DE 0102150 W DE0102150 W DE 0102150W WO 0197281 A3 WO0197281 A3 WO 0197281A3
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
processing
supporting
joining layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/DE2001/002150
Other languages
English (en)
French (fr)
Other versions
WO2001097281A2 (de
Inventor
Friedrich Kroener
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of WO2001097281A2 publication Critical patent/WO2001097281A2/de
Publication of WO2001097281A3 publication Critical patent/WO2001097281A3/de
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7402—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7412—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding

Landscapes

  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

Die Erfindung betrifft ein Verfahren zur Bearbeitung eines scheibenförmigen Wafers (1) bei welchem unter Zwischenlagerung einer Schutzschicht (4) auf einen Wafer (1) ein Träger-Wafer (2) aufgebracht wird. Der Träger-Wafer (2) wird mit dem Wafer (1) mittels einer Verbindungsschicht (5) lösbar verbunden. An der freiliegenden Scheibenseite des Wafers (1) werden Bearbeitungsschritte durchgeführt, wonach der Träger-Wafer (2) durch Entfernen der Verbindungsschicht (5) vom Wafer (1) abgelöst wird.
PCT/DE2001/002150 2000-06-13 2001-06-10 Verfahren zur bearbeitung eines wafers Ceased WO2001097281A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10029035.3 2000-06-13
DE10029035A DE10029035C1 (de) 2000-06-13 2000-06-13 Verfahren zur Bearbeitung eines Wafers

Publications (2)

Publication Number Publication Date
WO2001097281A2 WO2001097281A2 (de) 2001-12-20
WO2001097281A3 true WO2001097281A3 (de) 2002-04-11

Family

ID=7645529

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2001/002150 Ceased WO2001097281A2 (de) 2000-06-13 2001-06-10 Verfahren zur bearbeitung eines wafers

Country Status (2)

Country Link
DE (1) DE10029035C1 (de)
WO (1) WO2001097281A2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10156465C1 (de) * 2001-11-16 2003-07-10 Infineon Technologies Ag Waferanordnung und Verfahren zur Herstellung einer Bondverbindung
DE10232914B4 (de) * 2002-07-19 2004-11-04 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Wiederverwendbarer Trägerwafer und Verfahren zur Herstellung desselben
DE10238601A1 (de) * 2002-08-22 2004-03-11 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Handhabungswafer zur Handhabung von Substraten
US9111982B2 (en) 2012-04-25 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer assembly with carrier wafer
DE102012107899B4 (de) * 2012-04-25 2014-07-17 Taiwan Semiconductor Manufacturing Co., Ltd. Waferanordnung mit Trägerwafer und Herstellungsverfahren dafür

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3632074A (en) * 1967-10-09 1972-01-04 Western Electric Co Releasable mounting and method of placing an oriented array of devices on the mounting
AT324435B (de) * 1968-10-28 1975-08-25 Joseph Lucas Ind Verfahren zur herstellung von halbleiterbauelementen
US3947303A (en) * 1974-07-30 1976-03-30 Semikron, Gesellschaft Fur Gleichrichterbau Und Elektronik M.B.H. Method for producing a surface stabilizing protective layer in semiconductor devices
US4023997A (en) * 1967-10-09 1977-05-17 Western Electric Company, Inc. Method of placing an oriented array of devices on a releasable mounting
EP0325704A2 (de) * 1988-01-27 1989-08-02 General Instrument Corporation Prozess zur gleichzeitigen Herstellung einer Mehrzahl von Halbleiterbauelementen aus einer einzigen Scheibe
EP0844648A1 (de) * 1996-06-07 1998-05-27 Rohm Co., Ltd. Halbleiterbaustein und verfahren zu dessen herstellung
EP0977240A1 (de) * 1998-07-30 2000-02-02 IMEC vzw System, Verfahren und Vorrichtung Zur Bearbeitung von Halbleitern
FR2792440A1 (fr) * 1999-04-19 2000-10-20 Schlumberger Systems & Service Dispositif a circuit integre securise contre des attaques procedant par destruction controlee d'une couche complementaire

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3524301A1 (de) * 1985-07-06 1987-01-15 Semikron Gleichrichterbau Verfahren zum herstellen von halbleiterelementen

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3632074A (en) * 1967-10-09 1972-01-04 Western Electric Co Releasable mounting and method of placing an oriented array of devices on the mounting
US4023997A (en) * 1967-10-09 1977-05-17 Western Electric Company, Inc. Method of placing an oriented array of devices on a releasable mounting
AT324435B (de) * 1968-10-28 1975-08-25 Joseph Lucas Ind Verfahren zur herstellung von halbleiterbauelementen
US3947303A (en) * 1974-07-30 1976-03-30 Semikron, Gesellschaft Fur Gleichrichterbau Und Elektronik M.B.H. Method for producing a surface stabilizing protective layer in semiconductor devices
EP0325704A2 (de) * 1988-01-27 1989-08-02 General Instrument Corporation Prozess zur gleichzeitigen Herstellung einer Mehrzahl von Halbleiterbauelementen aus einer einzigen Scheibe
EP0844648A1 (de) * 1996-06-07 1998-05-27 Rohm Co., Ltd. Halbleiterbaustein und verfahren zu dessen herstellung
EP0977240A1 (de) * 1998-07-30 2000-02-02 IMEC vzw System, Verfahren und Vorrichtung Zur Bearbeitung von Halbleitern
FR2792440A1 (fr) * 1999-04-19 2000-10-20 Schlumberger Systems & Service Dispositif a circuit integre securise contre des attaques procedant par destruction controlee d'une couche complementaire

Also Published As

Publication number Publication date
WO2001097281A2 (de) 2001-12-20
DE10029035C1 (de) 2002-02-28

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