WO2002044836A2 - Procede et appareil de communication microprocesseur-reseau - Google Patents

Procede et appareil de communication microprocesseur-reseau Download PDF

Info

Publication number
WO2002044836A2
WO2002044836A2 PCT/US2001/043621 US0143621W WO0244836A2 WO 2002044836 A2 WO2002044836 A2 WO 2002044836A2 US 0143621 W US0143621 W US 0143621W WO 0244836 A2 WO0244836 A2 WO 0244836A2
Authority
WO
WIPO (PCT)
Prior art keywords
signal
protocol
microprocessor
network
adapter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2001/043621
Other languages
English (en)
Other versions
WO2002044836A3 (fr
Inventor
Yijun Zhao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
P & S Datacom Corp
Original Assignee
P & S Datacom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by P & S Datacom Corp filed Critical P & S Datacom Corp
Priority to AU2002241498A priority Critical patent/AU2002241498A1/en
Publication of WO2002044836A2 publication Critical patent/WO2002044836A2/fr
Publication of WO2002044836A3 publication Critical patent/WO2002044836A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/08—Protocols for interworking; Protocol conversion

Definitions

  • the present invention relates, in general, to network communication and, more particularly, to establishing communication between a microprocessor and a network.
  • MCUs embedded microcontroller units
  • TCP/IP Transmission Control Protocol/Internet Protocol
  • An MCU with TCP/IP programmed therein can access Internet through a modulation and demodulation device (MODEM) .
  • MODEM modulation and demodulation device
  • This approach normally needs an MCU of at least 16 bits. It also needs a large memory, e.g., at least 32 kilo-bytes, and a high operating speed in order to achieve a satisfactory performance.
  • the engineers who program the MCU chip must be familiar not only with the applications of the MCU but also with the TCP/IP protocol and related interfaces. Therefore, this approach usually requires a long development period, a high performance chip, and is cost inefficient.
  • Another approach for connecting a microprocessor such as an MCU to a network is to establish an off chip network interface, e.g., an interface developed by emWare, Inc.
  • emGateway program a network interface compatible protocol, e.g., a protocol developed by emWare, Inc. under the trademark "emNet", into the MCU chip.
  • emNet a protocol developed by emWare, Inc.
  • An MCU with emNet programmed therein can access Internet via the network interface emGateway.
  • emNet requires less memory than TCP/IP, this approach still requires the design engineers to be familiar not only with the application of the MCU but also with the emNet and related interfaces.
  • the existing MCU chips in a user's application systems may not satisfy the designer's expectation because of chip capability, memory, speed, etc. Therefore, this approach often also requires a long development period, a relatively high performance chip, and is cost inefficient.
  • a prime advantage of the present invention is to provide a simple and cost efficient process for communicating between a microprocessor and a network. Another advantage of the present invention is to provide a simple, reliable, and cost efficient apparatus to implement the communication process. A further advantage of the present invention is to provide the communication process capable of establishing communications between the network and microprocessors with wide spectra of applications, capabilities, performances, bit numbers, memory sizes, etc. In addition, a particular advantage of the present invention is that the communication process can be readily implemented with an existing microprocessor chip.
  • a method for communicating between a microprocessor and a network is implemented by first coupling the microprocessor to a signal adapter.
  • the signal adapter of the present invention establishes communications between a microprocessor having an internal bus and a network gateway having a network bus.
  • the signal adapter of the present invention is sometimes referred to as a WebChip.
  • the architecture and structure of the microprocessor can be independent of the communication protocol adopted by the network gateway.
  • the signal adapter includes a signal processing unit and a memory unit coupled to the signal processing unit.
  • a communication protocol is stored in the memory unit.
  • the signal adapter also has an interpreter stored in the memory unit.
  • the interpreter is compatible with the programming language, e.g., Java, C, C++, an assembly language, etc., of the microprocessor.
  • the signal adapter functions as an intermediary between the network and the microprocessor.
  • a signal in the network typically follows a network protocol.
  • a signal in the Internet typically follows Transmission Control ⁇ Protocol/Internet Protocol (TCP/IP) .
  • TCP/IP Transmission Control ⁇ Protocol/Internet Protocol
  • a signal in the network is sent to the microprocessor through a network gateway and the signal adapter.
  • the network gateway coverts the signal from TCP/IP to a protocol compatible with the communication protocol on the signal adapter.
  • the signal adapter identifies, interprets, and reformats the signal received from the network gateway into a microprocessor acceptable signal, e.g., a signal in a protocol compatible with the internal bus of the microprocessor, e.g., SPI, I 2 C, MICORWARE, etc. Further, the signal is preferably in a format compatible with Java, C, C++, an assembly language, etc.
  • the signal adapter can execute the reformatted signal and/or send the reformatted signal to the microprocessor.
  • the microprocessor executes the received signal and sends a return signal back to the network.
  • the return signal is sent to the signal adapter according to a format acceptable to the signal adapter.
  • the signal adapter identifies, interprets, and reformats the return signal in accordance with the communication protocol and sends it to the network
  • the network gateway converts the signal into the network protocol and sends it to the network.
  • the signal adapter of the present invention can establish communications between networks and microprocessors of various capabilities, performances, bit numbers, and memory sizes. It is compatible with microprocessors having as little as four bits. It occupies significantly less memory on the microprocessor than prior art communication systems. It does not require significant modifications of the software and the hardware structure of existing microprocessors in a user's application systems. The designers of the microprocessors are not required to be familiar with the network protocol.
  • a network e.g., Internet
  • the communication protocol on the signal adapter can be simple and memory space efficient. Therefore, the signal adapter of the present invention is simple, reliable, and cost efficient.
  • Fig. 1 is a block diagram of a microprocessor-network communication system in accordance with the present invention
  • Fig. 2 is a block diagram illustrating the physical structure of a signal adapter in accordance with a preferred embodiment of the present invention
  • Fig. 3 is a functional block diagram illustrating a signal adapter in accordance with another preferred embodiment of the present invention
  • Fig. 4 is a block diagram schematically illustrating a signal adapter in accordance with yet another embodiment of the present invention.
  • FIG. 1 is a block diagram illustrating a microprocessor-network communication system 10 in accordance with the present invention.
  • Fig. 1 shows communication system 10 between a network 15 and a plurality of microprocessors 25A, 25B, ..., and 25N.
  • communication system 10 is capable of establishing the communications between network 15 and any number of microprocessors, e.g., one, two, three, four, and so on.
  • Microprocessors 25A-25N include any kinds of processing units such as, for example, digital signal processing units (DSPs) , £entral processing units (CPUs) , microcontroller units (MCUs) , etc.
  • DSPs digital signal processing units
  • CPUs £entral processing units
  • MCUs microcontroller units
  • Microprocessors 25A-25N can be coupled to various kinds of electronic systems (not shown) such as, for example, smart devices, utility meters, refrigeration systems, home security systems, medical monitoring systems, vending machines, navigation systems, etc. for monitoring and/or controlling the operations of those electronic systems.
  • Communication system 10 establishes communications between network 15 and microprocessors 25A-25TSI through a network interface 12 and a plurality of signal adapters 20A, 20B, ..., and 20N.
  • Network interface 12 is also referred to as a network gateway or a gateway.
  • signal adapters 20A-20N are sometimes referred to as WebChips and can includes a microprocessor, communication peripheral, field programmable £ate array (FPGA) , programmable logic device (P D) , system on chip (SOC) , application specific standard product (ASSP) , application specific -ntegrated circuit
  • FPGA field programmable £ate array
  • P D programmable logic device
  • SOC system on chip
  • ASSP application specific standard product
  • Signal adapter 20A is coupled to microprocessor 25A via a signal transmission line 24A.
  • signal adapter 20B is coupled to microprocessor 25B via a signal transmission line 24B, and signal adapter 20N is coupled to microprocessor 25N via a signal transmission line
  • Signal adapters 20A-20N establish communications between network gateway 12 and respective microprocessors 25A-25N.
  • each of signal adapters 20A-20N and corresponding microprocessors 25A-25N are located adjacent to each other and close to respective , electronic systems (not shown) coupled to corresponding microprocessors 25A-25N.
  • Signal adapters 20A-20N establish communications respective microprocessors 25A-25N having internal buses and network gateway 12 having a network bus. -Thus, the architectures and structures of microprocessors 25A-25N can be independent of the communication protocol adopted by network gateway 12.
  • Fig. 1 shows network gateway 12 being coupled to network 15 via a signal transmission line 14 and coupled to signal adapters 20A, 20B, ..., and 20N via corresponding signal transmission lines 16A, 16B, ..., and 16N.
  • signal adapters 20A, 20B, ..., and 20N via corresponding signal transmission lines 16A, 16B, ..., and 16N.
  • network 15 e.g., an Internet browser with TCP/IP, a web page, a database, a graphic user interface (GUI), a custom application program interface, etc.
  • network gateway 12 are installed in a single system, e.g., an information server, a database server, a personal computer, a p_ersonal digital assistant (PDA) , a _set-t_op box (STB) , an Internet appliance (IA) , etc.
  • the communications between network gateway 12 and network 15 can be either wired or wireless.
  • the communications between network gateway 12 and signal adapters 20A-20N can also be either wired or wireless.
  • wireless communication examples include radio frequency (RF) communication and infrared communication following an Infrared Data Association (IrDA) protocol.
  • Wired communication can be either serial or parallel signal transmissions.
  • the serial signal transmissions such as asynchronous data transmissions following the RS-232 or RS-485 serial communication standard published by the Electronic Industries Alliance (EIA) , are typically more cost efficient and more reliable than parallel signal transmissions.
  • EIA Electronic Industries Alliance
  • the parallel signal transmissions are usually faster than the serial signal transmissions .
  • FIG. 2 is a block diagram of the structure of a signal adapter 20 coupled between a network gateway 12 and a microprocessor 25 in accordance with a preferred embodiment of the present invention.
  • Signal adapter 20 can be any of signal adapters 20A-20N shown in Fig. 1.
  • Microprocessor 25 can be any of microprocessors 25A-25N shown in Fig. 1.
  • Signal adapter 20 is an apparatus for establishing a communication or providing an interface between microprocessor 25 and a network, such as network 15 shown in Fig. 1.
  • Signal adapter 20 transforms a signal received from network gateway 12 and following a communication protocol to a signal in an internal protocol compatible with the programming language and the hardware structure of microprocessor 25.
  • the internal protocol is sometimes also referred to as a microprocessor protocol.
  • Signal adapter 20 also transforms a signal received from microprocessor 25 and following the microprocessor protocol compatible with the programming language the hardware structure of microprocessor 25 to a signal in the communication protocol compatible with network gateway 12. Therefore, signal adapter 20 can also be referred to as a network adapter, a network connector, an interface, a signal conversion device, a data conversion device, a network connecting device, a network connectivity device, a network interface, a communication controller, etc.
  • Signal adapter 20 includes a signal processing unit 42 and a memory unit 44 coupled to signal processing unit 42.
  • memory unit 44 is a nonvolatile memory unit, e.g., a read only memory (ROM) , an electrically erasable and programmable read only memory (EEPROM) , FLASH memory, and the likes.
  • Signal processing unit 42 can be a microprocessor, an MCU, a CPU, or the likes.
  • signal adapter 20 also includes a volatile memory unit (not shown), e.g., a static random access memory (SRAM) or a dynamic random access memory (DRAM) unit coupled to signal processing unit 42.
  • a communication protocol 43 and an interpreter 45 are established in signal adapter 20.
  • communication protocol 43 and interpreter 45 are stored in memory unit 44.
  • Communication protocol 43 is preferably compatible with a protocol of network gateway 12.
  • network gateway 12 may adopt emNet protocol.
  • Interpreter 45 is preferably compatible with a programming, language, e.g., Java, C, C++, assembly language, etc., of microprocessor 25.
  • Signal adapter 20 has terminals 54 and 56 connected to signal processing unit 42. Terminal 54 is adapted for coupling to microprocessor 25 via a signal transmission line 24.
  • Signal transmission line 24 can be a serial signal transmission line or a parallel signal transmission line.
  • signal transmission line 24 includes a three-wire serial synchronous communication protocol referred to as s_erial peripheral interface (SPI) and developed by Motorola, Inc.
  • SPI serial synchronous communication protocol
  • signal transmission line 24 includes a multi-master bus referred to as an Inter-Integrated Circuit (I 2 C) bus and developed by Philips Semiconductors, Inc.
  • signal transmission line 24 includes a serial bus developed by National Semiconductor Corporation under the trademark MICROWARE.
  • Terminal 56 is adapted for transmitting signals between signal processing unit 42 and network gateway 12.
  • the signal transmissions between signal processing unit 42 and network gateway 12 can be either wired or wireless and may follow any industry standards or protocols such as those described herein above with reference to Fig. 1.
  • An interface circuit 46 in signal adapter 20 is connected to terminal 56 and functions to conform signal to predetermined standards and protocols.
  • Signal adapter 20 further includes an oscillator and identifier circuit 48 coupled to signal processing unit 42.
  • the oscillator provides a clock signal to signal processing unit 42.
  • the identifier provides an electronic identification to signal adapter 20, thereby enabling network gateway 12 to selectively communicate with any of microprocessors 25A-25N via respective signal adapters 20A-20N as shown in Fig. 1.
  • signal processing unit 42 and memory unit 44 are fabricated on a single semiconductor chip.
  • Interface circuit 46 and oscillator and identifier circuit 48 can be either fabricated on the same chip as signal processing unit 42 and memory unit 44 or fabricated on different chips.
  • signal processing unit 42, memory unit 44, interface circuit 46, and oscillator and identifier circuit 48 are packaged together as a single integrated c_ircuit (IC) device 20.
  • IC integrated c_ircuit
  • different components in signal adapter 20 can be fabricated on a single chip or on different chips and can be packaged into a signal device or packaged into several devices.
  • signal adapter 20 is not limited to being an IC device. It is also conceivable for signal adapter 20 to be comprised of discrete devices.
  • signal adapter 20 In operation, when signal adapter 20 is switched on, it is initially disconnected from network gateway 12. Signal adapter 20 sends a signal to microprocessor 25 requesting initialization. Microprocessor 25 responds by transmitting an initialization signal to signal adapter 20. Signal adapter 20 sets up the connection with network gateway 12 in accordance with the initialization signal. If signal adapter 20 does not receive the initialization signal from microprocessor 25 within a predetermined time interval, it will use a default initial state to establish the connection with network gateway 12. Signal adapter 20 will generate an error signal and transmit the error signal to network gateway 12, informing network 15 regarding the initialization failure.
  • the communications among microprocessor 25, signal adapter 20, and network gateway 12 follow a predetermined protocol.
  • network gateway 12 and signal adapter 20 have a master-slave relationship with respect to each other, and signal adapter 20 and microprocessor 25 have a master-slave relationship with respect to each other.
  • a master can initiate a process in a slave by sending a signal to the slave, and the slave sends signals back the master upon request.
  • Network gateway 12 can send command signals, data signals, and request signals to signal adapter 20.
  • communication protocol 43 in signal adapter 20 unpacks the signal and verifies the validity of the signal.
  • signal adapter 20 can verify the validity of the signal by performing a cyclic redundancy check (CRC) .
  • CRC cyclic redundancy check
  • Signal adapter 20 informs network gateway 12 about any invalid signal.
  • signal processing unit 42 transforms or converts a valid signal following the communication protocol into a signal following the microprocessor protocol in accordance with a microprocessor programming language.
  • signal adapter 20 generates a signal or a data package in the microprocessor protocol compatible with microprocessor 25 in response to the signal in the communication protocol and received from network gateway 12. More particularly, signal adapter 20 identifies, interprets, and reformats the signal from network gateway 12 into a signal acceptable to microprocessor 25. Depending the signal, signal adapter 20 executes the transformed signal and/or transmits the ⁇ transformed signal to microprocessor 25 via signal transmission line 24.
  • Microprocessor 25 executes the incoming signal or data received from signal adapter 20. Depending on the signal, microprocessor 25 may return a signal or data package back to network gateway 12. In a preferred embodiment, microprocessor 25 can send data or return signals to adapter only after receiving permission from signal adapter 20. Upon receiving the permission, microprocessor 25 transmits the returned signal to signal adapter 20 via signal transmission line 24. Preferably, the return signal follows a predetermined format acceptable to signal adapter 20. In accordance with communication protocol 43 and interpreter 45 stored in memory unit 44, signal processing unit 42 transforms, converts, or reformats the return signal following the microprocessor programming language into a signal in the communication protocol.
  • signal adapter 20 generates a signal or a data packet in a protocol compatible with the communication protocol in response to the signal in the • microprocessor protocol compatible with microprocessor 25 and received from microprocessor 25. Following permission from network gateway 12, signal adapter 20 transmits the transformed signal to network gateway 12 through interface circuit 46. Depending on its size, a signal or data transmitted between network gateway 12, signal adapter 20, and microprocessor 25 can be transmitted in a single data packet or in a plurality of data packets.
  • signal adapter 20 sends a signal to microprocessor 25 requesting initialization when signal adapter 20 is switched on. After initialization, signal adapter 20 periodically sends event polling signals to microprocessor 25. If there is an event to be reported from microprocessor 25 to network gateway 12. Signal adapter 20 will establish a connection or a path of signal transmission to network gateway 12. In addition, signal adapter 20 may transmit signals to microprocessor 25 for sending data to microprocessor 25 and for granting permission to microprocessor 25 to send data to signal adapter 20.
  • microprocessor 25 can send a control command signal to signal adapter 20 to disrupt the path of signal transmission between signal adapter 20 and network gateway 12, or disconnect signal adapter 20 from network gateway 12. While being disconnected from network gateway 12, signal adapter 20 is preferably in a low power consumption sleep state. In accordance with a preferred embodiment of the present invention, signal adapter 20 in the sleep state periodically sends request signals to microprocessor 25. For example, signal adapter 20 can generate and transmit a request signal to microprocessor 25 once in a period ranging from approximately 50 milliseconds (ms) to approximately 800 ms. According to one preferred embodiment, signal adapter 20 transmits a request signal to microprocessor 25 every 200 ms .
  • ms milliseconds
  • signal adapter 20 transmits a request signal to microprocessor 25 every 500 ms .
  • microprocessor 25 sends a response signal to signal adapter 20.
  • the response signal may continue to place signal adapter 20 in the sleep mode.
  • the response signal may also be a control command signal for reconnecting signal adapter 20 to 'network gateway 12, initializing or resetting signal adapter 20, etc.
  • information communicated between microprocessor 25 and network gateway 12 are preferably based on an object property table that describes object properties related to the operation of microprocessor
  • the object property table can be stored in microprocessor 25, signal adapter 20, network gateway 12, or a server on network 15. If the object property table is stored in microprocessor 25, the object property table is preferably mapped from microprocessor 25 to signal adapter 20 and further to network gateway 12 upon initialization of signal adapter 20.
  • FIG. 3 is a functional block diagram illustrating a signal adapter 20 couple between microprocessor 25 and network gateway 12 in accordance with another preferred embodiment of the present invention.
  • Signal adapter 20 serves to establish communications between microprocessor 25 having an internal bus and network gateway 12 having a network bus.
  • the architecture and structure of microprocessor 25 can be independent of the communication protocol adopted by network gateway 12.
  • microprocessor 25 is an MCU.
  • Signal adapter 20 has an application layer 100 functionally coupled to MCU 25 via a data transmission layer 62, an MCU bus 64, and signal transmission line 24.
  • Data transmission layer 62 controls the signal transmission between application layer 100 and MCU bus 64.
  • Data transmission layer 62 also performs the trouble shooting function during the data transmission process.
  • MCU bus 64 provides a physical port for signal transmission line 24 between signal adapter 20 and MCU 25.
  • MCU bus 64 generates voltage levels at signal transmission line 24 when signal adapter 20 transmits signals to MCU 25, and sense the voltage levels at signal transmission line 24 when signal adapter 20 receives signals from MCU 25.
  • Application layer 100 is further coupled to network gateway 12 via a communication interface protocol stack 82, a gateway bus 84, and signal transmission line 16.
  • Communication interface protocol stack 82 preferably supports various types of communication processes.
  • communication interface protocol stack 82 encodes the data packets into electrical signals and sends the signals to network gateway 12 via gateway bus 84.
  • communication interface protocol stack 82 decodes the data packet from the electrical signals transmitted from network gateway 12 via gateway bus 84.
  • Communication interface protocol stack 82 also verifies the validity of the signal.
  • Communication interface protocol stack 82 includes a medium assess control unit (MAC) 83 for network address coding.
  • MAC 83 serves to direct data packets to proper a destination node address on network 15 shown in Fig. 1.
  • Gateway bus 84 also serves to determine whether signal adapter 20 and MCU 25 coupled thereto are at the proper network node address for an incoming data packet.
  • Gateway bus 84 transmits signal to network gateway 12 by generating voltage levels and signal transmission line 16. When receiving signals from network gateway 12, gateway bus 84 senses the voltage levels at signal transmission line 16.
  • Gateway bus 84 can be any kinds of data transmission physical interfaces, e.g., RS-232, RS-485, universal _serial bus (USB), controller area network (CAN) , consumer electronics bus (CEBus) , Bluetooth, etc.
  • Gateway bus 84 is sometimes also referred to as a network bus .
  • Application layer 100 includes a protocol conversion unit or converter 102 in application layer 100 for converting the data format between a protocol compatible with MCU 25, referred as an MCU protocol by way of example, and a protocol compatible with network gateway 12, referred to as a communication protocol by way of example.
  • Protocol converter 102 is coupled to a memory 104 in application layer 100.
  • Memory 104 preferably includes a non-volatile memory such as, for example, FLASH, EEPROM, etc., and a volatile memory such as SRAM, DRAM, etc.
  • signal adapter 20 has a digital identification (Digital ID) (not shown) stored in memory 104.
  • the Digital ID of signal adapter 20 provides accessibility of signal adapter 20 from anywhere on network 15 shown in Fig. 1.
  • Protocol converter 102 and memory 104 are also coupled to an MCU data processing unit 106 and a network data process unit 108 in application layer 100.
  • MCU data processing unit 106 is coupled to data transmission layer 62.
  • MCU data processing unit 106 packs the data to be sent to MCU 25 into data packets and transmits the data packets to data transmission layer 62.
  • MCU data processing unit 106 also unpacks the data packets from MCU 25 via data transmission layer 62 and sends the unpacked data to protocol converter 102.
  • Network data processing unit 108 is coupled to communication interface protocol stack 82.
  • Network data processing unit 108 packs the data to be sent to network gateway 12 into data packets and transmits the data packets to communication interface protocol stack 82.
  • Network data processing unit 108 also unpacks the data packets from network gateway 12 via communication interface protocol stack 82 and sends the unpacked data to protocol converter 102.
  • Application layer 100 also includes communication control unit or a controller 105 coupled to protocol converter 102, memory 104, MCU data processing unit 106, and network data processing unit 108 in application layer 100. Controller 105 is further coupled to data transmission layer 62, communication interface protocol stack 82, and gateway bus 84 in signal adapter 20. In a preferred embodiment, controller 105 can modify the communication codes stored in memory 104, thereby controlling the operation modes of signal adapter 20. Through controlling data transmission layer 62, controller 105 is capable of setting the signal transmission modes between MCU 25 and signal adapter 20. Likewise, through communication interface protocol stack 82, controller 105 is capable of setting the signal transmission modes between signal adapter 20 and network gateway 12 and setting the format of the data packets to be sent from signal adapter 20 to network gateway 12. Through gateway bus 84, controller 105 is capable of selecting the communication modes and signal transmission speeds between signal adapter 20 and network gateway 12.
  • Memory 104 stores the programming codes and relevant parameters for the operation of signal adapter 20. Memory 104 may also store the object property table. If the object property table is stored in MCU 25, it is preferably mapped into memory 104 when signal adapter 20 is initialized. Memory 104 also temporarily stores the information passing through signal adapter 20 during the communication between network gateway 12 and MCU 25. In a preferred embodiment, memory 104 includes two memory blocks so that the programming codes in memory 104 can be modified through an In-Application re- Programming (IAP) process initiated by user coupled to network gateway 12. In operation, when signal adapter 20 is switched on, it is initially disconnected from network gateway 12. Signal adapter 20 sends a signal to MCU 25 requesting initialization. MCU 25 responds by transmitting a control signal to signal adapter 20.
  • IAP In-Application re- Programming
  • Controller 105 in signal adapter 20 executes the control signal from MCU 25 and sets up the connection with network gateway 12 in accordance with the initialization signal. If signal adapter 20 does not receive the control signal from MCU 25 within a predetermined time interval, controller 105 will generate an error signal. Alternatively, controller 105 may use a default initial state to establish the connection between signal adapter 20 and network gateway 12. Controller 105 selects a communication interface protocol, e.g., USB, RS-232, R-485, etc., stored in communication interface protocol stack 82 to match that of gateway bus 84.
  • a communication interface protocol e.g., USB, RS-232, R-485, etc.
  • network gateway 12 and signal adapter 20 have a master-slave relationship with respect to each other, and signal adapter 20 and MCU 25 have a master- slave relationship with respect to each other.
  • a master can initiate a process in a slave by sending a signal to the slave, and the slave sends signals back the master upon request.
  • Network gateway 12 can send command signals, data signals, and request signals to signal adapter 20.
  • Gateway bus 84 senses the voltage levels at signal transmission line 16, thereby receiving the signals form network gateway 12.
  • MAC 83 in communication interface protocol stack 82 determines whether signal adapter 20 and MCU 25 coupled thereto are the proper network node address for receiving the signals from network gateway 12.
  • Communication interface protocol stack 82 decodes the electrical signals from gateway bus 84 and preferably verifies the validity of the signals from network gateway 12. Preferably, signal adapter 20 informs network gateway 12 about any invalid signal. After the validity check, communication interface protocol stack 82 sends the decoded signals to network data process unit 108 in data packets . Network data processing unit 108 unpacks the data packets and sends the unpacked data to protocol converter 102. The signals from network gateway 12 follow a communication protocol, protocol converter 102 transforms or converts a valid signal following the communication protocol into a signal following an MCU protocol in accordance with a microprocessor programming language and the hardware structure of MCU 25.
  • protocol converter 102 generates signals or data in an MCU protocol compatible with MCU 25 in response to the signals in the communication protocol and received from network gateway 12. More particularly, protocol converter 102 identifies, interprets, and reformats the signal from network gateway 12 into a signal acceptable to MCU 25.
  • controller 105 may instruct signal adapter 20 to ignore the transformed signal, or execute the signal and proceed to transmit the transformed signal to MCU 25.
  • protocol converter 102 sends the transformed signal to MCU data processing unit 106, which packs the signal into data packets and transmits the data packets to MCU bus 64 via data transmission layer 62.
  • Data transmission layer 62 which performs the functions of data transmission control and trouble shooting.
  • MCU bus 64 generates voltage levels at signal transmission line 24 to transmit data to MCU 25.
  • MCU 25 preferably responds every signal from signal adapter 20. If MCU 25 fails to respond within a predetermined time interval, e.g., a time interval between approximately 50 ms and approximately 800 ms, controller 105 in signal adapter 20 will recognizes it as a timeout error. MCU 25 transmits the response signal in data packets to signal adapter 20 via signal transmission line 24. MCU bus 64 senses the voltage levels at signal transmission line 24 to detect the signals from MCU 25. Data transmission layer 62 relays the signal from MCU bus 64 to MCU data processing unit 106. MCU data processing unit 106 unpacks the data packets received from data transmission layer 62 and sends the unpacked data to protocol converter 102.
  • a predetermined time interval e.g., a time interval between approximately 50 ms and approximately 800 ms
  • Protocol converter 102 transforms, converts, or reformats the data following the MCU protocol to into signals or data following the communication protocol of network gateway 12.
  • protocol converter 102 generates the signals in the communication protocol accepted by network gateway 12 in response to signals or data in an MCU protocol compatible with MCU 25. More particularly, protocol converter 102 identifies, interprets, and reformats the signal from MCU 25 into a signal acceptable to network gateway 12. Signal adapter 20 can ignore the signal from MCU 25. Further, signal adapter 20 may transmit the signal received from MCU 25 to network gateway 12. To relay the signal from MCU 25 to network gateway 12, protocol converter 102 transmits the converted signal to network data processing unit 108, which packs the signal into data packets and sends the data packets to communication interface protocol stack 82. Communication interface protocol stack 82 encodes the data packets into electrical signals.
  • Gateway bus 84 generates voltage levels at signal transmission line 16 in accordance with the encoded electrical signals from communication interface protocol stack 82, thereby transmitting the response signal from MCU 25 to network gateway 12.
  • signal adapter 20 can sends command signals to MCU 25.
  • Signal adapter 20 may send commands to MCU 25 as requested by its own master network gateway 12 or as initiated by signal adapter 20 itself.
  • signal adapter may periodically sends event polling signals to MCU 25.
  • a command signal from signal adapter 20 preferably requires a response from MCU 25.
  • the response signal from MCU 25 may include information and data requested by signal adapter 20.
  • MCU may also respond signal adapter 20 by transmitting a control command to signal adapter 20.
  • Controller 105 in signal adapter 20 preferably executes the control command, thereby initializing, rebooting, or resetting signal adapter 20.
  • the control command from MCU 25 can specify the communication modes between signal adapter 20 and MCU 25 and between signal adapter 20 and network gateway 12.
  • the control command can also disconnect signal adapter 20 from network gateway 12 and put signal adapter in a low power consumption sleep mode.
  • signal adapter 20 periodically sends polling signals to MCU 25.
  • MCU 25 can wake up signal adapter 20 by sending a command to signal adapter 20 in response to the polling signal.
  • a user on network 15 can send programming codes to signal adapter 20 via network gateway 12.
  • the programming codes transmitted to signal adapter 20 can be used for modifying the programming codes of signal adapter 20 in an IAP process.
  • signal adapter 20 can reformats the programming codes and send the reformatted programming codes - to MCU 25 for modifying the programming codes in MCU 25 in an IAP process.
  • FIG. 4 is a block diagram schematically illustrating a signal adapter chip 120 in accordance coupled between MCU 25 and network gateway 12 in with yet another preferred embodiment of the present invention.
  • Signal adapter chip 120 which is sometimes also referred to as a WebChip, includes a signal adapter 20 and a peripheral circuit 90.
  • signal adapter chip 120 can replace any of signal adapters 20A-20N shown in Fig. 1.
  • Signal adapter 20 in signal adapter chip 120 is functionally similar to signal adapter 20 shown in Figs. 2 and 3.
  • Peripheral circuit 90 may include any circuit, e.g., real t_ime clock (RTC) , FPGA, power management circuitry, data converter, etc., that is suitable to serve as a periphery for MCU 25.
  • RTC real t_ime clock
  • MCU 25 can be replaced with a microprocessor, FPGA, PLD, ASSP, ASIC, DSP, CPU, etc.
  • Signal adapter chip 120 also includes a switching unit 121 coupled to MCU 25 via signal transmission line 24. Switching unit 121 is also coupled to signal adapter 20 via an internal bus 124 and to peripheral circuit 90 via another internal bus 94. A switch logic circuit 123 on signal adapter chip 120 is coupled for controlling switching unit 121.
  • MCU 25 has a chip selection (CS) or chip enabling (CE) signal line 125 coupled to switch logic circuit 123 in signal adapter chip 120.
  • CS chip selection
  • CE chip enabling
  • a feature of signal adapter chip 120 is the inclusion of peripheral circuit on the same chip as signal adapter 20.
  • MCU 25 transmits a chip selection signal to switch logic circuit 123.
  • Switch logic circuit 123 controls switching unit 121 to determine whether signal transmission line 24 is coupled to signal adapter 20 via internal bus 124 or to peripheral circuit 90 via internal bus 94.
  • MCU 25 can communicate with signal adapter 20 and network gateway 12 in a process similar to those described supra with reference to Figs. 1, 2, and 3.
  • MCU 25 is a slave with respect to signal adapter 20.
  • MCU 25 When coupled to peripheral circuit 90 via signal transmission line 24, switching circuit 121, and internal bus 94, MCU 25 is the master of peripheral circuit 94.
  • the communication and operation of an MCU and its peripheral circuit are well known in the art.
  • the signal adapter of the present invention is capable of establishing communications between networks and microprocessors without modifying the software structure or the hardware structure of existing microprocessors.
  • the microprocessor design processes do not depend on the network protocol. The designers of the microprocessors are not required to be familiar with the network protocol.
  • the signal adapter is compatible with microprocessors, MCUs, CPUs, etc., of various capabilities, performances, bit numbers, and memory sizes.
  • the development time and cost of a microprocessor-network system in accordance with the present invention are significantly reduced compared with prior art microprocessor-network communication systems.
  • the signal adapter communicates with the network via a network gateway, thereby significantly simplifying the signal adapter compared with prior art devices. Therefore, the signal adapter of the present invention is simple, reliable, and cost efficient.
  • the communication process of the present invention can be readily implemented with microprocessors in a user's existing application systems.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)

Abstract

L'invention concerne un adaptateur de signaux (20) qui sert d'intermédiaire entre un microprocesseur (25) et un réseau (15). L'adaptateur de signaux (20) reformate un signal, reçu d'une passerelle de réseau (12) et suivant un protocole de réseau, en un signal compatible avec les structures de logiciel et d'équipement du microprocesseur, et émet le signal reformaté au microprocesseur (25). L'adaptateur de signaux (20) transforme également un signal reçu du microprocesseur (25) en un signal compatible avec le protocole de réseau et émet le signal transformé à la passerelle de réseau (12). L'adaptateur de signaux (20) est capable d'établir une communication de réseau pour divers types de microprocesseurs sans beaucoup modifier ou reprogrammer les microprocesseurs.
PCT/US2001/043621 2000-11-28 2001-11-16 Procede et appareil de communication microprocesseur-reseau Ceased WO2002044836A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002241498A AU2002241498A1 (en) 2000-11-28 2001-11-16 Microprocessor-network communicaiton method and apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US72450200A 2000-11-28 2000-11-28
US09/724,502 2000-11-28

Publications (2)

Publication Number Publication Date
WO2002044836A2 true WO2002044836A2 (fr) 2002-06-06
WO2002044836A3 WO2002044836A3 (fr) 2002-08-15

Family

ID=24910665

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/043621 Ceased WO2002044836A2 (fr) 2000-11-28 2001-11-16 Procede et appareil de communication microprocesseur-reseau

Country Status (2)

Country Link
AU (1) AU2002241498A1 (fr)
WO (1) WO2002044836A2 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1335562A3 (fr) * 2002-02-12 2004-09-29 Sanden Corporation Système de gestion pour machines de vente
DE102007031718A1 (de) * 2007-07-06 2009-01-08 Carl Zeiss Surgical Gmbh Kommunikationseinrichtung für ein chirurgisches System und chirurgisches System, insbesondere ophtalmisches mikrochirurgisches System zur Phako-Chirurgie

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4837677A (en) * 1985-06-14 1989-06-06 International Business Machines Corporation Multiple port service expansion adapter for a communications controller
JPH0619771A (ja) * 1992-04-20 1994-01-28 Internatl Business Mach Corp <Ibm> 異種のクライアントによる共用ファイルのファイル管理機構
JP3227850B2 (ja) * 1992-12-07 2001-11-12 ヤマハ株式会社 マルチアクセス型ｌａｎ
US6047002A (en) * 1997-01-16 2000-04-04 Advanced Micro Devices, Inc. Communication traffic circle system and method for performing packet conversion and routing between different packet formats including an instruction field
US6229818B1 (en) * 1997-07-07 2001-05-08 Advanced Micro Devices, Inc. Active isolation system and method for allowing local and remote data transfers across a common data link
KR100251712B1 (ko) * 1997-07-11 2000-04-15 윤종용 전전자교환기에서 엑스.25 프로토콜 통신을 위한 엑스.25망정합장치
US6151390A (en) * 1997-07-31 2000-11-21 Cisco Technology, Inc. Protocol conversion using channel associated signaling

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1335562A3 (fr) * 2002-02-12 2004-09-29 Sanden Corporation Système de gestion pour machines de vente
DE102007031718A1 (de) * 2007-07-06 2009-01-08 Carl Zeiss Surgical Gmbh Kommunikationseinrichtung für ein chirurgisches System und chirurgisches System, insbesondere ophtalmisches mikrochirurgisches System zur Phako-Chirurgie
DE102007031718B4 (de) * 2007-07-06 2012-12-06 Carl Zeiss Meditec Ag Kommunikationseinrichtung für ein chirurgisches System und chirurgisches System, insbesondere ophtalmisches mikrochirurgisches System zur Phako-Chirurgie

Also Published As

Publication number Publication date
AU2002241498A1 (en) 2002-06-11
WO2002044836A3 (fr) 2002-08-15

Similar Documents

Publication Publication Date Title
US8073439B2 (en) Control system and method for operating a transceiver
US7337259B2 (en) Smart card virtual hub
KR100424297B1 (ko) 가전기기 제어시스템 및 그 동작방법
CN100524119C (zh) 一种可编程逻辑控制器与扩展模块的接口
CN113228567B (zh) 一种信息处理的方法、装置和信息处理系统
KR100550524B1 (ko) 홈 네트워크 시스템 및 그 동작방법
KR20050032313A (ko) 홈 네트워크 시스템
CN103973643A (zh) 智能协议转换器
CN112514332A (zh) 一种基于事物描述模型以使USB设备转作物联网（IoT）设备运行的方法和系统
KR101559089B1 (ko) 장치의 컴포넌트들 간에 메모리 자원들을 공유하기 위한 통신 프로토콜
KR100328499B1 (ko) 다양한 프로토콜의 홈 네트워크와 액세스 네트워크를연결하는홈 게이트웨이 시스템 및 네트워크 정합방법
KR101632710B1 (ko) LTE 게이트웨이용 IoT 단말기 및 그를 이용한 단말기 확장 방법
CN109873741B (zh) 一种单线共享总线协议的系统和工作方法
WO2002044836A2 (fr) Procede et appareil de communication microprocesseur-reseau
US6718397B1 (en) Network adapter for providing initialization and protocol translation between a microprocessor and a network interface
US6714990B1 (en) Communication system and data adapter
CN115460036A (zh) 基于uart实现多路can数据收发的系统、方法、设备及存储介质
KR100386599B1 (ko) 다수의 홈 네트워크 분리 방법
KR100504610B1 (ko) 홈 네트워크 시스템의 홈 코드 설정방법
CN2659038Y (zh) 一种嵌入式网络接口电路
KR100565524B1 (ko) 홈네트워크 시스템 및 그 동작방법
CN115708076A (zh) 用于单总线的通信方法、装置、服务器及存储介质
WO2002044837A2 (fr) Protocole de communication de réseau local
EP1481296B1 (fr) Appareil electromenager dote d&#39;une unite de communication permettant une commande externe
WO2002044925A1 (fr) Protocole de communication microprocesseur/interface

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: COMMUNICATION UNDER RULE 69 (EPO FORM 1205A OF 09.09.2003)

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP