WO2002097895A3 - Transistor, verfahren zur herstellung einer integrierten schaltung und verfahren zur herstellung einer metallsilizidschicht - Google Patents

Transistor, verfahren zur herstellung einer integrierten schaltung und verfahren zur herstellung einer metallsilizidschicht Download PDF

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Publication number
WO2002097895A3
WO2002097895A3 PCT/EP2002/005773 EP0205773W WO02097895A3 WO 2002097895 A3 WO2002097895 A3 WO 2002097895A3 EP 0205773 W EP0205773 W EP 0205773W WO 02097895 A3 WO02097895 A3 WO 02097895A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer
producing
metal silicide
metal oxide
silicide layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2002/005773
Other languages
English (en)
French (fr)
Other versions
WO2002097895A2 (de
Inventor
Dietmar Krueger
Andriy Goryachko
Rainer Kurps
Jing Ping Liu
Hans-Joerg Osten
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
IHP GmbH
Original Assignee
IHP GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10127234A external-priority patent/DE10127234A1/de
Application filed by IHP GmbH filed Critical IHP GmbH
Priority to EP02740651A priority Critical patent/EP1396028A2/de
Priority to US10/479,300 priority patent/US7196382B2/en
Publication of WO2002097895A2 publication Critical patent/WO2002097895A2/de
Publication of WO2002097895A3 publication Critical patent/WO2002097895A3/de
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/013Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332Making the insulator
    • H10D64/01336Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/01342Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid by deposition, e.g. evaporation, ALD or laser deposition
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/011Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251Source or drain electrodes for field-effect devices
    • H10D64/258Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/62Electrodes ohmically coupled to a semiconductor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Für die Herstellung einer höchstintegrierten Schaltung, vorzugsweise im Rahmen eines CMOS oder BiCMOS-Prozesses, wird ein neuartiges Verfahren zur selektiven Silizidierung von Kontaktbereichen vorgeschlagen. Dabei wird eine Metalloxidschicht (14), die beispielsweise Praseodymoxid enthält, auf einem präparierten Wafer (12) abgeschieden. Auf der Metalloxidschicht (14) wird anschließend eine Siliziumschicht (16) und auf dieser eine Deckelschicht (18) abgeschieden. Die Deckelschicht wird lateral strukturiert. In einem nachfolgenden Temperschritt in sauerstofffreier, reduzierender Gasatmosphäre wird in Lateralabschnitten (20, 22), in denen die Deckelschicht (18) entfernt wurde, die Siliziumschicht (16) und die Metalloxidschicht (14) in eine Metallsilizidschicht umgewandelt.
PCT/EP2002/005773 2001-05-26 2002-05-24 Transistor, verfahren zur herstellung einer integrierten schaltung und verfahren zur herstellung einer metallsilizidschicht Ceased WO2002097895A2 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP02740651A EP1396028A2 (de) 2001-05-26 2002-05-24 Transistor, verfahren zur herstellung einer integrierten schaltung und verfahren zur herstellung einer metallsilizidschicht
US10/479,300 US7196382B2 (en) 2001-05-26 2002-05-24 Transistor, method for producing an integrated circuit and a method of producing a metal silicide layer

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE10127234A DE10127234A1 (de) 2001-05-26 2001-05-26 Transistor, Verfahren zur Herstellung einer integrierten Schaltung und Verfahren zur Herstellung einer Metallsilizidschicht
DE10127234.0 2001-05-26
DE10155915.1 2001-11-12
DE10155915 2001-11-12

Publications (2)

Publication Number Publication Date
WO2002097895A2 WO2002097895A2 (de) 2002-12-05
WO2002097895A3 true WO2002097895A3 (de) 2003-09-25

Family

ID=26009474

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2002/005773 Ceased WO2002097895A2 (de) 2001-05-26 2002-05-24 Transistor, verfahren zur herstellung einer integrierten schaltung und verfahren zur herstellung einer metallsilizidschicht

Country Status (3)

Country Link
US (1) US7196382B2 (de)
EP (1) EP1396028A2 (de)
WO (1) WO2002097895A2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10230674B4 (de) 2002-07-04 2006-11-23 IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik Halbleiterkondensator und damit aufgebauter MOSFET
DE10348006B4 (de) * 2003-10-15 2006-07-20 Infineon Technologies Ag Feldeffekttransistor, insbesondere vertikaler Feldeffekttransistor, Speicherzelle und Herstellungsverfahren
US7384481B2 (en) * 2003-12-29 2008-06-10 Translucent Photonics, Inc. Method of forming a rare-earth dielectric layer
WO2005065357A2 (en) * 2003-12-29 2005-07-21 Translucent, Inc. Rare earth-oxides, rare-earth-nitrides, rare earth-phosphides and ternary alloys with silicon
US8495527B2 (en) 2010-10-28 2013-07-23 International Business Machines Corporation Pattern recognition with edge correction for design based metrology
US8429570B2 (en) 2010-10-28 2013-04-23 International Business Machines Corporation Pattern recognition with edge correction for design based metrology
US8803243B2 (en) 2012-01-03 2014-08-12 International Business Machines Corporation Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor
US10971399B2 (en) 2019-01-21 2021-04-06 International Business Machines Corporation Oxygen-free replacement liner for improved transistor performance

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0048849A2 (de) * 1980-09-29 1982-04-07 International Business Machines Corporation Verfahren zur Herstellung von Schottky-Sperrschicht-Silizid-Kontakten auf Siliziumsubstraten und Silizium-Halbleiter-Einrichtungen mit Schottky-Sperrschicht-Silizid-Kontakten
EP0171003A2 (de) * 1984-07-27 1986-02-12 Hitachi, Ltd. Feldeffekttransistor mit zusammengesetztem Draingebiet
US4803539A (en) * 1985-03-29 1989-02-07 International Business Machines Corporation Dopant control of metal silicide formation
EP0407202A2 (de) * 1989-07-06 1991-01-09 Sony Corporation Herstellen von Halbleitervorrichtungen
US6100173A (en) * 1998-07-15 2000-08-08 Advanced Micro Devices, Inc. Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process
EP1094514A2 (de) * 1999-10-18 2001-04-25 Nec Corporation Flachgraben-Isolationsstruktur für Bipolar-Transistoren

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62162362A (ja) * 1986-01-10 1987-07-18 Mitsubishi Electric Corp Mos型集積回路及びその製造方法
US5221853A (en) * 1989-01-06 1993-06-22 International Business Machines Corporation MOSFET with a refractory metal film, a silicide film and a nitride film formed on and in contact with a source, drain and gate region
US6191059B1 (en) * 1998-12-30 2001-02-20 Libbey-Owens-Ford Co. Metal silicides as performance modifiers for glass compositions
KR100327347B1 (en) * 2000-07-22 2002-03-06 Samsung Electronics Co Ltd Metal oxide semiconductor field effect transistor having reduced resistance between source and drain and fabricating method thereof
US6458678B1 (en) * 2000-07-25 2002-10-01 Advanced Micro Devices, Inc. Transistor formed using a dual metal process for gate and source/drain region
DE10039327A1 (de) 2000-08-03 2002-02-14 Ihp Gmbh Elektronisches Bauelement und Herstellungsverfahren für elektronisches Bauelement
DE10230674B4 (de) * 2002-07-04 2006-11-23 IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik Halbleiterkondensator und damit aufgebauter MOSFET

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0048849A2 (de) * 1980-09-29 1982-04-07 International Business Machines Corporation Verfahren zur Herstellung von Schottky-Sperrschicht-Silizid-Kontakten auf Siliziumsubstraten und Silizium-Halbleiter-Einrichtungen mit Schottky-Sperrschicht-Silizid-Kontakten
EP0171003A2 (de) * 1984-07-27 1986-02-12 Hitachi, Ltd. Feldeffekttransistor mit zusammengesetztem Draingebiet
US4803539A (en) * 1985-03-29 1989-02-07 International Business Machines Corporation Dopant control of metal silicide formation
EP0407202A2 (de) * 1989-07-06 1991-01-09 Sony Corporation Herstellen von Halbleitervorrichtungen
US6100173A (en) * 1998-07-15 2000-08-08 Advanced Micro Devices, Inc. Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process
EP1094514A2 (de) * 1999-10-18 2001-04-25 Nec Corporation Flachgraben-Isolationsstruktur für Bipolar-Transistoren

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
OSTEN H J ET AL: "HIGH-K GATE DIELECTRICS WITH ULTRA-LOW LEAKAGE CURRENT BASED ON PRASEODYMIUM OXIDE", INTERNATIONAL ELECTRON DEVICES MEETING 2000. IEDM. TECHNICAL DIGEST. SAN FRANCISCO, CA, DEC. 10 - 13, 2000, NEW YORK, NY: IEEE, US, 10 December 2000 (2000-12-10), pages 653 - 656, XP000988915, ISBN: 0-7803-6439-2 *

Also Published As

Publication number Publication date
US7196382B2 (en) 2007-03-27
WO2002097895A2 (de) 2002-12-05
EP1396028A2 (de) 2004-03-10
US20050227466A1 (en) 2005-10-13

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