WO2003010616A1 - Circuit mos integre a miroir de courant - Google Patents

Circuit mos integre a miroir de courant Download PDF

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Publication number
WO2003010616A1
WO2003010616A1 PCT/JP2002/006970 JP0206970W WO03010616A1 WO 2003010616 A1 WO2003010616 A1 WO 2003010616A1 JP 0206970 W JP0206970 W JP 0206970W WO 03010616 A1 WO03010616 A1 WO 03010616A1
Authority
WO
WIPO (PCT)
Prior art keywords
current mirror
circuit
transistor
mos
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2002/006970
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English (en)
Japanese (ja)
Inventor
Munehiro Karasudani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NSC Co Ltd
Original Assignee
Nigata Semitsu Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nigata Semitsu Co Ltd filed Critical Nigata Semitsu Co Ltd
Publication of WO2003010616A1 publication Critical patent/WO2003010616A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Definitions

  • the present invention relates to a MOS integrated circuit having a current mirror.
  • CMOS technology has features such as low power consumption, low voltage operation, high-speed operation with miniaturization, and low manufacturing cost. Mostly adopted.
  • the RF (Radio Frequency) circuit (analog circuit section) that receives and processes high-frequency signals often uses bipolar technology or GaAs technology. Technology was rarely used. This is because the CMOS technology is mainly suitable for digital circuits, and the SMOS cannot obtain good and sufficient high-frequency characteristics in the CMOS circuit.
  • FIG. 1 shows the basic circuit of a power mirror constructed using the CMOS technology.
  • the current mirror circuit shown in FIG. 1 p MO S transistor T r 1 to flow a reference current I, and the current 1 2 is equal, a circuit for supplying the p MO S transistor T r 2 in the independent potentials
  • the pMOS transistor Trl has a so-called diode connection in which the source and the gate are connected.
  • p M ⁇ S Transistor The source of Tr 1 is connected to the power supply VDD, and the drain is grounded via the resistor R.
  • Another pMOS transistor Tr2 which forms a current mirror together with the pMOS transistor Tr1, has a source connected to the power supply VDD, a drain connected to a desired position, and a gate connected to the pMOS transistor Trl. Connected to the gate of r1.
  • the current mirror circuit is written as a circuit diagram as shown in Fig. 1, but when actually laying out on a semiconductor chip, the current mirror circuit arrangement often has to be separated as shown in Fig. 2. .
  • each transistor T rl, Tr 2 itself is arranged at a required position on the layout, and another power supply VDD is connected to the source of each transistor T rl, Tr 2.
  • the wires 11 and 12 between the gates of the transistors Tr 1 and Tr 2 and between the sources are elongated long.
  • the source line 12 to which the power supply VDD is connected is elongated, a distributed resistance is generated on the source line 12.
  • the source line The resistance value generated on 12 increases. As a result, a voltage drop occurs due to the resistance, and the source potentials are not uniform between the transistors Tr 1 and Tr 2.
  • the present invention has been made to solve such a problem, and keeps the current mirror in good balance even when the circuit arrangement of the current mirror is far away from the chip layout.
  • the purpose is to be able to Disclosure of the invention
  • a MOS integrated circuit having a current mirror In a MOS integrated circuit having a current mirror according to the present invention, a plurality of MOS transistor elements constituting a current mirror are arranged close to each other, and a signal line connected to a drain of the plurality of MOS transistor elements is provided as desired. It is characterized by wiring to the position.
  • Another embodiment of the present invention is characterized in that the sources of the plurality of MOS transistor elements are commonly connected to the same power supply.
  • an amplifier circuit in which a differential amplifier that amplifies an input signal from a previous stage and outputs the amplified signal to the next stage is connected in multiple stages, and is commonly connected to the plurality of differential amplifiers connected in multiple stages.
  • a plurality of MOS transistors connected between the plurality of differential amplifiers and the constant current source circuit, and a plurality of current mirror circuits each including a plurality of MOS transistors.
  • the signal lines connected to the drains of the plurality of MOS transistor elements are routed to the positions of the plurality of differential amplifiers, respectively. .
  • the present invention comprises the above technical means, the source wiring length between a plurality of M ⁇ S transistor elements constituting the current mirror circuit is shortened, and the distributed resistance and the voltage drop generated on the distribution line can be minimized. Becomes BRIEF DESCRIPTION OF THE FIGURES
  • FIG. 1 is a diagram showing a configuration example of a general current mirror circuit.
  • FIG. 2 is a diagram showing an example of a layout of a conventional current mirror circuit.
  • FIG. 3 is a diagram showing an example of a layout configuration of the current mirror circuit according to the present embodiment on a CMOS integrated circuit.
  • FIG. 4 is a diagram showing another example of the layout of the current mirror circuit according to the present embodiment on a CMOS integrated circuit.
  • FIG. 5 is a diagram showing a configuration example of a multistage amplifier to which the current mirror circuit of the present embodiment is applied.
  • FIG. 3 is a diagram showing an example of a layout of a current mirror circuit according to the present embodiment on a CMOS integrated circuit.
  • Karen Tomi error circuit shown in FIG. 3 p MO S transistor T r 1 to flow a reference current I, and the current 1 2 is equal, is a circuit for supplying the P MO S transistor T r 2 in the independent potential .
  • the pMOS transistor Trl has a so-called diode connection in which the source and the gate are connected.
  • the gate of this pMOS transistor Tr1 is connected to the gate of the other PM ⁇ S transistor Tr2 that forms a current mirror together with the pMOS transistor Tr1.
  • the sources of the pair of pMOS transistors Trl and Tr2 are connected in common to the same power supply VDD via a common node A which is approximately the same distance from each transistor Tr1 and Tr2. I have.
  • the drain of the pMOS transistor Tr1 is grounded via the resistor R, and the drain of the pMOS transistor Tr2 is connected to a desired position.
  • a pair of pMOS transistors Tr 1 and Tr 2 constituting a current mirror are arranged close to each other and connected to the drain of the transistor Tr 2
  • the signal line (drain line) 10 is extended to a desired position for wiring.
  • the signal line between the gates (gate line) 11 and the signal line between the sources (source line) 12 must be shortened. Can be. As a result, the distributed resistance generated on the source line 12 can be reduced to a negligible level, and a voltage drop on the source line 12 can be suppressed.
  • the sources of the transistors Trl, Tr2 are commonly connected to the same power supply VDD via the common node A located at substantially the same distance.
  • the two source potentials can be made almost exactly the same magnitude. Therefore, it is possible to eliminate irregularities in the source potentials of the transistors Tr 1 and Tr 2 and to maintain a good current mirror balance.
  • FIG. 4 shows the current mirror circuit according to the present embodiment on a CMOS integrated circuit.
  • FIG. 8 is a diagram illustrating another example of a layout configuration in FIG. Karen Tomi error circuit shown in FIG. 4, reference current I flowing through the p MOS transistor T r 1, with an equal correct the current I 2, I 3> 1 4, each P MO S transistor T r 2 ⁇ T r 4 It is a circuit for flowing.
  • a pair of current mirror circuits (three pairs of pMOS transistors Tr1 are also used) is configured.
  • the gate of the pMOS transistor Tr1 and the gates of the other three pMOS transistors Tr2 to Tr4 are connected to each other.
  • the sources of the pMOS transistors Tr1 to Tr4 are commonly connected to the same power supply VDD via a common node B.
  • the drain of the pMOS transistor Tr1 is grounded via the resistor R, and the drains of the other three pMOS transistors Tr2 to Tr4 are connected to desired positions.
  • three pairs of pMOS transistors Trl to Tr4 constituting the current mirror are arranged close to each other and connected to the drains of transistors Tr2 to Tr4.
  • Each of the drain lines 10 is extended to a desired position for wiring.
  • the wiring length of the source line 12 connecting the three pairs of pMOS transistors Trl to Tr4 can be reduced.
  • the distributed resistance generated on the source line 12 can be reduced to a negligible level, and the voltage drop on the source line 12 can be suppressed.
  • the irregularities in the source potential are eliminated and the current mirror circuit is reduced. Can be kept in a good balance.
  • FIG. 5 is a diagram illustrating an application example of the above-described current mirror circuit.
  • the configuration of a multi-stage amplifier applied to various wireless communication devices such as AM or FM radio receivers, television receivers, mobile phones, short-range wireless data communication technology bluetooth, and wireless LANs. Is shown.
  • components having the same functions as the components shown in FIG. 4 are denoted by the same reference numerals.
  • the multistage amplifier shown in Fig. 5 is composed of n stages of differential amplifiers connected in multiple stages from the input side to the output side.
  • First-stage differential amplifier circuit arranged in the input stage is configured to include two resistors R n, R 12 and two p MO S transistor Q n, a differential pair consisting of Q 12 Metropolitan.
  • the second-stage differential amplifier is configured to include a differential pair including two transistors R 21 and R 22 and two pMOS transistors Q 2 and Q 22 as in the first-stage. .
  • the third to n-th stages (not shown) have the same configuration.
  • each differential pair the sources of the two transistors Q; Q i2 are commonly connected to each other, and these common sources are connected to the pMOS transistors Tr 2, Tr 3, Tr 4 ,... Drains are connected.
  • the pMOS transistors Tr2, Ti-3, Tr4, ... function as switching elements of each differential pair.
  • Another pMOS transistor Tr1 that forms a current mirror circuit together with each transistor Tr2, Tr3, Tr4,... are grounded via a resistor R, and the source is connected to one end of the constant current source circuit 30.
  • the other end of the constant current source circuit 30 is connected to the power supply VDD.
  • Each differential pair has the same current I as flowing through the constant current source circuit 30 through the pMOS transistor Tf2, Tr3, Tr4, ... composed of a current mirror circuit.
  • I 2 , I 3 , I 4 > are supplied respectively.
  • the signal input to the bases of the transistors Q 1, Q 2, and Q 12 of the first-stage differential amplifier is amplified by a predetermined level and output.
  • the signal amplified and output here is input to the bases of the transistors Q 2 and Q 22 of the second-stage differential amplifier, and further amplified and output by the second-stage differential amplifier. Is done.
  • the signals are sequentially amplified by the differential amplifiers at each stage. As a result, the amplitude of the input signal to the first-stage differential amplifier increases in the subsequent stage, and finally an output signal amplified to a predetermined level is obtained.
  • the pMOS transistors Tr:! To Tr4 that constitute the current mirror are arranged close to each other and connected to the drains of the transistors Tr2 to Tr4.
  • the drain line 10 is extended to the position of the differential pair in each stage and wired. Therefore, the source line 12 connecting the transistors Tr 1 to Tr 4 can be shortened.
  • the distributed resistance generated on the source line 12 can be reduced to a negligible level, and the voltage drop on the source line 12 can be suppressed. Therefore, it is possible to maintain a good balance of the current mirror by eliminating irregularities in the source potentials at each of the transistors 1 to 1 to 4 so that the current mirror circuit having such characteristics can be used in a wireless communication device.
  • good input / output characteristics The linearity can be ensured.
  • the wiring length from each of the transistors Tr 1 to Tr 4 to the power supply VDD and the constant current source circuit 30 is short, it is necessary to reduce the impedance of the connection between the transistors and realize low-noise power supply. The operation can be stabilized even when handling high-frequency signals.
  • a PMOS transistor is used as a transistor element constituting the current mirror circuit.
  • an nMOS transistor may be used.
  • the number of the transistor elements constituting the current mirror circuit shown in the above embodiment is merely an example, and the present invention is not limited to this.
  • FIG. 5 shows a multistage amplifier as an application example of a current mirror circuit, but the present invention is not limited to this, and any application using a current mirror circuit is possible.
  • a plurality of MOS transistors constituting a current mirror are arranged close to each other, and a signal line connected to the drains of the plurality of MOS transistors is moved to a desired position. Since the wiring is used, the wiring length of the signal line connecting the source of each MOS transistor and element can be shortened. As a result, the distributed resistance generated on the source line can be reduced to a negligible level, so that the voltage drop on the source line is suppressed and the source resistance of each MOS transistor is reduced. The difference between the potentials can be prevented. Therefore, even when the circuit arrangement of the current mirror is far away from the chip layout, the current mirror can be well balanced. In particular, when the current mirror circuit of the present invention is applied to an RF circuit such as a mobile phone, the high-frequency characteristics can be improved.
  • the sources of a plurality of MOS transistor elements are commonly connected to the same power supply, so that the source potential of each MOS transistor can be more accurately aligned.
  • the balance of the current mirror can be better maintained.
  • the present invention is useful for a MOS integrated circuit capable of maintaining a good balance of a current mirror even when the circuit arrangement of the power mirror is far away from the chip layout.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)

Abstract

L'invention concerne un circuit MOS intégré, équipé d'un miroir de courant, comprenant des transistors pMOS (Tr1, Tr2) disposés proches l'un de l'autre. La longueur de câblage de chaque transistor (Tr1, Tr2) est raccourcie en raison de l'extension de la ligne de drain de chaque transistor (Tr1, Tr2) dans une position recherchée de façon qu'une résistance distribuée, générée sur la ligne de source (12), soit réduite à un niveau négligeable, supprimant ainsi une chute de tension sur la ligne de source (12) et éliminant un potentiel de source accidentel.
PCT/JP2002/006970 2001-07-23 2002-07-10 Circuit mos integre a miroir de courant Ceased WO2003010616A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001-220878 2001-07-23
JP2001220878A JP2003037456A (ja) 2001-07-23 2001-07-23 カレントミラーを備えたｍｏｓ集積回路

Publications (1)

Publication Number Publication Date
WO2003010616A1 true WO2003010616A1 (fr) 2003-02-06

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PCT/JP2002/006970 Ceased WO2003010616A1 (fr) 2001-07-23 2002-07-10 Circuit mos integre a miroir de courant

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JP (1) JP2003037456A (fr)
WO (1) WO2003010616A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101180729B (zh) * 2005-05-26 2011-11-30 Nxp股份有限公司 电子器件及其制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0749722A (ja) * 1993-08-05 1995-02-21 Nec Kansai Ltd 定電流回路
JPH09275320A (ja) * 1996-04-05 1997-10-21 Sony Corp 基準電流源回路とこれを備えた電子装置
JP2000269426A (ja) * 1999-03-17 2000-09-29 Toshiba Corp ミラー回路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0749722A (ja) * 1993-08-05 1995-02-21 Nec Kansai Ltd 定電流回路
JPH09275320A (ja) * 1996-04-05 1997-10-21 Sony Corp 基準電流源回路とこれを備えた電子装置
JP2000269426A (ja) * 1999-03-17 2000-09-29 Toshiba Corp ミラー回路

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