WO2003015102A1 - Synchronous semiconductor storage device module and its control method, information device - Google Patents

Synchronous semiconductor storage device module and its control method, information device Download PDF

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Publication number
WO2003015102A1
WO2003015102A1 PCT/JP2002/007880 JP0207880W WO03015102A1 WO 2003015102 A1 WO2003015102 A1 WO 2003015102A1 JP 0207880 W JP0207880 W JP 0207880W WO 03015102 A1 WO03015102 A1 WO 03015102A1
Authority
WO
WIPO (PCT)
Prior art keywords
address
burst
matched
updates
control method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2002/007880
Other languages
English (en)
French (fr)
Inventor
Hiroshi Okumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to KR1020047001932A priority Critical patent/KR100630827B1/ko
Priority to US10/486,124 priority patent/US20040236898A1/en
Priority to EP02746157A priority patent/EP1422722A4/en
Priority to CN028198352A priority patent/CN1565034B/zh
Publication of WO2003015102A1 publication Critical patent/WO2003015102A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1027—Static column decode serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled bit line addresses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Static Random-Access Memory (AREA)
PCT/JP2002/007880 2001-08-07 2002-08-01 Synchronous semiconductor storage device module and its control method, information device Ceased WO2003015102A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020047001932A KR100630827B1 (ko) 2001-08-07 2002-08-01 동기형 반도체 기억장치 모듈 및 그 제어방법, 정보기기
US10/486,124 US20040236898A1 (en) 2001-08-07 2002-08-01 Synchronous semiconductor storage device module and its control method, information device
EP02746157A EP1422722A4 (en) 2001-08-07 2002-08-01 SYNCHRONOUS TYPE SEMICONDUCTOR STORAGE UNIT MODULE, CONTROL METHOD THEREFOR, AND COMPUTER SYSTEM
CN028198352A CN1565034B (zh) 2001-08-07 2002-08-01 同步型半导体存储器设备模块及其控制方法与信息设备

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001-239377 2001-08-07
JP2001239377A JP3932166B2 (ja) 2001-08-07 2001-08-07 同期型半導体記憶装置モジュールおよびその制御方法、情報機器

Publications (1)

Publication Number Publication Date
WO2003015102A1 true WO2003015102A1 (en) 2003-02-20

Family

ID=19070143

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2002/007880 Ceased WO2003015102A1 (en) 2001-08-07 2002-08-01 Synchronous semiconductor storage device module and its control method, information device

Country Status (7)

Country Link
US (1) US20040236898A1 (ja)
EP (1) EP1422722A4 (ja)
JP (1) JP3932166B2 (ja)
KR (1) KR100630827B1 (ja)
CN (1) CN1565034B (ja)
TW (1) TW569229B (ja)
WO (1) WO2003015102A1 (ja)

Cited By (1)

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JP2021174561A (ja) * 2020-04-20 2021-11-01 ウィンボンド エレクトロニクス コーポレーション 半導体記憶装置

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US20050273560A1 (en) * 2004-06-03 2005-12-08 Hulbert Jared E Method and apparatus to avoid incoherency between a cache memory and flash memory
KR100624960B1 (ko) 2004-10-05 2006-09-15 에스티마이크로일렉트로닉스 엔.브이. 반도체 메모리 장치 및 이의 패키지 및 이를 이용한메모리 카드
JP4945125B2 (ja) * 2005-12-21 2012-06-06 ラピスセミコンダクタ株式会社 メモリ制御装置
US20070162713A1 (en) * 2006-01-09 2007-07-12 Josef Schnell Memory having status register read function
KR100684909B1 (ko) 2006-01-24 2007-02-22 삼성전자주식회사 읽기 에러를 방지할 수 있는 플래시 메모리 장치
KR100721021B1 (ko) * 2006-02-15 2007-05-23 삼성전자주식회사 반도체 메모리 장치의 버스트 리드 회로 및 버스트 데이터출력 방법
US7701764B2 (en) * 2006-05-17 2010-04-20 Micron Technology, Inc. Apparatus and method for reduced peak power consumption during common operation of multi-NAND flash memory devices
KR100798792B1 (ko) * 2006-12-27 2008-01-28 주식회사 하이닉스반도체 반도체 메모리 장치
KR100813627B1 (ko) * 2007-01-04 2008-03-14 삼성전자주식회사 멀티-비트 데이터를 저장할 수 있는 플래시 메모리 장치를제어하는 메모리 제어기와 그것을 포함한 메모리 시스템
JP4325685B2 (ja) 2007-02-21 2009-09-02 セイコーエプソン株式会社 メモリを制御するメモリコントローラ、メモリモジュール、メモリの制御方法、および、コンピュータ。
JP5103663B2 (ja) * 2007-09-27 2012-12-19 ルネサスエレクトロニクス株式会社 メモリ制御装置
JP4910117B2 (ja) * 2008-04-04 2012-04-04 スパンション エルエルシー 積層型メモリ装置
JP5239939B2 (ja) * 2009-02-25 2013-07-17 凸版印刷株式会社 半導体メモリ
CN101882119B (zh) * 2009-05-08 2014-05-14 上海炬力集成电路设计有限公司 与非型闪存控制器及其数据传输方法
JP2011081884A (ja) * 2009-10-09 2011-04-21 Elpida Memory Inc 半導体記憶装置及びこれを備える情報処理システム
JP5577776B2 (ja) * 2010-03-17 2014-08-27 株式会社リコー メモリ制御装置及びマスクタイミング制御方法
JP5513285B2 (ja) * 2010-07-06 2014-06-04 スパンション エルエルシー 不揮発性半導体記憶装置
KR101147696B1 (ko) * 2010-07-21 2012-05-24 윈본드 일렉트로닉스 코포레이션 메모리 칩 및 이를 이용하는 메모리 장치
US9715909B2 (en) 2013-03-14 2017-07-25 Micron Technology, Inc. Apparatuses and methods for controlling data timing in a multi-memory system
US10083728B2 (en) * 2013-09-06 2018-09-25 Mediatek Inc. Memory controller, memory module and memory system
KR101487264B1 (ko) * 2013-10-15 2015-01-28 (주)피델릭스 시리얼 독출 동작의 초기 센싱 오동작을 감소시키는 반도체 메모리 장치 및 그의 시리얼 독출 방법
JP5732160B2 (ja) * 2014-03-27 2015-06-10 スパンション エルエルシー 不揮発性半導体記憶装置の制御方法
JP6363978B2 (ja) * 2015-08-05 2018-07-25 株式会社メガチップス 半導体記憶装置及びその制御方法
KR102339780B1 (ko) * 2015-10-29 2021-12-15 삼성전자주식회사 칩 아이디(id) 발생 회로를 갖는 반도체 장치
JP6232109B1 (ja) * 2016-09-27 2017-11-15 ウィンボンド エレクトロニクス コーポレーション 半導体記憶装置および連続読出し方法
JP6274589B1 (ja) * 2016-09-28 2018-02-07 ウィンボンド エレクトロニクス コーポレーション 半導体記憶装置および連続読出し方法
KR102336666B1 (ko) * 2017-09-15 2021-12-07 삼성전자 주식회사 메모리 장치 및 이를 포함하는 메모리 시스템
CN108595350B (zh) * 2018-01-04 2022-04-05 深圳开阳电子股份有限公司 一种基于axi的数据传输方法和装置
KR102729765B1 (ko) * 2019-12-12 2024-11-13 주식회사 메타씨앤아이 메모리 장치에서 통합 카운터
US11372591B2 (en) * 2020-06-30 2022-06-28 SK Hynix Inc. Memory apparatus, a semiconductor system including the same and an operating method thereof
KR102865309B1 (ko) * 2020-09-03 2025-09-30 삼성전자주식회사 반도체 메모리 장치 및 그것의 동작 방법
CN115834995B (zh) * 2021-09-15 2024-11-01 广州印芯半导体技术有限公司 线性图像传感器以及图像传感方法
US12517679B2 (en) * 2022-01-12 2026-01-06 Taiwan Semiconductor Manufacturing Company Ltd. Memory interface
CN114637711B (zh) * 2022-03-31 2024-06-18 深圳市洲明科技股份有限公司 芯片的控制方法、控制数据传输方法、装置和计算机设备

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JPH05282882A (ja) * 1991-12-19 1993-10-29 Toshiba Corp 不揮発性半導体メモリ
JPH06149662A (ja) * 1992-11-02 1994-05-31 Toshiba Corp Ｒｏｍバースト転送の連続読みだし拡大方式およびその方式を用いたｒｏｍ内蔵型マイクロコンピュータシステム
JPH11203860A (ja) * 1998-01-07 1999-07-30 Nec Corp 半導体記憶装置
JP2001184874A (ja) * 1999-12-21 2001-07-06 Sony Corp 半導体記憶装置の読み出し方法および半導体記憶装置

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JPH06149662A (ja) * 1992-11-02 1994-05-31 Toshiba Corp Ｒｏｍバースト転送の連続読みだし拡大方式およびその方式を用いたｒｏｍ内蔵型マイクロコンピュータシステム
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Cited By (2)

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Publication number Priority date Publication date Assignee Title
JP2021174561A (ja) * 2020-04-20 2021-11-01 ウィンボンド エレクトロニクス コーポレーション 半導体記憶装置
US11430495B2 (en) 2020-04-20 2022-08-30 Winbond Electronics Corp. Semiconductor storing apparatus including multiple chips and continous readout method

Also Published As

Publication number Publication date
CN1565034B (zh) 2010-05-26
EP1422722A4 (en) 2006-02-15
TW569229B (en) 2004-01-01
CN1565034A (zh) 2005-01-12
EP1422722A1 (en) 2004-05-26
US20040236898A1 (en) 2004-11-25
JP3932166B2 (ja) 2007-06-20
KR100630827B1 (ko) 2006-10-02
JP2003051194A (ja) 2003-02-21
KR20040030944A (ko) 2004-04-09

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