WO2003015152A3 - Procede de fabrication d'un dispositif semi-conducteur dote d'une memoire non-volatile contenant une cellule de memoire a grille d'acces et a grille de commande et une zone de stockage de charge - Google Patents

Procede de fabrication d'un dispositif semi-conducteur dote d'une memoire non-volatile contenant une cellule de memoire a grille d'acces et a grille de commande et une zone de stockage de charge Download PDF

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Publication number
WO2003015152A3
WO2003015152A3 PCT/IB2002/002040 IB0202040W WO03015152A3 WO 2003015152 A3 WO2003015152 A3 WO 2003015152A3 IB 0202040 W IB0202040 W IB 0202040W WO 03015152 A3 WO03015152 A3 WO 03015152A3
Authority
WO
WIPO (PCT)
Prior art keywords
gate
conductive layer
gate structure
side walls
semiconductor body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2002/002040
Other languages
English (en)
Other versions
WO2003015152A2 (fr
Inventor
Michiel Slotboom
Franciscus P Widdershoven
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Priority to KR10-2004-7001760A priority Critical patent/KR20040023716A/ko
Priority to JP2003519985A priority patent/JP2004538638A/ja
Priority to US10/485,496 priority patent/US6984558B2/en
Publication of WO2003015152A2 publication Critical patent/WO2003015152A2/fr
Anticipated expiration legal-status Critical
Publication of WO2003015152A3 publication Critical patent/WO2003015152A3/fr
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H10D30/683—Floating-gate IGFETs having only two programming levels programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6892—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0147—Manufacturing their gate sidewall spacers

Landscapes

  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un dispositif semi-conducteur comprenant un corps semi-conducteur (1) situé sur une surface (2) pourvue d'une mémoire non volatile renfermant, d'une part, une cellule de mémoire avec une structure de grille (4) à grille d'accès (19) et une structure de grille (3) à grille de commande (5) et, d'autre part, une zone de stockage de charge, telle qu'une grille flottante (6), située entre la grille de commande (5) et le corps semi-conducteur (1). Selon ce procédé, à la surface (2) du corps semi-conducteur (1), une première structure desdites structures de grille est formée avec des parois latérales (10) s'étendant pratiquement perpendiculairement à la surface, une couche conductrice est formée par dépôt (13) sur la structure de grille et à proximité de celle-ci, la couche conductrice est soumise à un traitement de planarisation, jusqu'à ce que la première structure de grille soit exposée, et la couche conductrice ainsi planarisée est imprimée de manière à former au moins une partie de l'autre structure de grille adjacente à la première structure de grille. Cette impression de la couche conductrice planarisée est réalisée, de telle manière que la couche conductrice planarisée (14) est décapée pour exposer une portion supérieure (15) des parois latérales de la première structure de grille, une entretoise (18) est formée sur la portion supérieure exposée (15) des parois latérales de la première structure de grille et la couche conductrice (16) est décapée de manière anisotrope, au moyen de l'entretoise en tant que masque. On peut ainsi produire des cellules de mémoire très petites.
PCT/IB2002/002040 2001-08-06 2002-06-04 Procede de fabrication d'un dispositif semi-conducteur dote d'une memoire non-volatile contenant une cellule de memoire a grille d'acces et a grille de commande et une zone de stockage de charge Ceased WO2003015152A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR10-2004-7001760A KR20040023716A (ko) 2001-08-06 2002-06-04 반도체 디바이스 제조 방법
JP2003519985A JP2004538638A (ja) 2001-08-06 2002-06-04 アクセスゲートと制御ゲートと電荷蓄積領域とを有するメモリセルを含む不揮発性メモリを備えた半導体装置の製造方法
US10/485,496 US6984558B2 (en) 2001-08-06 2002-06-04 Method of manufacturing a semiconductor device with non-volatile memory comprising a memory cell with an access gate and with a control gate and a charge storage region

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
EP01203001 2001-08-06
EP01203000 2001-08-06
EP01203000.3 2001-08-06
EP01203001.1 2001-08-06
EP02076743.0 2002-05-02
EP02076743 2002-05-02

Publications (2)

Publication Number Publication Date
WO2003015152A2 WO2003015152A2 (fr) 2003-02-20
WO2003015152A3 true WO2003015152A3 (fr) 2004-05-27

Family

ID=27224300

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2002/002040 Ceased WO2003015152A2 (fr) 2001-08-06 2002-06-04 Procede de fabrication d'un dispositif semi-conducteur dote d'une memoire non-volatile contenant une cellule de memoire a grille d'acces et a grille de commande et une zone de stockage de charge

Country Status (5)

Country Link
US (1) US6984558B2 (fr)
JP (1) JP2004538638A (fr)
KR (1) KR20040023716A (fr)
TW (1) TW564524B (fr)
WO (1) WO2003015152A2 (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100859081B1 (ko) * 2001-08-06 2008-09-17 엔엑스피 비 브이 반도체 디바이스 제조 방법
US7154779B2 (en) 2004-01-21 2006-12-26 Sandisk Corporation Non-volatile memory cell using high-k material inter-gate programming
KR100678479B1 (ko) * 2005-07-20 2007-02-02 삼성전자주식회사 3-트랜지스터 메모리 셀을 갖는 비휘발성 메모리 소자들 및그 제조방법들
US7928005B2 (en) * 2005-09-27 2011-04-19 Advanced Micro Devices, Inc. Method for forming narrow structures in a semiconductor device
JP4528718B2 (ja) * 2005-12-27 2010-08-18 株式会社東芝 不揮発性半導体メモリの製造方法
KR100697048B1 (ko) * 2006-08-31 2007-03-20 이순익 노면 미끄럼방지홈 시공방법 및 시공장치
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
JP2009212399A (ja) * 2008-03-05 2009-09-17 Nec Electronics Corp 不揮発性半導体記憶装置及びその製造方法
JP2009212398A (ja) * 2008-03-05 2009-09-17 Nec Electronics Corp 不揮発性半導体記憶装置及びその製造方法
US8097911B2 (en) * 2008-12-31 2012-01-17 Intel Corporation Etch stop structures for floating gate devices
US9368644B2 (en) * 2013-12-20 2016-06-14 Cypress Semiconductor Corporation Gate formation memory by planarization
CN110854184B (zh) * 2018-08-03 2023-04-07 联华电子股份有限公司 半导体元件及其制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0411573A2 (fr) * 1989-07-31 1991-02-06 Kabushiki Kaisha Toshiba Dispositif semi-conducteur de mémoire rÀ©manente et méthode pour sa mise en oeuvre
US5541130A (en) * 1995-06-07 1996-07-30 International Business Machines Corporation Process for making and programming a flash memory array
JP2001085541A (ja) * 1999-09-10 2001-03-30 Hitachi Ltd 半導体集積回路装置およびその製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3973819B2 (ja) * 1999-03-08 2007-09-12 株式会社東芝 半導体記憶装置およびその製造方法
KR100308128B1 (ko) * 1999-08-24 2001-11-01 김영환 비휘발성 메모리 소자 및 그의 제조 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0411573A2 (fr) * 1989-07-31 1991-02-06 Kabushiki Kaisha Toshiba Dispositif semi-conducteur de mémoire rÀ©manente et méthode pour sa mise en oeuvre
US5541130A (en) * 1995-06-07 1996-07-30 International Business Machines Corporation Process for making and programming a flash memory array
JP2001085541A (ja) * 1999-09-10 2001-03-30 Hitachi Ltd 半導体集積回路装置およびその製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 20 10 July 2001 (2001-07-10) *

Also Published As

Publication number Publication date
US20040175886A1 (en) 2004-09-09
TW564524B (en) 2003-12-01
US6984558B2 (en) 2006-01-10
WO2003015152A2 (fr) 2003-02-20
KR20040023716A (ko) 2004-03-18
JP2004538638A (ja) 2004-12-24

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