WO2003017498A3 - Procede et dispositif d'entrelacement et de desentrelacement dans un processus de turbodecodage - Google Patents

Procede et dispositif d'entrelacement et de desentrelacement dans un processus de turbodecodage Download PDF

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Publication number
WO2003017498A3
WO2003017498A3 PCT/DE2002/002357 DE0202357W WO03017498A3 WO 2003017498 A3 WO2003017498 A3 WO 2003017498A3 DE 0202357 W DE0202357 W DE 0202357W WO 03017498 A3 WO03017498 A3 WO 03017498A3
Authority
WO
WIPO (PCT)
Prior art keywords
interlacing
deinterlacing
decoding process
turbo decoding
hardware circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/DE2002/002357
Other languages
German (de)
English (en)
Other versions
WO2003017498A2 (fr
Inventor
Burkhard Becker
Thuyen Le
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of WO2003017498A2 publication Critical patent/WO2003017498A2/fr
Publication of WO2003017498A3 publication Critical patent/WO2003017498A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6569—Implementation on processors, e.g. DSPs, or software implementations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
    • H03M13/2714—Turbo interleaver for 3rd generation partnership project [3GPP] universal mobile telecommunications systems [UMTS], e.g. as defined in technical specification TS 25.212
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/276—Interleaving address generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)

Abstract

L'invention concerne un procédé de mise en oeuvre d'un processus d'entrelacement et/ou de désentrelacement dans un turbodécodage utilisant un processeur et un circuit matériel, procédé caractérisé en ce que l'information d'entrelacement et/ou de désentrelacement est calculée dans le processeur (1), et en ce que le circuit matériel (3) est ensuite programmé avec l'information calculée d'entrelacement et de désentrelacement. Dans une autre étape, le processus d'entrelacement et/ou de désentrelacement est effectué dans le circuit matériel (3).
PCT/DE2002/002357 2001-08-06 2002-06-27 Procede et dispositif d'entrelacement et de desentrelacement dans un processus de turbodecodage Ceased WO2003017498A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2001138566 DE10138566A1 (de) 2001-08-06 2001-08-06 Verfahren und Vorrichtung zur Durchführung der Ver- und Entschachtelung bei einer Turbo-Dekodierung
DE10138566.8 2001-08-06

Publications (2)

Publication Number Publication Date
WO2003017498A2 WO2003017498A2 (fr) 2003-02-27
WO2003017498A3 true WO2003017498A3 (fr) 2003-10-30

Family

ID=7694561

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2002/002357 Ceased WO2003017498A2 (fr) 2001-08-06 2002-06-27 Procede et dispositif d'entrelacement et de desentrelacement dans un processus de turbodecodage

Country Status (2)

Country Link
DE (1) DE10138566A1 (fr)
WO (1) WO2003017498A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10306302A1 (de) * 2003-02-14 2004-08-26 Infineon Technologies Ag Verfahren und Schaltung zur Adressgenerierung von Pseudo-Zufalls-Interleavern oder -Deinterleavern

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5659580A (en) * 1994-11-29 1997-08-19 Lucent Technologies Inc. Data interleaver for use with mobile communication systems and having a contiguous counter and an address twister
EP1650873B1 (fr) * 1999-02-26 2011-05-11 Fujitsu Ltd. Dispositif de turbo decodage et dispositif de turbo entrelacement et de turbo desentrelacement

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
"3RD GENERATION PARTNERSHIP PROJECT (3GPP);TECHNICAL SPECIFICATION GROUP RADIO ACCESS NETWORK MULTIPLEXING AND CHANNEL CODING (FDD) (3G TS 25.212 VERSION 3.0.0)", 3G TS 25 212 V3.0.0, XX, XX, October 1999 (1999-10-01), pages COMPLETE54, XP002149187 *
GATHERER A ET AL: "DSP-BASED ARCHITECTURES FOR MOBILE COMMUNICATIONS: PAST, PRESENT AND FUTURE", IEEE COMMUNICATIONS MAGAZINE, IEEE SERVICE CENTER. PISCATAWAY, N.J, US, vol. 38, no. 1, January 2000 (2000-01-01), pages 84 - 90, XP000908341, ISSN: 0163-6804 *
S. MORRIS: "Signal processing demands", WIRELESS SYSTEMS DESIGN, November 1999 (1999-11-01), pages 1 - 5, XP002229584, Retrieved from the Internet <URL:http://www.wsdmag.com/Globals/PlanetEE/Content/123.pdf> [retrieved on 20030131] *

Also Published As

Publication number Publication date
DE10138566A1 (de) 2003-03-06
WO2003017498A2 (fr) 2003-02-27

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