WO2003019640A3 - Procede de mise en forme d'une couche mince et de formation d'une prise de contact - Google Patents

Procede de mise en forme d'une couche mince et de formation d'une prise de contact Download PDF

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Publication number
WO2003019640A3
WO2003019640A3 PCT/FR2002/002926 FR0202926W WO03019640A3 WO 2003019640 A3 WO2003019640 A3 WO 2003019640A3 FR 0202926 W FR0202926 W FR 0202926W WO 03019640 A3 WO03019640 A3 WO 03019640A3
Authority
WO
WIPO (PCT)
Prior art keywords
thin layer
layer
forming
etched
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/FR2002/002926
Other languages
English (en)
Other versions
WO2003019640A2 (fr
Inventor
Nicolas Sillon
Philippe Vasseur
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat à l'Énergie Atomique et Aux Énergies Alternatives
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Publication of WO2003019640A2 publication Critical patent/WO2003019640A2/fr
Publication of WO2003019640A3 publication Critical patent/WO2003019640A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group IV materials or Group III-V materials
    • H10P50/692—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group IV materials or Group III-V materials characterised by their composition, e.g. multilayer masks or materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group IV materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group IV materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/695—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group IV materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/405—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their composition, e.g. multilayer masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

La présente invention concerne un procédé de mise en forme d'une couche mince (12), comprenant les étapes successives suivantes : le dépôt sur la couche mince d'une couche (14) en un métal différent du matériau de la couche mince, susceptible d'être gravé par laser, la gravure dans la couche de métal d'au moins une ouverture (20) selon un motif coïncidant avec au moins ne partie de la couche mince devant être éliminée, la gravure ayant lieu par soumission locale de la couche de métal à un faisceau laser, et la gravure localisée de la couche mince sous-jacente, selon le motif, en utilisant la couche de métal comme masque de gravure. Application à la réalisation de prises de contact.
PCT/FR2002/002926 2001-08-24 2002-08-22 Procede de mise en forme d'une couche mince et de formation d'une prise de contact Ceased WO2003019640A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0111098A FR2828957A1 (fr) 2001-08-24 2001-08-24 Procede de mise en forme d'une couche mince et de formation d'une prise de contact
FR01/11098 2001-08-24

Publications (2)

Publication Number Publication Date
WO2003019640A2 WO2003019640A2 (fr) 2003-03-06
WO2003019640A3 true WO2003019640A3 (fr) 2003-12-18

Family

ID=8866728

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2002/002926 Ceased WO2003019640A2 (fr) 2001-08-24 2002-08-22 Procede de mise en forme d'une couche mince et de formation d'une prise de contact

Country Status (2)

Country Link
FR (1) FR2828957A1 (fr)
WO (1) WO2003019640A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009057881A1 (de) * 2009-12-11 2011-06-16 Centrothem Photovoltaics Ag Verfahren zur Laserstrukturierung eines transparenten Mediums und Verwendung des Verfahrens bei der Herstellung eines Halbleiterbauelements

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4542578A (en) * 1983-03-18 1985-09-24 Sanyo Electric Co., Ltd. Method of manufacturing photovoltaic device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4542578A (en) * 1983-03-18 1985-09-24 Sanyo Electric Co., Ltd. Method of manufacturing photovoltaic device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JAAFAR M A S ET AL: "A PLATED THROUGH-HOLE INTERCONNECT TECHNOLOGY IN SILICON", EXTENDED ABSTRACTS, ELECTROCHEMICAL SOCIETY. PRINCETON, NEW JERSEY, US, vol. 94/2, 1992, pages 490, XP000550868, ISSN: 0160-4619 *

Also Published As

Publication number Publication date
FR2828957A1 (fr) 2003-02-28
WO2003019640A2 (fr) 2003-03-06

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