WO2003019649A3 - Leiterbahnanordnung und verfahren zum herstellen einer leiterbahnanordnung - Google Patents

Leiterbahnanordnung und verfahren zum herstellen einer leiterbahnanordnung Download PDF

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Publication number
WO2003019649A3
WO2003019649A3 PCT/DE2002/002946 DE0202946W WO03019649A3 WO 2003019649 A3 WO2003019649 A3 WO 2003019649A3 DE 0202946 W DE0202946 W DE 0202946W WO 03019649 A3 WO03019649 A3 WO 03019649A3
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
conductor arrangement
strip conductor
producing
buffer layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/DE2002/002946
Other languages
English (en)
French (fr)
Other versions
WO2003019649A8 (de
WO2003019649A2 (de
Inventor
Guenther Schindler
Werner Pamler
Zvonimir Gabric
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to US10/487,190 priority Critical patent/US7033926B2/en
Priority to EP02754521A priority patent/EP1419525A2/de
Publication of WO2003019649A2 publication Critical patent/WO2003019649A2/de
Publication of WO2003019649A3 publication Critical patent/WO2003019649A3/de
Publication of WO2003019649A8 publication Critical patent/WO2003019649A8/de
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/072—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/46—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising air gaps

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

Eine Leiterbahnanordnung (100) weist auf ein Substrat (101) aus einem ersten Isolationsmaterial mit einer Substratoberfläche (102), mindestens zwei nebeneinander in dem Substrat (101) angeordnete Leiterbahnen (103), mit einer Pufferschicht (104) aus einem zweiten Isolationsmaterial über dem Substrat (101) und mit einer zu der Substratoberfläche (102) parallelen Pufferschichtoberfläche (105), mindestens einen zwischen den Leiterbahnen (103) angeordneten, bezüglich der Pufferschichtoberfläche (105) tiefer als die Leiterbahnen (103) in das Substrat (101) hineinragenden Hohlraum (107), und eine über der Pufferschicht (104) angeordnete Deckschicht (111) aus einem dritten Isolationsmaterial, welche den Hohlraum (107) vollständig zur Pufferschichtoberfläche (105) hin abschliesst.
PCT/DE2002/002946 2001-08-20 2002-08-09 Leiterbahnanordnung und verfahren zum herstellen einer leiterbahnanordnung Ceased WO2003019649A2 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10/487,190 US7033926B2 (en) 2001-08-20 2002-08-09 Strip conductor arrangement and method for producing a strip conductor arrangement
EP02754521A EP1419525A2 (de) 2001-08-20 2002-08-09 Leiterbahnanordnung und verfahren zum herstellen einer leiterbahnanordnung

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10140754.8 2001-08-20
DE10140754A DE10140754A1 (de) 2001-08-20 2001-08-20 Leiterbahnanordnung und Verfahren zum Herstellen einer Leiterbahnanordnung

Publications (3)

Publication Number Publication Date
WO2003019649A2 WO2003019649A2 (de) 2003-03-06
WO2003019649A3 true WO2003019649A3 (de) 2003-08-07
WO2003019649A8 WO2003019649A8 (de) 2003-11-13

Family

ID=7696008

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2002/002946 Ceased WO2003019649A2 (de) 2001-08-20 2002-08-09 Leiterbahnanordnung und verfahren zum herstellen einer leiterbahnanordnung

Country Status (5)

Country Link
US (1) US7033926B2 (de)
EP (1) EP1419525A2 (de)
DE (1) DE10140754A1 (de)
TW (1) TW571422B (de)
WO (1) WO2003019649A2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7361991B2 (en) * 2003-09-19 2008-04-22 International Business Machines Corporation Closed air gap interconnect structure
US7071532B2 (en) * 2003-09-30 2006-07-04 International Business Machines Corporation Adjustable self-aligned air gap dielectric for low capacitance wiring
DE102004003337A1 (de) * 2004-01-22 2005-08-18 Infineon Technologies Ag Plasmaangeregtes chemisches Gasphasenabscheide-Verfahren, Silizium-Sauerstoff-Stickstoff-haltiges Material und Schicht-Anordnung
DE102004050391B4 (de) 2004-10-15 2007-02-08 Infineon Technologies Ag Verfahren zum Herstellen einer Schicht-Anordnung und Schicht-Anordnung
DE102005039323B4 (de) * 2005-08-19 2009-09-03 Infineon Technologies Ag Leitbahnanordnung sowie zugehöriges Herstellungsverfahren
US20070090433A1 (en) * 2005-10-26 2007-04-26 International Business Machines Corporation Isolation collar void and methods of forming the same
US7649239B2 (en) * 2006-05-04 2010-01-19 Intel Corporation Dielectric spacers for metal interconnects and method to form the same
US7772702B2 (en) * 2006-09-21 2010-08-10 Intel Corporation Dielectric spacers for metal interconnects and method to form the same
US7973409B2 (en) 2007-01-22 2011-07-05 International Business Machines Corporation Hybrid interconnect structure for performance improvement and reliability enhancement
US7871923B2 (en) * 2007-01-26 2011-01-18 Taiwan Semiconductor Maufacturing Company, Ltd. Self-aligned air-gap in interconnect structures
US20090081862A1 (en) * 2007-09-24 2009-03-26 Taiwan Semiconductor Manufacturing Co., Ltd. Air gap structure design for advanced integrated circuit technology
US8399350B2 (en) * 2010-02-05 2013-03-19 International Business Machines Corporation Formation of air gap with protection of metal lines
US8497203B2 (en) 2010-08-13 2013-07-30 International Business Machines Corporation Semiconductor structures and methods of manufacture
KR101600217B1 (ko) 2011-12-30 2016-03-04 인텔 코포레이션 자기-폐쇄 비대칭 상호연결 구조
US8772938B2 (en) 2012-12-04 2014-07-08 Intel Corporation Semiconductor interconnect structures
TWI493754B (zh) * 2013-07-18 2015-07-21 Univ Nat Cheng Kung Luminescent diodes with interfacial periodic structure
US10157778B2 (en) 2016-05-31 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and manufacturing method thereof
JP6685945B2 (ja) * 2017-01-31 2020-04-22 キオクシア株式会社 半導体装置およびその製造方法
US11302662B2 (en) 2020-05-01 2022-04-12 Nanya Technology Corporation Semiconductor package with air gap and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5510645A (en) * 1993-06-02 1996-04-23 Motorola, Inc. Semiconductor structure having an air region and method of forming the semiconductor structure
US5792706A (en) * 1996-06-05 1998-08-11 Advanced Micro Devices, Inc. Interlevel dielectric with air gaps to reduce permitivity
US5908318A (en) * 1995-12-08 1999-06-01 Advanced Micro Devices, Inc. Method of forming low capacitance interconnect structures on semiconductor substrates
EP1026726A2 (de) * 1999-02-05 2000-08-09 Nec Corporation Halbleiterbauelement mit einem insulierenden Film mit Hohlräumen und sein Herstellungsverfahren

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6242336B1 (en) * 1997-11-06 2001-06-05 Matsushita Electronics Corporation Semiconductor device having multilevel interconnection structure and method for fabricating the same
US6888247B2 (en) * 1999-09-03 2005-05-03 United Microelectronics Corp. Interconnect structure with an enlarged air gaps disposed between conductive structures or surrounding a conductive structure within the same
JP2002026016A (ja) * 2000-07-13 2002-01-25 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US6472266B1 (en) * 2001-06-18 2002-10-29 Taiwan Semiconductor Manufacturing Company Method to reduce bit line capacitance in cub drams

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5510645A (en) * 1993-06-02 1996-04-23 Motorola, Inc. Semiconductor structure having an air region and method of forming the semiconductor structure
US5908318A (en) * 1995-12-08 1999-06-01 Advanced Micro Devices, Inc. Method of forming low capacitance interconnect structures on semiconductor substrates
US5792706A (en) * 1996-06-05 1998-08-11 Advanced Micro Devices, Inc. Interlevel dielectric with air gaps to reduce permitivity
EP1026726A2 (de) * 1999-02-05 2000-08-09 Nec Corporation Halbleiterbauelement mit einem insulierenden Film mit Hohlräumen und sein Herstellungsverfahren

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ARNAL V ET AL: "A novel SiO/sub 2/-air gap low k for copper dual damascene interconnect", ADVANCED METALLIZATION CONFERENCE 2000 (AMC 2000). PROCEEDINGS OF THE CONFERENCE, ADVANCED METALLIZATION CONFERENCE 2000 (AMC 2000). PROCEEDINGS OF THE CONFERENCE, SAN DIEGO, CA, USA, 2-5 OCT. 2000, 2000, Warrendale, PA, USA, Mater. Res. Soc, USA, pages 71 - 76, XP002234545, ISBN: 1-55899-574-9 *

Also Published As

Publication number Publication date
US20050079700A1 (en) 2005-04-14
EP1419525A2 (de) 2004-05-19
US7033926B2 (en) 2006-04-25
WO2003019649A8 (de) 2003-11-13
WO2003019649A2 (de) 2003-03-06
TW571422B (en) 2004-01-11
DE10140754A1 (de) 2003-03-27

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