WO2003030260A1 - Semiconductor device and semiconductor device manufacturing method - Google Patents

Semiconductor device and semiconductor device manufacturing method Download PDF

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Publication number
WO2003030260A1
WO2003030260A1 PCT/JP2002/009826 JP0209826W WO03030260A1 WO 2003030260 A1 WO2003030260 A1 WO 2003030260A1 JP 0209826 W JP0209826 W JP 0209826W WO 03030260 A1 WO03030260 A1 WO 03030260A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
connection
connection terminal
device manufacturing
connection portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2002/009826
Other languages
English (en)
French (fr)
Inventor
Atsushi Yoshimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to KR1020047004575A priority Critical patent/KR100628418B1/ko
Priority to EP02772899A priority patent/EP1432034A4/en
Publication of WO2003030260A1 publication Critical patent/WO2003030260A1/ja
Priority to US10/807,311 priority patent/US7141872B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Combinations Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
PCT/JP2002/009826 2001-09-28 2002-09-25 Semiconductor device and semiconductor device manufacturing method Ceased WO2003030260A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020047004575A KR100628418B1 (ko) 2001-09-28 2002-09-25 반도체 장치 및 반도체 장치의 제조 방법
EP02772899A EP1432034A4 (en) 2001-09-28 2002-09-25 SEMICONDUCTOR COMPONENT AND SEMICONDUCTOR COMPONENT MANUFACTURING METHOD
US10/807,311 US7141872B2 (en) 2001-09-28 2004-03-24 Semiconductor device and method of manufacturing semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001-304745 2001-09-28
JP2001304745A JP2003110091A (ja) 2001-09-28 2001-09-28 半導体装置及び半導体装置の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10/807,311 Continuation US7141872B2 (en) 2001-09-28 2004-03-24 Semiconductor device and method of manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
WO2003030260A1 true WO2003030260A1 (en) 2003-04-10

Family

ID=19124623

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2002/009826 Ceased WO2003030260A1 (en) 2001-09-28 2002-09-25 Semiconductor device and semiconductor device manufacturing method

Country Status (7)

Country Link
US (1) US7141872B2 (ja)
EP (1) EP1432034A4 (ja)
JP (1) JP2003110091A (ja)
KR (1) KR100628418B1 (ja)
CN (1) CN100382312C (ja)
TW (1) TW571434B (ja)
WO (1) WO2003030260A1 (ja)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006165320A (ja) * 2004-12-08 2006-06-22 Matsushita Electric Ind Co Ltd 半導体積層モジュールとその製造方法
JP4504798B2 (ja) * 2004-12-16 2010-07-14 パナソニック株式会社 多段構成半導体モジュール
JP4356683B2 (ja) * 2005-01-25 2009-11-04 セイコーエプソン株式会社 デバイス実装構造とデバイス実装方法、液滴吐出ヘッド及びコネクタ並びに半導体装置
JP4520355B2 (ja) * 2005-04-19 2010-08-04 パナソニック株式会社 半導体モジュール
JP2007317861A (ja) * 2006-05-25 2007-12-06 Nec Lcd Technologies Ltd 多層プリント基板及び液晶表示装置
KR101563630B1 (ko) * 2009-09-17 2015-10-28 에스케이하이닉스 주식회사 반도체 패키지
JP5887901B2 (ja) * 2011-12-14 2016-03-16 富士電機株式会社 半導体装置及び半導体装置の製造方法
JP6434494B2 (ja) * 2014-03-10 2018-12-05 三菱重工業株式会社 マルチチップモジュール、オンボードコンピュータ、センサインターフェース基板、及びマルチチップモジュール製造方法
US9659985B2 (en) * 2015-02-17 2017-05-23 Taiwan Semiconductor Manufacturing Company Ltd. Integrated circuit and image sensing device having metal shielding layer and related fabricating method
JP7242342B2 (ja) 2019-02-22 2023-03-20 三菱重工業株式会社 マルチチップモジュール、電子機器およびマルチチップモジュールの製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07106509A (ja) * 1993-09-29 1995-04-21 Nitto Denko Corp 多層構造半導体装置
JP2001068624A (ja) * 1999-08-26 2001-03-16 Toshiba Corp 半導体装置及び半導体装置の製造方法
JP2001230365A (ja) * 2000-02-15 2001-08-24 Sony Corp 多層半導体装置及びその製造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61127153A (ja) * 1984-11-26 1986-06-14 Matsushita Electric Works Ltd 半導体素子の実装構造
US5239448A (en) 1991-10-28 1993-08-24 International Business Machines Corporation Formulation of multichip modules
US5454160A (en) * 1993-12-03 1995-10-03 Ncr Corporation Apparatus and method for stacking integrated circuit devices
US6020629A (en) * 1998-06-05 2000-02-01 Micron Technology, Inc. Stacked semiconductor package and method of fabrication
US6376769B1 (en) * 1999-05-18 2002-04-23 Amerasia International Technology, Inc. High-density electronic package, and method for making same
JP2001177051A (ja) * 1999-12-20 2001-06-29 Toshiba Corp 半導体装置及びシステム装置
JP2001339043A (ja) * 2000-05-30 2001-12-07 Mitsubishi Electric Corp 半導体装置及びそれを用いた半導体モジュール
US6404043B1 (en) * 2000-06-21 2002-06-11 Dense-Pac Microsystems, Inc. Panel stacking of BGA devices to form three-dimensional modules
US6577013B1 (en) * 2000-09-05 2003-06-10 Amkor Technology, Inc. Chip size semiconductor packages with stacked dies
JP2002176137A (ja) * 2000-09-28 2002-06-21 Toshiba Corp 積層型半導体デバイス
JP3655242B2 (ja) * 2002-01-04 2005-06-02 株式会社東芝 半導体パッケージ及び半導体実装装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07106509A (ja) * 1993-09-29 1995-04-21 Nitto Denko Corp 多層構造半導体装置
JP2001068624A (ja) * 1999-08-26 2001-03-16 Toshiba Corp 半導体装置及び半導体装置の製造方法
JP2001230365A (ja) * 2000-02-15 2001-08-24 Sony Corp 多層半導体装置及びその製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1432034A4 *

Also Published As

Publication number Publication date
EP1432034A1 (en) 2004-06-23
CN100382312C (zh) 2008-04-16
KR20040045017A (ko) 2004-05-31
CN1559088A (zh) 2004-12-29
US7141872B2 (en) 2006-11-28
TW571434B (en) 2004-01-11
EP1432034A4 (en) 2007-12-12
KR100628418B1 (ko) 2006-09-28
JP2003110091A (ja) 2003-04-11
US20040238935A1 (en) 2004-12-02

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