WO2003107725A1 - Lampe sans electrode a micro-ondes - Google Patents

Lampe sans electrode a micro-ondes Download PDF

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Publication number
WO2003107725A1
WO2003107725A1 PCT/US2003/016212 US0316212W WO03107725A1 WO 2003107725 A1 WO2003107725 A1 WO 2003107725A1 US 0316212 W US0316212 W US 0316212W WO 03107725 A1 WO03107725 A1 WO 03107725A1
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WO
WIPO (PCT)
Prior art keywords
circuit
microwave
pfc
converter
bulb
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2003/016212
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English (en)
Inventor
James T. Dolan
James E. Simpson
Douglas A. Kirkpatrick
Kjell Lidstrom
Nicklas Skold
Albert G. Tarrillo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fusion Lighting Inc
Original Assignee
Fusion Lighting Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fusion Lighting Inc filed Critical Fusion Lighting Inc
Priority to AU2003241581A priority Critical patent/AU2003241581A1/en
Publication of WO2003107725A1 publication Critical patent/WO2003107725A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J65/00—Lamps without any electrode inside the vessel; Lamps with at least one main electrode outside the vessel
    • H01J65/04—Lamps in which a gas filling is excited to luminesce by an external electromagnetic field or by external corpuscular radiation, e.g. for indicating plasma display panels
    • H01J65/042—Lamps in which a gas filling is excited to luminesce by an external electromagnetic field or by external corpuscular radiation, e.g. for indicating plasma display panels by an external electromagnetic field
    • H01J65/044—Lamps in which a gas filling is excited to luminesce by an external electromagnetic field or by external corpuscular radiation, e.g. for indicating plasma display panels by an external electromagnetic field the field being produced by a separate microwave unit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B41/00—Circuit arrangements or apparatus for igniting or operating discharge lamps
    • H05B41/14—Circuit arrangements
    • H05B41/26—Circuit arrangements in which the lamp is fed by power derived from DC by means of a converter, e.g. by high-voltage DC
    • H05B41/28—Circuit arrangements in which the lamp is fed by power derived from DC by means of a converter, e.g. by high-voltage DC using static converters
    • H05B41/2806—Circuit arrangements in which the lamp is fed by power derived from DC by means of a converter, e.g. by high-voltage DC using static converters with semiconductor devices and specially adapted for lamps without electrodes in the vessel, e.g. surface discharge lamps, electrodeless discharge lamps
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps

Definitions

  • the invention relates generally to microwave electrodeless lamps.
  • the invention relates more specifically to a novel microwave cavity configurations for a lamp and improved mesh screen configurations and materials.
  • Another aspect of the invention relates generally to power supplies.
  • This aspect relates more specifically to a novel power factor correction (PFC) circuit and technique.
  • PFC power factor correction
  • Microwave lamps utilizing cylindrical mesh screens are well known in the art. Most such lamps utilize a relatively narrow screen such that the ratio of the length of the cylindrical cavity to the diameter of the cylindrical cavity is greater than one. In the prior art, a narrow cavity is preferred because it allows the placement of an external reflector closer to the bulb.
  • Using a cylindrical cavity with a small diameter also simplifies the microwave circuit because the lowest frequency resonant mode is utilized with large frequency separation from other resonant modes.
  • the smaller diameter cavity is also less sensitive to changes in the length of the cavity.
  • a problem with the narrow cavity is that the proximity of the electrodeless bulb to the screen wall causes overheating of the screen material. Over time the overheating causes degradation of the screen. Once degraded the problem is exacerbated and even greater overheating can lead to thermal runaway, eventually causes failure of the screen and consequently the reliability of the lamp is reduced.
  • One object of the invention is to provide an improved microwave electrodeless lamp.
  • One aspect of the present invention is achieved by a mesh screen having a lower aspect ratio of length to diameter that reduces the thermal stress on the screen.
  • Another object of the invention is to provide an interleaved PFC boost converter circuit that operates over a range of input voltages and frequencies.
  • One aspect of the present invention is achieved by sharing of timing information between two sides of an interleaved PFC boost converter.
  • a timing control circuit may provide substantially simultaneous go and stop signals to respective sides of the interleaved PFC boost converter.
  • Fig. 1 is a block diagram of a microwave electrodeless lamp in accordance with the present invention.
  • Fig. 2 is a perspective view of an example of a microwave electrodeless lamp in accordance with the present invention.
  • Fig. 3 is another perspective view of the microwave electrodeless lamp.
  • Fig. 4 is a more detailed perspective view of the lamp with an external cover removed.
  • Fig. 5 is another more detailed perspective view of the lamp.
  • Fig. 6 is an exploded perspective view showing various components and assemblies of the lamp of the present invention.
  • Fig. 7 is a schematic view of an example of a secondary envelope in accordance with the present invention.
  • Fig. 8 is a cross sectional view of the secondary envelope taken along line 8-8 in Fig. 7.
  • Fig. 9 is a schematic view of another example of a secondary envelope in accordance with the present invention.
  • Fig. 10 is a perspective view of the secondary envelope from Fig. 9.
  • Fig. 11 is a cross sectional view of selected components of the lamp of the present invention.
  • Fig. 12 is a perspective view of an example of a mesh screen in accordance with the present invention.
  • Fig. 13 is a perspective, cut-away view of the lamp system showing cooling channels.
  • Fig. 14 is another perspective, cut-away view of the lamp system showing cooling channels.
  • Fig. 15 is a best fit line graph of light output versus wall plug input for exemplary lamp systems of the present invention.
  • Fig. 16 is a best fit line graph of lumens per watt versus wall plug input power for the exemplary lamp systems of the present invention.
  • Fig. 17 is a graph of relative light intensity versus wavelength for a lamp of the present invention.
  • Fig. 18 is a comparison graph of light intensity versus angle for a lamp of the present invention.
  • Fig. 1 A is a block diagram of a conventional interleaved PFC circuit.
  • Fig. 2A is a block diagram of an interleaved PFC circuit in accordance with the present invention.
  • Fig. 3A is a more detailed block diagram of an interleaved PFC circuit in accordance with the present invention.
  • Fig. 4A is a schematic diagram of a first interleaved PFC circuit in accordance with the present invention.
  • Fig. 5A is a timing diagram of various signals for the circuit from Fig. 4.
  • Fig. 6A is a schematic diagram of a second PFC circuit in accordance with the present invention.
  • Fig. 7A is a schematic diagram of a third PFC circuit in accordance with the present invention.
  • Fig. 8A is a graph of PFC voltage versus Input voltage for one example of the present invention.
  • Fig. 9A is a graph of the PFC coefficient versus input voltage for one example of the present invention.
  • an example block diagram of a preferred microwave lamp system of the present invention includes an RF assembly providing RF or microwave power.
  • the RF assembly includes a magnetron which generates microwave energy.
  • the microwave energy is transmitted via a waveguide to a microwave cavity, generally comprised of a mesh screen.
  • the microwave cavity is part of the optical cavity assembly which includes the mesh screen and the electrodeless bulb disposed within the screen.
  • the optical cavity further includes an optional reflector for controlling the light output from the bulb.
  • Power is provided to the RF assembly and various other components from a power and control assembly.
  • the power and control assembly receives power from a suitable external source via a power terminal and includes a power supply module for converting the external power to a type of power appropriate for the RF assembly and other electronic components of the lamp.
  • the power supply module may include the novel power factor correction circuit described below in connection with Figs. 1A-9A.
  • the power supply module contains control software for controlling the operation of the power supply.
  • the power supply and control assembly includes a microprocessor for running the control software.
  • An optical sensor provides information to the control assembly which may be used, for example, as a safety interlock.
  • the power and control assembly may include an optional communication module for interfacing with other external devices.
  • the lamp components are disposed in a housing assembly which further includes a fan and cooling system.
  • a lamp 10 includes a housing 12 comprised of a plate 14 and a cover 16. A set of brackets are provided to secure
  • the cover 16 provides openings for a cooling air inlet 18 and exhaust air outlets 20.
  • the cover 16 also provides a power receptacle 22 and a covered wiring area 24 for access to an internal power wiring terminal 26.
  • Optional access to a communication port may also be provided through the cover 16.
  • a secondary envelope 28 in the shape of a globe is secured to the plate 14 bye a pair of retaining brackets 30.
  • the globe 28 protects the microwave cavity and bulb from environmental hazards and may include a gasket, caulking, epoxy, or other suitable material disposed between the lip 31 of the globe 28 and the plate 14 to provide an environmental seal against contaminants.
  • the microwave cavity and bulb may include a gasket, caulking, epoxy, or other suitable material disposed between the lip 31 of the globe 28 and the plate 14 to provide an environmental seal against contaminants.
  • 0 globe 28 is made from glass and may be transparent or translucent (e.g. frosted).
  • the plate 16 provides one end wall of a cylindrical microwave cavity with the remainder of the cavity being defined by a mesh screen 32.
  • the globe 28 protects the screen 32 from mishandling (e.g. accidental deformation).
  • An electrodeless bulb 34 is disposed inside the microwave cavity and includes a stem
  • the plate 16 also provides one wall of a waveguide 40.
  • the stem 36 of the bulb 34 extends past the waveguide 40 (outside of the waveguide 40, see Fig. 11) and through a motor mount 42.
  • the mount 42 further functions to thermally isolate the motor 38 from the RF assembly.
  • a motor cover 44 covers the motor and
  • >0 protects the motor from environmental hazards and may include a gasket, caulking, epoxy, or other suitable material disposed between the lip 45 of the cover 44 and the waveguide 40 to provide an environmental seal against contaminants.
  • the cover 44 is made from plastic or other suitable material. With the globe 28 and the cover 44, the lamp is well sealed against environmental hazards such as dust or fumes and the lamp reliability is improved.
  • the lamp 10 further includes a magnetron 46 positioned against the waveguide 40.
  • the waveguide 40 provides an opening therethrough to receive the antenna 48 of the magnetron 46.
  • Power is provided to the magnetron 46 and other lamp components by a power supply module 50.
  • the power supply module 50 is supported by brackets 52 which further function to thermally isolate the module 50 from the RF assembly.
  • the lamp 10 provides external access to the power terminal assembly 26 through the cover 16.
  • the lamp 10 includes an active cooling system for the magnetron 46 and the power supply module 50. Other than rotation of the bulb, no active cooling is provided inside the sealed environment of the globe 28, the waveguide 40, and the motor cover 44.
  • the cooling system includes a fan 54 and a set of ductwork 56, 58, and 60 positioned between the plate 14 / waveguide 40 and the power supply module 50.
  • the globe 28 has a generally spherical shape, truncated on one side providing an opening in the globe 28 and defining a lip 31.
  • the globe is large enough to not overheat the screen and / or bulb.
  • a glass globe will tend to absorb or shed infrared (IR) light and not reflect the IR back at the screen or bulb.
  • a second envelope 90 has the general shape of a hollow truncated cone which is open on its smaller end and closed on its larger end.
  • the envelope 90 further defines a lip 91 around its open end for mounting the envelope 90 to the lamp 10 and sealing the interior of the envelope 90 against environmental hazards.
  • the secondary envelope 90 can be adapted to function as a reflector for directing light output from the lamp.
  • either the interior or exterior surface of the envelope 90 can be coated or metalized with reflective material. Depending on the application and the material, either the interior or exterior surface may be preferred.
  • the coating is thin so that the coating is transparent to RF energy. However, there may be some applications where it is desired that the metal coating be thick enough to provide secondary RF shielding.
  • Another alternative is a thin metal layer to reflect light which is substantially transparent to RF and a subsequent outer layer which absorbs RF (e.g. thicker resistive material).
  • An alternative secondary envelope includes a metal reflector with a light transmissive cover plate and appropriate environmental seals.
  • the RF assembly is shown in cross section.
  • the plate 14 defines an opening therethrough which is the coupling slot 112 where microwave energy is transmitted from the waveguide 40 to the microwave cavity 114.
  • the waveguide 40 defines a shoulder 116 near the slot 112 which improves the matching between the magnetron 46 and the cavity 114 and increases the bandwidth.
  • a capacitive tuning element 142 may further improve the match.
  • the element 142 may be adjustable or may have a fixed location.
  • the microwave cavity 114 is defined by the mesh screen 32.
  • the dimensions of the cavity 114 are selected in accordance with material characteristics of the screen to improve the lifetime of the screen, and consequently the reliability of the lamp.
  • the resulting screen has a novel aspect ratio (length of the cylindrical cavity : diameter of the cylindrical cavity) as compared to prior mesh screens used to define the microwave cavity of an electrodeless lamp.
  • the material selected for the mesh screen is a metal or metal alloy. Such materials have quantifiable material qualities including the temperature at which the material degrades. Based on a desired operating temperature of the electrodeless bulb, a minimum distance between the bulb and the screen may be determined to keep the screen at a temperature which is well below the temperature at which the screen material degrades.
  • a preferred mesh screen 32 has a generally right cylindrical shape with a domed end cap 122. A slight tensioning on the domed portion during assembly helps the screen retain its shape with sagging.
  • a preferred material for the mesh screen is aluminum plated stainless steel.
  • both materials are inexpensive, readily available, and well characterized.
  • the aluminum coating is known to undergo a phase change at 495 °C.
  • the aluminum may be applied to the stainless steel as a flashing, for example by an ion beam vapor deposition (IVD) process.
  • the aluminum plated stainless steel has lower resistance and higher reflectivity as compared to a stainless steel screen.
  • the aluminum protects the stainless steel from oxidation with a self-healing skin of aluminum oxide.
  • the minimum distance between the bulb the material may be determined (e.g. empirically or mathematically) to be about X mm.
  • a problem with a larger diameter screen is that the cylindrical cavity will support more than one mode of microwave propagation.
  • a diameter of the cavity is selected in accordance with a minimum distance to reduce thermal stress and a length of the cavity is selected to provide frequency separation from undesired microwave modes.
  • a preferred length of the cavity is about 81 mm.
  • a TE111 mode is supported at 2450 MHz, while the TM010 mode has a resonant frequency of 2090 MHz and the TM011 mode has a resonant frequency of 2790 MHz.
  • both of these closest modes are several hundred megahertz separated from the desired mode and the desired mode is roughly centered between the frequencies of the other modes.
  • the dimensions are also advantageously greater than the above mentioned minimum distance for thermal stress. Operation of the lamp at 1300 W wall plug power (about 950 W RF power) results in a screen temperature of between about 400 °C and 425 °C, which is well below the maximum stable temperature of the screen material.
  • FIG. 13-14 respective cut-away perspective views show the paths of cooling air (represented with arrows) for the example lamp of the present invention.
  • the duct 58 divides the airflow into to channels, one past the magnetron 46 and the other past the power supply module 50.
  • the module 50 includes a finned heatsink 144 and the duct 58 provides a shroud 146 over the finned heatsink to define the air flow channel.
  • the cover 44 keeps contaminants in the cooling air out of the motor assembly.
  • Figs. 15-17 representative performance graphs for the lamp of the present invention. At about 1300 W of wall plug power, the lamp produces about 120,000 lumens light output, corresponding to an efficiency of about 94 lumens per watt of wall plug power. With respect to RF power (i.e. not counting power supply or magnetron losses), the efficiency rating is of course much higher. A representative light output spectrum is shown in Fig. 17. [0060] With reference to Fig.
  • the lamp 10 includes an angled reflector 118 at the base of the microwave cavity.
  • the reflector 118 does not interfere with the microwave mode and is made from metal.
  • the outer wall of the reflector conveniently provides a surface for clamping the fingers of the mesh screen to hold the screen in place.
  • the inside surface of the reflector 118 may be polished, anodized, or otherwise treated to increase the reflectivity of the reflector 118.
  • the inside surface of the plate 14 may likewise be polished or otherwise treated to improve its reflectivity.
  • the reflector 118 may cooperate with an external reflector to further control the light output.
  • a dielectric mirror may be positioned in or over the coupling slot to avoid light loss in the slot.
  • a dielectric mirror is positioned over the inside surface of the plate 14 (including the slot) to reflect light and also to absorb IR to reduce the thermal load on the screen. This configuration may be particularly useful in a down light application because the bulb tends to runs hotter at the highest point of the bulb (with respect to the floor or ground).
  • a PFC circuit is utilized to condition an input power signal and provide a more desirably shaped (e.g. less distorted) input power signal by reducing current peaks on the input conductors.
  • Universal line input refers to the ability to operate on more than one and preferably many of the different power line voltages available around the world.
  • DCM discontinuous-current-mode
  • CCM continuous-current-mode
  • Critical mode operation is a technique (with respect to the PFC inductors) where the converter is operating with a triangular input current in the region between discontinuous and continuous mode.
  • the benefit of the critical mode technique is that zero-current switching of the PFC- transistor is obtained with high efficiency and reliability. Zero current switching is obtained because the PFC-transistor does not turn-on until the current in the PFC- inductor and the PFC-diode is zero, thereby preventing the flow of recovery current.
  • Patent No. 6,091 ,233 entitled "Interleaved Zero Current Switching in a Power Factor Correction Boost Converter".
  • FIG. 1A A typical interleaved PFC circuit configuration is shown in Fig. 1A.
  • An input signal I is provided to a master circuit A and a slave circuit B. Operation of the master circuit A is not dependent on operation of the slave circuit B. Operation of the slave circuit B is at least partially dependent on the operation of the master circuit A.
  • a delay circuit D is connected between the master circuit A and the slave circuit B, with the master circuit A providing a signal to the delay circuit D which in turn provides a signal to the slave circuit B.
  • Outputs from the two circuits A and B are combined to provide a conditioned output signal O.
  • An error signal E is fed back to the converters A and B to adjust the operation of the circuit.
  • the timing control of the PFC circuit is uni-directional from the master circuit A to the slave circuit B.
  • the master i circuit A measures the PFC-voltage or current and tries to maintain its output at a constant level.
  • the delay circuit D includes a phase shifter which is synchronized to the gate signal of the master circuit A, and provides a 180-degree delay to a stop signal going to the slave circuit B. If the operation of the two circuits A and B is 180 degrees out-of-phase with respect to each other the overall ripple is reduced on the
  • a PFC is utilized to reduce high current peaks in the input line and provide an input power signal to downstream electronics having a shape which is closer to a sinusoid.
  • Most PFC circuits work by sensing the current in an inductor. When the current is determined to be zero, one side of an interleaved PFC
  • the 5 circuit is triggered by closing a switch to apply power through the PFC inductor to charge up the PFC capacitor.
  • the input signal to a PFC stage is sinusoidal and the output of the PFC stage is a well regulated DC signal (with some ripple).
  • the DC output can be passed to any desirable subsequent power supply stage (e.g. a buck or a boost).
  • D interleaved PFC stage operates affects the amount of ripple, the efficiency, and the reliability.
  • the effectiveness of the switching operation primarily determines the efficiency and the reliability. For example, a voltage superimposed on the switch before the switch is closed may cause a current spike which lead to reliability problems.
  • the switching of the two sides is ideally 180 degrees out of phase with respect to each other.
  • the two sides are frequency modulated with the particular switching frequency adjusted in accordance with the level of the mains signal.
  • the two sides operate with longer pulses near peaks of the input
  • phase shifter In order to maintain critical mode operation over a wide input operating voltage range, the phase shifter must be accurate over a wide span of frequencies which in practice is difficult to implement. In addition, manufacturing tolerances in the PFC-inductors may cause the inductor values to differ by ten percent or more, at
  • the present invention solves the timing problem by using a shared timing control circuit which inhibits phase shift error and provides no open loop for either portion of the interleaved circuit.
  • a shared timing control circuit which inhibits phase shift error and provides no open loop for either portion of the interleaved circuit.
  • an interleaved PFC circuit utilizes a topology in which neither converter is master or slave.
  • an interleaved PFC circuit 20 includes a first converter A and a second converted B which receive a common input signal I.
  • a timing circuit X is shared between the two converters A and B.
  • the first converter A provides a signal to the timing circuit X and receives a signal from the timing circuit X. Operation of the first converter A is at least partially dependent on the signal it receives from the timing circuit X.
  • the second converter B also provides a signal to the timing circuit X and receives a signal from the timing circuit X.
  • Operation of the second converter B is at least partially dependent on the signal it receives from the timing circuit X.
  • Both converters A and B receive an error signal E.
  • the output from both converters A and B is combined to provide a conditioned output signal O.
  • the timing circuit X is shared between the two converters A and B, the period of operation of both converters is the same.
  • the PFC circuit is tolerant of manufacturing variations affecting the timing circuit X because such variations are applied equally to both converters A and B. More importantly, the phase shift is accurate under a wide range of operating conditions because the timing circuit X turns off the converter A at the same time it turns on the converter B (and vice versa). Accordingly, there can be no overlap in operation of the two converter stages.
  • the converters A and B are configured as two co-equal circuits with a bi-directional timing circuit X controlling the operation of both sides.
  • the novel topology is applicable for all power levels, although it may find particularly beneficial application in the medium power range of 300 W - 2kW.
  • the novel topology is applicable to various regulation control modes including but not limited to voltage, current, and hysteresis.
  • a novel timing circuit includes a memory circuit X1 , an integrator X2, and a sign detect circuit X3.
  • the memory circuit X1 receives respective signals from both converters A and B and provides an output signal to the integrator X2.
  • the integrator X2 provides a signal to the sign detect circuit X3 which provides respective signals to both converters A and B.
  • the other circuit connections are as described above with respect to Fig. 2A.
  • Operation of the circuit is generally as follows.
  • the two converters A and B work in a desired control mode of, for example, current control or time control.
  • the memory circuit X1 holds a value corresponding to which converter (A or B) operated during the preceding period.
  • the integrator X2 is configured with a suitable time range corresponding to the working frequency of the converter and produces either an increasing or decreasing output in accordance with the signal from the memory circuit X1.
  • the sign detect circuit X3 senses the polarity of the output of the integrator X2 and provides respective signals (e.g. complementary signals) to the converters A and B indicating which of the two converters should operate.
  • the memory circuit X1 has an initial value. For example the value is a logical 0 or a logical 1 corresponding to an appropriate output voltage (e.g. zero volts or five volts).
  • the value of the memory circuit X1 is provided to the integrator X2.
  • the integrator generates a ramp signal which has either a positive slope or a negative slope in accordance with the value of the memory circuit X1 ,
  • the ramp signal from the integrator X2 is provided to the sign detect circuit X3.
  • the sign detect circuit X3 compares the ramp signal to a reference value.
  • the circuit X3 substantially simultaneously provides a "go" signal to one converter and a “stop” signal to the other converter in accordance with the direction of the ramp signal.
  • the converter which received the "go” signal provides a signal to the memory circuit X1 which causes the value of the memory circuit X1 to toggle.
  • a first example PFC circuit 40 includes a first control chip A1 and a second control chip B2 which receive the input signal 11 (e.g. the current sense or output voltage) through respective conditioning components (e.g. resistor R1 / capacitor C1 and resistor R2 / capacitor C2) to a buffer or inverter.
  • the first control chip A1 provides a gate signal A to a gate of a transistor Ml
  • the source of the transistor M1 is grounded and the drain of the transistor M1 is connected to one terminal of a PFC inductor L1 and also to a cathode of a PFC diode D1.
  • a second control chip B2 provides a gate signal B to a gate of a transistor M2.
  • the source of the transistor M2 is grounded and the drain of the transistor M2 is connected to one terminal of a PFC inductor L2 and also to a cathode of a PFC diode D2.
  • the respective other ends of the PFC inductors L1 and L2 are tied in common and provide the input voltage of the circuit.
  • the anode ends of the PFC diodes D1 and D2 are tied in common (the output) and connected to one terminal of a PFC capacitor C6.
  • the other terminal of the PFC capacitor C6 is grounded.
  • the PFC circuit 40 further includes a timing control circuit shared between the two stages.
  • the timing control circuit includes a toggle flip flop X1 which receives respective toggle signal from the two gate signal lines via respective capacitors C4 and C5.
  • the output signal C of the flip flop X1 is provided to an negative input terminal of an integrator X2 (e.g. comprising a comparator) via a resistor R3.
  • the positive terminal of the integrator is connected to a reference voltage V EFI and the output of the integrator X2 is fed back to the negative input terminal of the integrator X2 via a capacitor C3.
  • the output signal D of the integrator X2 is provided to a sign detect circuit X3 (e.g. comprising an operational amplifier) at the negative input terminal of the circuit X3.
  • the positive terminal of the circuit X3 is connected to a reference voltage VR E F2-
  • the output signal E of the sign detect circuit is provided to the first control chip A1 and through an inverter X5 to the second control chip B2.
  • the PFC circuit 40 further includes additional logic elements which determine when the two stages may operate. Specifically, the output of the sign detect circuit X3 is combined with respective zero signals from the two stages to ensure that zero current switching is obtained.
  • the non-inverted output of the circuit X3 is provided to a logical NAND circuit X4 and a zero signal Z1 from the first stage is provided to another input of the NAND circuit X4.
  • the output of the NAND circuit X4 is provided to the control chip A1.
  • the inverted output signal F of the circuit X5 is provided to a logical NAND circuit X6 and a zero signal Z2 from the second stage is provided to another input of the NAND circuit X6.
  • the output signal G of the NAND circuit X6 is provided to the control chip B2.
  • the general operation of the PFC circuit 40 is as follows.
  • the two control chips A1 and B2 work with a controlled current limit or controlled ON-time corresponding to a feedback signal sensing the PFC-voltage output.
  • the controllers have zero signal control inputs sensing when the current through the PFC-diodes, for each period, has stopped entirely.
  • the memory circuit is the flip-flop X1 that remembers which half of the circuit that produced the last positive going output gate- pulse signal.
  • the integrator X2 is attached to the flip-flop and generates a suitable time range for the working frequency of the converter.
  • the sign detect circuit X3 senses the polarity of the output of the integrator X2, and has two complementary outputs (one via the inverter X5).
  • reference voltage for the sign detect circuit is 2.5 V if the memory value is either 0 V or 5 V.
  • the logic circuits (X4 and X6) logically combine the zero current signals (Z1 and Z2) of each converter with respective outputs from the sign detector X3 before permitting the respective PFC- control circuit A1 or B2 to start a new period.
  • the integrator X2 output generates a delayed "clear-to-go" gate-signal to the respective PFC-controller after the flip-flop X1 has toggled.
  • a new period can start for a converter side when the "clear to go" is in the appropriate state for that side and the zero signal is indicating zero current.
  • the delay function will automatically force the other side to wait if the first side is delayed due to component difference, passive or active.
  • the present invention facilitates 180-degree phase shift for a wide range of frequencies as this phase information is delayed and passed in both directions the same way.
  • any frequency dependent extra delay will be the same both ways, thus symmetry is maintained. This is important as the working frequency varies over a large span, from a low frequency (for example, 40-100kHz in practice with present technology) when the mains voltage is momentarily high until the point where the mains voltage is momentarily close to zero where the frequency can go very high (for example, > 400kHz).
  • the circuit will, if PFC-controllers A1 and B2 are configured with controlled ON-time, give a final dead-time on one of the channels that depends only on possible tolerance variations in the ON-time between the two circuits. The converter side with the longest ON-time will always have minimum dead time. Variations in the PFC-inductor values will not adversely affect the function of the circuit.
  • FIG. 5A represent signal waveforms are illustrated for signals A-G, I/L2 and Z2.
  • the signal A is the gate signal to the transistor M2.
  • Signal A goes high at time TO (Based on the output signal C of the flip flop X1).
  • the duration of the pulse for the signal A depends on the mains voltage and the power level. However the duration of the pulse is not critical to the timing of the circuit because the flip flop X1 is edge triggered.
  • the waveform I/L2 is representative of current flowing through the inductor L2.
  • the current in the inductor L2 increases when the transistor M2 is conducting.
  • the signal C is representative of the actual status of the output of the flip flop X1.
  • the output signal C toggles with the rising edge of the signal A and toggles again with the rising edge of the signal B.
  • the output signal D of the integrator X2 starts to go negative at time TO as a result of the flip flop changing.
  • the output signal E of the comparator X3 goes high when the integrator output signal D goes under the reference level at time T1.
  • the signal E and its complement are substantially simultaneously provided to the two control chips A1 and B1 , via additional control logic circuits X4 and X6. [0090] In this cycle, at time T1 , the comparator output E goes from low to
  • control circuit B1 then awaits the arrival of a low signal Z2.
  • the signal Z2 goes low when the inductor L1 has fully released its energy to capacitor C6 via diode D1.
  • the signal Z2 returns to zero at time T1 thus making the signal G go low and enabling the control circuit B1.
  • the signal B goes high at time T2 thus causing the transistor M1 to conduct.
  • the operation of the circuit repeats in a symmetrical manner from this point in time with the B side of the circuit instead of the A side of the circuit.
  • the current through L2 starts to increase, the flip flop toggles back to the state before time TO, and the integrator starts to increase its output voltage.
  • both control circuits A1 and B1 are gated by the integrator X2 output and the zero current signals Z1 and Z2. Both signals must be in the appropriate state before switching control. If one side is late in starting due to a late arriving zero signal, then the other side will automatically be delayed a time corresponding to a 180 degree phase shift due to the symmetry of the integrator.
  • the circuit provides headroom between the transition of the signal E and the corresponding zero signal Z1 and Z2.
  • component tolerances may alter the precise symmetry of operation with respect to the zero signals, and one side may have little or no headroom as compared to the other side.
  • An advantage of the circuit is that, even with component tolerance variations, symmetry in time is maintained because the zero signal is utilized together with the integrator X2 output to activate the next control side of the converter.
  • the PFC capacitor may be life-limiting.
  • the present invention reduces electrical stress on the PFC capacitor, thereby
  • a preferred PFC circuit in accordance with the invention incorporates the following features:
  • 0 information between the two converters is bi-directional in order to get 180-degree phase shift under a wide range of conditions while inhibiting any phase disturbances.
  • One stage is always operated in critical mode.
  • the other stage generally operates in the critical mode, but may operate in DCM.
  • DCM is as efficient as CCM and more reliable as compared to CCM.
  • the circuit described in Fig. 6A is one example which is simple and does not require a conventional analog amplifier and comparator. It is built with a flip-flop and four high-speed transistors, Q1-Q4, and one integrator (resistors R5, R6 and capacitor C3).
  • the NAND-ing function is implemented by holding respective zero inputs of the PFC-control chips high via Q3 or Q4, thus stopping a new cycle from starting, until the integrator output allows the respective control circuit to re- trigger. (The zero signal is low when the PFC-inductor current is zero) [0108]
  • the two PFC-controllers operating in critical-mode can basically work according to two dominating techniques. Namely, controlling the on-time or controlling the current.
  • Controlling the on-time is an example of a technique used by the
  • Tl/Unitrode chip UC3852 uses a constant ON-time set by an error amplifier with respect to the mains frequency.
  • the chip does not control the peak current normally, except for setting an upper limit. However the circuit senses the current at a low minimum level to determine when to turn on the PFC-transistor each cycle. [0110]
  • These integrated circuits exhibit excellent part to part tolerance.
  • a SG-Thomson integrated circuit having part number L6561 uses an example of a technique which involves controlling the current.
  • a multiplier having the input from a divider sensing the input voltage and the error amplifier controls the envelope of the peak current. The result will in the end be more or less the same as in the case outlined above, namely the ON-time will be constant over the mains period.
  • An advantage of this circuit is the way the circuit determines when to start the next pulse.
  • a zero detector input senses when the voltage reverses over the PFC-inductor. This can only happen after the current through the PFC-diode has stopped entirely. Accordingly, the circuit prevents any recovery current at all.
  • the two methods mentioned above treats variations in component values in a different way. Variations in controlling the ON-time will give a variation in peak current but the period time will always stay constant even if the PFC-inductor changes. Controlling the peak current on the other hand is not possible if the period time has to be the same with different inductor values. At least not if the current is the same for both PFC-circuits.
  • FIG. 7A Another aspect of the present invention is based on the L6561 for following reasons.
  • the temperature range and input tolerance of this circuit is very good.
  • the way the controller is re-triggered has attributes which are suitable for implementation of the present invention.
  • the present design incorporates aspects from both circuits above.
  • the present L6561 circuit works primarily with a multiplier for current control thus giving almost constant ON-time but otherwise uses its normal basic functions.
  • An extra external error amplifier circuit is utilized instead of the internal error amplifier.
  • the internal error amplifier is utilized as a comparator.
  • Both controllers (A and B) have 6 - IO:s with following functions:
  • the inverter input is for the internal error amplifier. This amplifier has an internal reference of 2.5 V at the non-inverting input.
  • the same capacitors will start to charge at a rate set by the error amplifier X5 output level when a pulse has once started. This charging will continue until the voltage level on the respective capacitor has reached a level of 2.5 V where, in this case, the built in error amplifier of L6561 acts as a comparator.
  • the EA output of L6561 starts to go low, and as this output level controls the current, the pulse will be terminated when the set value corresponds to the actual current.
  • Both circuits will stop entirely when the PFC-voltage is high enough that the dividers formed by R14-R15 and R17-R18 hold respectively timing capacitor permanently charged to 2.5 V. There might be a slight difference of this level between the two circuits due to normal component tolerances. This does not matter, as the integrator with the following AND-gates will not permit one circuit to operate on its own. This is the process that will take over when the mains voltage reaches a peak operating voltage. Both circuits will stop whenever the peak mains voltage is higher than the PFC-capacitor.
  • FIGs. 8A and 9A representative performance graphs of the interleaved PFC circuit of the present invention show the PFC voltage and the PFC coefficient over a range of input voltages. Based on actual hardware tests, examples of the PFC circuit of the present invention generate excellent PFC voltage regulation over a wide input voltage range (see Fig. 8A). The PFC coefficient is maintained at greater than or equal to 0.99 for most of the input range, trailing of slightly at the upper ranges (see Fig. 9A).

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Rectifiers (AREA)

Abstract

L'invention concerne une lampe sans électrode à micro-ondes comprenant une ampoule sans électrode (34) renfermant une charge de génération de lumière, une grille maillée (32) entourant l'ampoule, dont la moitié au moins du volume se trouve complètement dans la maille, cette dernière, aux côtés d'une autre surface conductrice, délimitant une cavité à micro-ondess (114), un magnétron (46) permettant d'apporter une énergie micro-ondes et un guide d'ondes (40) permettant d'émettre l'énergie de micro-ondes à partir du magnétron vers la cavité à micro-ondes, la distance minimale séparant la surface externe de l'ampoule et la partie la plus proche de la maille étant sélectionnée conformément à la température de l'ampoule pendant son fonctionnement et à la température à laquelle la matière d'écran se dégrade. Font également l'objet de cette invention d'autres modes de réalisation et d'autres variantes.
PCT/US2003/016212 2002-06-14 2003-06-13 Lampe sans electrode a micro-ondes Ceased WO2003107725A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003241581A AU2003241581A1 (en) 2002-06-14 2003-06-13 Microwave electrodeless lamp

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US38833902P 2002-06-14 2002-06-14
US38833802P 2002-06-14 2002-06-14
US60/388,339 2002-06-14
US60/388,338 2002-06-14

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WO2003107725A1 true WO2003107725A1 (fr) 2003-12-24

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WO (1) WO2003107725A1 (fr)

Cited By (7)

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Publication number Priority date Publication date Assignee Title
EP1715507A1 (fr) * 2005-04-21 2006-10-25 LG Electronics Inc. Système d'illumination à plasma
EP1770756A1 (fr) * 2005-09-28 2007-04-04 LG Electronics Inc. Système d'éclairage sans électrodes comprenant un résonateur en treillis métallique
WO2008085091A1 (fr) * 2007-01-08 2008-07-17 Dipolar Ab Convertisseur-élévateur de tension entrelacé à correcteur de facteur de puissance
US20110006683A1 (en) * 2009-07-10 2011-01-13 Lg Electronics Inc. Electrodeless lighting system and control method thereof
EP2731124A1 (fr) * 2012-11-12 2014-05-14 LG Electronics, Inc. Appareil d'éclairage
EP2482622A3 (fr) * 2010-12-28 2017-07-19 LG Electronics Inc. Système d'éclairage à plasma
CN112490111A (zh) * 2020-12-07 2021-03-12 清华四川能源互联网研究院 分立式微波激励器和等离子光源装置

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US4933602A (en) * 1987-03-11 1990-06-12 Hitachi, Ltd. Apparatus for generating light by utilizing microwave
US5841233A (en) * 1996-01-26 1998-11-24 Fusion Lighting, Inc. Method and apparatus for mounting a dichroic mirror in a microwave powered lamp assembly using deformable tabs
US20020030453A1 (en) * 1999-05-12 2002-03-14 Kirkpatrick Douglas A. High brightness microwave lamp

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Publication number Priority date Publication date Assignee Title
US4933602A (en) * 1987-03-11 1990-06-12 Hitachi, Ltd. Apparatus for generating light by utilizing microwave
US5841233A (en) * 1996-01-26 1998-11-24 Fusion Lighting, Inc. Method and apparatus for mounting a dichroic mirror in a microwave powered lamp assembly using deformable tabs
US20020030453A1 (en) * 1999-05-12 2002-03-14 Kirkpatrick Douglas A. High brightness microwave lamp

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1715507A1 (fr) * 2005-04-21 2006-10-25 LG Electronics Inc. Système d'illumination à plasma
US7902766B2 (en) 2005-04-21 2011-03-08 Lg Electronics Inc. Plasma lighting system
EP1770756A1 (fr) * 2005-09-28 2007-04-04 LG Electronics Inc. Système d'éclairage sans électrodes comprenant un résonateur en treillis métallique
WO2008085091A1 (fr) * 2007-01-08 2008-07-17 Dipolar Ab Convertisseur-élévateur de tension entrelacé à correcteur de facteur de puissance
EP2100362A4 (fr) * 2007-01-08 2014-09-24 Dipolar Ab Convertisseur-élévateur de tension entrelacé à correcteur de facteur de puissance
US8410700B2 (en) 2009-07-10 2013-04-02 Lg Electronics Inc. Electrodeless lighting system and control method thereof
EP2280588A3 (fr) * 2009-07-10 2012-05-09 LG Electronics Inc. Système d'éclairage sans électrode et son procédé de commande
US20110006683A1 (en) * 2009-07-10 2011-01-13 Lg Electronics Inc. Electrodeless lighting system and control method thereof
EP2482622A3 (fr) * 2010-12-28 2017-07-19 LG Electronics Inc. Système d'éclairage à plasma
EP2731124A1 (fr) * 2012-11-12 2014-05-14 LG Electronics, Inc. Appareil d'éclairage
US9305763B2 (en) 2012-11-12 2016-04-05 Lg Electronics Inc. Lighting apparatus
CN112490111A (zh) * 2020-12-07 2021-03-12 清华四川能源互联网研究院 分立式微波激励器和等离子光源装置
CN112490111B (zh) * 2020-12-07 2025-07-15 清华四川能源互联网研究院 分立式微波激励器和等离子光源装置

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