WO2004010308A3 - Systeme de communication interprocesseurs ameliore pour une communication entre processeurs - Google Patents

Systeme de communication interprocesseurs ameliore pour une communication entre processeurs Download PDF

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Publication number
WO2004010308A3
WO2004010308A3 PCT/IB2003/002813 IB0302813W WO2004010308A3 WO 2004010308 A3 WO2004010308 A3 WO 2004010308A3 IB 0302813 W IB0302813 W IB 0302813W WO 2004010308 A3 WO2004010308 A3 WO 2004010308A3
Authority
WO
WIPO (PCT)
Prior art keywords
processor
processors
unit
programmable
communication
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2003/002813
Other languages
English (en)
Other versions
WO2004010308A2 (fr
Inventor
Stefan Koch
Hans-Joachim Gelke
Harald Bauer
Arthur Tritthart
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Intellectual Property and Standards GmbH
Koninklijke Philips NV
Original Assignee
Philips Intellectual Property and Standards GmbH
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Intellectual Property and Standards GmbH, Koninklijke Philips Electronics NV filed Critical Philips Intellectual Property and Standards GmbH
Priority to AU2003246991A priority Critical patent/AU2003246991A1/en
Priority to JP2004522393A priority patent/JP4368795B2/ja
Priority to US10/521,881 priority patent/US20060123152A1/en
Priority to AT03765224T priority patent/ATE543138T1/de
Priority to EP03765224A priority patent/EP1535169B1/fr
Publication of WO2004010308A2 publication Critical patent/WO2004010308A2/fr
Anticipated expiration legal-status Critical
Publication of WO2004010308A3 publication Critical patent/WO2004010308A3/fr
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Multi Processors (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Microcomputers (AREA)
  • Bus Control (AREA)

Abstract

L'invention concerne un système comprenant au moins deux processeurs intégrés (P1 et P2). Ces deux processeurs (P1 et P2) sont reliés de manière fonctionnelle par le biais de deux canaux de communication bidirectionnels pour échanger des informations. Pour établir ces canaux de communication bidirectionnels, le système comprend un premier bus de processeur (10) auquel est relié le premier processeur (P1), une première unité d'accès à mémoire directe (45), une première unité programmable (34), et une première unité pouvant être partagée (13). L'unité programmable (34) peut être programmée par le premier processeur (P1). L'invention concerne également un second bus de processeur (20), le second processeur (P2) pouvant être connecté au second bus de processeur (20), une seconde unité d'accès à mémoire directe (35), et une seconde unité programmable (44). Ladite seconde unité programmable (44) peut être programmée par le biais du second processeur (P2).
PCT/IB2003/002813 2002-07-23 2003-07-16 Systeme de communication interprocesseurs ameliore pour une communication entre processeurs Ceased WO2004010308A2 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
AU2003246991A AU2003246991A1 (en) 2002-07-23 2003-07-16 Improved inter-processor communication system for communication between processors
JP2004522393A JP4368795B2 (ja) 2002-07-23 2003-07-16 プロセッサ間で通信を行うための改良プロセッサ間通信システム
US10/521,881 US20060123152A1 (en) 2002-07-23 2003-07-16 Inter-processor communication system for communication between processors
AT03765224T ATE543138T1 (de) 2002-07-23 2003-07-16 Verbesserte interprozessorkommunikation zwischen prozessoren
EP03765224A EP1535169B1 (fr) 2002-07-23 2003-07-16 Systeme de communication interprocesseurs ameliore pour une communication entre processeurs

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP02016492.7 2002-07-23
EP02016492 2002-07-23

Publications (2)

Publication Number Publication Date
WO2004010308A2 WO2004010308A2 (fr) 2004-01-29
WO2004010308A3 true WO2004010308A3 (fr) 2005-04-07

Family

ID=30470237

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2003/002813 Ceased WO2004010308A2 (fr) 2002-07-23 2003-07-16 Systeme de communication interprocesseurs ameliore pour une communication entre processeurs

Country Status (7)

Country Link
US (1) US20060123152A1 (fr)
EP (1) EP1535169B1 (fr)
JP (1) JP4368795B2 (fr)
CN (1) CN100447768C (fr)
AT (1) ATE543138T1 (fr)
AU (1) AU2003246991A1 (fr)
WO (1) WO2004010308A2 (fr)

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CN100334581C (zh) * 2004-04-02 2007-08-29 明基电通股份有限公司 在多个微处理器间传输数据的嵌入式计算机系统及方法
JP2006059303A (ja) * 2004-08-24 2006-03-02 Oki Electric Ind Co Ltd コンピュータシステム
JP2006133968A (ja) * 2004-11-04 2006-05-25 Fujitsu Ltd 情報処理装置
US8732368B1 (en) * 2005-02-17 2014-05-20 Hewlett-Packard Development Company, L.P. Control system for resource selection between or among conjoined-cores
CN101098527B (zh) * 2006-06-27 2012-06-13 雅斯拓（北京）智能卡科技有限公司 同时处理个人令牌中的数据传输会话的线程控制器
US7984301B2 (en) 2006-08-17 2011-07-19 Inside Contactless S.A. Bi-processor architecture for secure systems
JP4476267B2 (ja) * 2006-10-06 2010-06-09 株式会社日立製作所 プロセッサ及びデータ転送ユニット
US20100077472A1 (en) * 2008-09-23 2010-03-25 Atmel Corporation Secure Communication Interface for Secure Multi-Processor System
US8195858B1 (en) * 2009-07-28 2012-06-05 Nvidia Corporation Managing conflicts on shared L2 bus
US8321618B1 (en) 2009-07-28 2012-11-27 Nvidia Corporation Managing conflicts on shared L2 bus
CN102063337B (zh) * 2009-11-17 2014-01-08 中兴通讯股份有限公司 多处理器核的信息交互和资源分配的方法及系统
US8458377B2 (en) * 2010-03-05 2013-06-04 Lsi Corporation DMA engine capable of concurrent data manipulation
KR101685407B1 (ko) * 2010-07-29 2016-12-13 삼성전자주식회사 멀티코어 시스템을 위한 다이렉트 메모리 억세스 장치 및 다이렉트 메모리 억세스 장치의 동작 방법
US9762434B2 (en) 2011-08-12 2017-09-12 Rambus Inc. Temporal redundancy
FR3026869B1 (fr) * 2014-10-07 2016-10-28 Sagem Defense Securite Systeme embarque sur puce a haute surete de fonctionnement
US10303630B2 (en) * 2017-10-08 2019-05-28 Huawei Technologies Co., Ltd. Configurable hardware accelerators
CN111427816A (zh) * 2020-03-04 2020-07-17 深圳震有科技股份有限公司 一种amp系统核间通讯方法、计算机设备及存储介质
CN112181878B (zh) * 2020-08-28 2022-04-08 珠海欧比特宇航科技股份有限公司 RapidIO接口架构和数据处理方法
CN112838888A (zh) * 2021-01-11 2021-05-25 深圳震有科技股份有限公司 一种基于5g的卫星编解码并发计算方法和系统
CN114228725A (zh) * 2021-11-23 2022-03-25 深圳元戎启行科技有限公司 车载控制系统以及无人驾驶车辆
US20260088976A1 (en) * 2024-09-26 2026-03-26 Xilinx, Inc. Acceleration of cryptographic operations

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Publication number Priority date Publication date Assignee Title
US5335326A (en) * 1992-10-01 1994-08-02 Xerox Corporation Multichannel FIFO device channel sequencer
US5644729A (en) * 1992-01-02 1997-07-01 International Business Machines Corporation Bidirectional data buffer for a bus-to-bus interface unit in a computer system
US20020055979A1 (en) * 2000-09-06 2002-05-09 Stefan Koch Inter-processor communication system for communication between processors

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JPS60229160A (ja) * 1984-04-26 1985-11-14 Toshiba Corp マルチプロセツサシステム
US5283903A (en) * 1986-12-25 1994-02-01 Nec Corporation Priority selector
US5222227A (en) * 1987-01-16 1993-06-22 Hitachi, Ltd. Direct memory access controller for a multi-microcomputer system
JPH02109153A (ja) * 1988-10-18 1990-04-20 Fujitsu Ltd プロセッサ間データ伝送方式
US5289588A (en) * 1990-04-24 1994-02-22 Advanced Micro Devices, Inc. Interlock acquisition for critical code section execution in a shared memory common-bus individually cached multiprocessor system
JP3196637B2 (ja) * 1996-04-26 2001-08-06 三菱電機株式会社 ソートプロセッサおよびソート処理装置
US5890013A (en) * 1996-09-30 1999-03-30 Intel Corporation Paged memory architecture for a single chip multi-processor with physical memory pages that are swapped without latency
CN1293494C (zh) * 1999-09-09 2007-01-03 上海贝尔有限公司 主从式多处理器系统中的通信接口
US6775717B1 (en) * 2001-08-31 2004-08-10 Integrated Device Technology, Inc. Method and apparatus for reducing latency due to set up time between DMA transfers

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5644729A (en) * 1992-01-02 1997-07-01 International Business Machines Corporation Bidirectional data buffer for a bus-to-bus interface unit in a computer system
US5335326A (en) * 1992-10-01 1994-08-02 Xerox Corporation Multichannel FIFO device channel sequencer
US20020055979A1 (en) * 2000-09-06 2002-05-09 Stefan Koch Inter-processor communication system for communication between processors

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
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H. HELLWAGNER, W. KARL, M. LEBERECHT: "Fast communication mechanisms - COupling hardware distributed shared memory and user-level messaging"", 1997, INSTITUT FÜR INFORMATIK DER TECHNISCHEN UNIVERSITÄT MÜNCHEN, XP002314569, Retrieved from the Internet <URL:http://citeseer.ist.psu.edu/hellwagner97fast.html> [retrieved on 20050119] *

Also Published As

Publication number Publication date
CN100447768C (zh) 2008-12-31
CN1688986A (zh) 2005-10-26
US20060123152A1 (en) 2006-06-08
AU2003246991A1 (en) 2004-02-09
WO2004010308A2 (fr) 2004-01-29
EP1535169B1 (fr) 2012-01-25
JP2005534094A (ja) 2005-11-10
JP4368795B2 (ja) 2009-11-18
EP1535169A2 (fr) 2005-06-01
ATE543138T1 (de) 2012-02-15
AU2003246991A8 (en) 2004-02-09

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