WO2004010468A2 - Recuit a l'ozone a basse temperature de grilles et d'element dielectrique de condensateur - Google Patents

Recuit a l'ozone a basse temperature de grilles et d'element dielectrique de condensateur Download PDF

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Publication number
WO2004010468A2
WO2004010468A2 PCT/US2003/022235 US0322235W WO2004010468A2 WO 2004010468 A2 WO2004010468 A2 WO 2004010468A2 US 0322235 W US0322235 W US 0322235W WO 2004010468 A2 WO2004010468 A2 WO 2004010468A2
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WO
WIPO (PCT)
Prior art keywords
ozone
annealing
gas
temperature
dielectric
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Ceased
Application number
PCT/US2003/022235
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English (en)
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WO2004010468A3 (fr
Inventor
Yoshihide Senzaki
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ASML US Inc
Aviza Technology Inc
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ASML US Inc
Aviza Technology Inc
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Priority to AU2003253951A priority Critical patent/AU2003253951A1/en
Publication of WO2004010468A2 publication Critical patent/WO2004010468A2/fr
Publication of WO2004010468A3 publication Critical patent/WO2004010468A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6529—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to a gas or vapour
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/0134—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6536—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to radiation, e.g. visible light
    • H10P14/6538—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to radiation, e.g. visible light by exposure to UV light
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6928—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
    • H10P14/693—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides the material containing hafnium, e.g. HfSiOx or HfSiON
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6928—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
    • H10P14/6934—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides the material containing zirconium, e.g. ZrSiOx
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
    • H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
    • H10P14/69393—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
    • H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
    • H10P14/69394—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing titanium, e.g. TiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
    • H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
    • H10P14/69395—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing zirconium, e.g. ZrO2

Definitions

  • the present invention relates generally to the field of semiconductors. More specifically, the present invention relates to the thermal anneal process used in gate fabrication of semiconductor devices.
  • High-k dielectrics to conventional silicon dioxide dielectrics (SiO 2 ) are actively sought.
  • These types of metal oxides can be deposited on the surface of a silicon substrate by traditional techniques such as chemical vapor deposition (CVD) or newer
  • ⁇ techniques such as atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • N 2 nitrogen
  • O 2 oxygen
  • Conventional post deposition annealing thermal anneal process induces additional oxide growth at the interface between the metal oxide layer and the underlying silicon substrate.
  • the conventional thermal anneal step induces interfacial oxide growth and therefore increases the equivalent oxide thickness (EOT), and as a result, loses the merit of post deposition anneal.
  • EOT equivalent oxide thickness
  • Oxygen from the metal oxide layer diffuses into the underlying silicon substrate and reacts with the silicon to form a SiO x suboxide layer at the interface between the gate or capacitor dielectric and the substrate thereby degrading the device performance.
  • one object of the present invention is to provide a method in which post deposition anneal of high-k dielectric oxide layers is carried out at a low temperature, thereby suppressing interfacial oxide growth.
  • the anneal can be done at a lower temperature than conventional anneal processes, thereby suppressing interfacial oxide growth.
  • the lower temperature anneal method of the present invention retains the benefits of conventional annealing of fixing electron trapping sites in metal oxides and improving the electrical properties while minimizing the undesired interfacial oxide growth.
  • a method of annealing one or more gate and/or capacitor dielectric layers on a semiconductor substrate characterized in that the one or more gate and/or capacitor dielectric layer(s) is exposed to an ozone-containing atmosphere for a period of time in the range of about 0.1 second to 5 minutes, and at a temperature in the range of 20°C to 500°C.
  • a method of annealing a dielectric layer on a semiconductor substrate wherein the substrate is placed in a chamber, the chamber is heated to an annealing temperature, the dielectric layer is exposed to a ozone- containing gas at a flow rate in the range of about 20 seem to 10,000 seem, where the temperature and flow rate are maintained for a annealing time.
  • FIGS. 1A and IB illustrate two different apparatus suitable for the performing the method of the present invention.
  • FIG. 2 provides a flow chart illustrating the steps of the method according to one embodiment of the present invention.
  • FIG. 3 illustrates devices that may be annealed using the invention.
  • the present invention provides a method of thermal annealing of a semiconductor device. More specifically, the present invention provides a method of annealing a metal oxide dielectric layer having a high dielectric constant (high-k).
  • the method of the present invention uses ozone, or an ozone containing mixture, as the annealing gas.
  • Ozone is a stronger oxidizer than molecular oxygen and allows for annealing of the high-k material at a lower temperature than required in conventional annealing processes that employ nitrogen or oxygen.
  • annealing of high-k metal oxide dielectrics can be performed at a temperature as low as 100°C, and even at or near room temperature with the addition of UV light.
  • Thermal annealing systems are well known in the industry, and are typically classified as hot wall chambers (see FIG. 1A) or cold wall chambers (see FIG. IB).
  • Systems may be batch systems which support a plurality of wafers for processing in one batch, or a single wafer system which processes one wafer at a time. As such systems are well known, they are not described in detail herein and are shown in a simplified manner in FIGS. 1A and IB.
  • a hot wall chamber type system 101 is partially shown in a cross sectional view.
  • a plurality of wafers 100 are stacked vertically in the chamber.
  • Heater elements (not shown) are provided to heat the environment of the wafer 100. Gases are conveyed to and from the chamber 101 via inlet 104 and outlet 105, respectively.
  • a cold wall chamber type system 102 is partially shown in a cross sectional view.
  • a single wafer 100 is processes in the chamber.
  • the wafer is supported and heated by a heated support or chuck 103.
  • a cold wall chamber is preferred as it tends to preserve the stability of the ozone.
  • the chamber 101 or 102 is heated, preferably in an inert environment, to the annealing temperature.
  • Inert diluent gases such as nitrogen, helium, neon, argon, xenon or a mixture of any of the above can be used; nitrogen and argon are preferred inert diluent gases for cost reasons.
  • an ozone containing annealing gas is introduced into the chamber through inlet 104.
  • the wafers are exposed to the ozone containing gas at the annealing temperature for a desired time, the annealing time.
  • the annealing gas is removed from the annealing chamber by pumping the gas out of the chamber through outlet 105.
  • the wafer(s) 100 is allowed to cool to room temperature, or preferably, rapidly cooled to room temperature by conventional cooling techniques in an inert atmosphere.
  • the post deposition annealing method of the present invention is performed at an annealing temperature in the range of about 20°C to 500°C in an ozone-containing atmosphere for a time period ranging from 0.1 seconds to 5 minutes (the annealing time), as required by the device specifications and/or performance.
  • the annealing temperature can be higher than 500°C, however it is not preferred as the best results are achieved at or lower than 500°C.
  • the annealing temperature can be less than 100°C with the assistance of UV light.
  • the annealing time is from 5 seconds to 1 minute, with optimal results obtained with an annealing time of 10 to 30 seconds.
  • the ozone-containing atmosphere may be maintained during annealing at a pressure in the range of 10 Torr to 760 Torr.
  • the total gas flow rate into the chamber can be from 10 seem to 10,000 seem, with 100 seem to 10,000 seem being the preferred range.
  • the preferred ozone mass fraction of the total gas flow can be from 0.1% to 20% with the balance being O 2 .
  • the anneal of the present invention is preferably performed at a temperature within the range from about 150°C to 450°C, and most preferably at a temperature within the range of 200 to 400°C. At this lower temperature with exposure to ozone, the benefits of the anneal are realized, while the growth of the interfacial oxide is minimized.
  • the method is carried out at a temperature less than about 100°C, and during exposure of the substrate to the oxidizing gas UV is radiated on the substrate.
  • the anneal gas contains ozone, and is preferably pure, or close to pure, ozone.
  • the anneal gas contains a mixture of gases that includes ozone gas.
  • the mixture in addition to ozone, can include oxygen and/or nitrogen. Other gases may also be included.
  • the exact proportion of the components of the mixture is not critically important. As a general rule, however, a higher concentration of ozone gas in the mixture allows for annealing at a lower temperature, which in turn minimizes the undesired interfacial oxide growth.
  • rapid cooling after the heat exposure step is preferred. As with conventional annealing, however, rapid cooling is not a required step.
  • the device may alternatively be allowed to cool to ambient temperature simply by being removed from the heat source in an inert atmosphere.
  • the present invention is ideally suited for the annealing of gate and capacitor dielectrics and more specifically after the deposition of a high-k metal oxide dielectric containing a metal such as Ta, Ti, Hf or Zr, or a high-k metal silicate dielectric such as Hf-Si-O or Zr-Si-O 300.
  • a metal such as Ta, Ti, Hf or Zr
  • a high-k metal silicate dielectric such as Hf-Si-O or Zr-Si-O 300.
  • the metal in the oxide or silicate could also be chosen from the list comprising Hf, Ti, Zr, Y, La, V, Nb, Ta, W, Zn, Al, Sn, Ce, Pr, Sm, Eu, Tb, Dy, Ho, Er, Tm, Yb, or Lu.
  • the invention is also suited for annealing of dielectrics stacked with silicon oxide/silicon nitride layers 301. Annealing of other devices is also envisioned within the scope of the present invention where a lower temperature is desired.

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

La présente invention concerne un procédé de recuit thermique de dispositifs semiconducteurs. Dans un aspect de cette invention, les couches de grille ou d'élément diélectrique de condensateur sont exposées à une atmosphère contenant de l'ozone pendant une durée comprise entre environ 0,1 seconde et 5 minutes et à une température comprise entre environ 20 DEG C et 500 DEG C.
PCT/US2003/022235 2002-07-19 2003-07-16 Recuit a l'ozone a basse temperature de grilles et d'element dielectrique de condensateur Ceased WO2004010468A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003253951A AU2003253951A1 (en) 2002-07-19 2003-07-16 Low temperature ozone anneal of gate and capacitor dielectrics

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US39674202P 2002-07-19 2002-07-19
US60/396,742 2002-07-19

Publications (2)

Publication Number Publication Date
WO2004010468A2 true WO2004010468A2 (fr) 2004-01-29
WO2004010468A3 WO2004010468A3 (fr) 2004-04-08

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PCT/US2003/022235 Ceased WO2004010468A2 (fr) 2002-07-19 2003-07-16 Recuit a l'ozone a basse temperature de grilles et d'element dielectrique de condensateur

Country Status (3)

Country Link
AU (1) AU2003253951A1 (fr)
TW (1) TW200403767A (fr)
WO (1) WO2004010468A2 (fr)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2814049B2 (ja) * 1993-08-27 1998-10-22 株式会社半導体エネルギー研究所 半導体装置およびその作製方法
US6165834A (en) * 1998-05-07 2000-12-26 Micron Technology, Inc. Method of forming capacitors, method of processing dielectric layers, method of forming a DRAM cell
US6818500B2 (en) * 2002-05-03 2004-11-16 Micron Technology, Inc. Method of making a memory cell capacitor with Ta2O5 dielectric

Also Published As

Publication number Publication date
AU2003253951A8 (en) 2004-02-09
TW200403767A (en) 2004-03-01
WO2004010468A3 (fr) 2004-04-08
AU2003253951A1 (en) 2004-02-09

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