WO2004017640A1 - Unite de traitement de signal et systeme - Google Patents

Unite de traitement de signal et systeme Download PDF

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Publication number
WO2004017640A1
WO2004017640A1 PCT/JP2002/008236 JP0208236W WO2004017640A1 WO 2004017640 A1 WO2004017640 A1 WO 2004017640A1 JP 0208236 W JP0208236 W JP 0208236W WO 2004017640 A1 WO2004017640 A1 WO 2004017640A1
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WO
WIPO (PCT)
Prior art keywords
image
cache
processing device
control unit
memory
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Ceased
Application number
PCT/JP2002/008236
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English (en)
Japanese (ja)
Inventor
Yukifumi Kobayashi
Hiroshi Hatae
Hiromi Watanabe
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Renesas Technology Corp
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Renesas Technology Corp
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Publication date
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Priority to JP2004528812A priority Critical patent/JPWO2004017640A1/ja
Priority to PCT/JP2002/008236 priority patent/WO2004017640A1/fr
Publication of WO2004017640A1 publication Critical patent/WO2004017640A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction

Definitions

  • the present invention relates to a signal processing device, and more particularly to a technology that is effective when applied to a control method of an image cache memory.
  • LSIs that realize compression and decompression processing of moving images such as MPEG-4 are being developed.
  • image memory has a large capacity, so large-capacity but slow-speed memory such as DRAM is often used. Therefore, a cache memory may be provided between the processor and the memory to improve speed.
  • the first problem is that the same cache control is performed in both the processing of an encoded image and the processing of a reference image. Normally, in image processing, the coded image and the reference image are accessed frequently, but the address of the pixel data of the coded image and the address of the pixel data of the reference image are far apart at that time. .
  • the entry is determined Since it is determined by the lower bits of the address, entry conflicts are more likely to occur when frequent access to distant locations in memory occurs. Therefore, if the access to the coded image and the access to the reference image are performed alternately, frequent access to a distant location in the memory may occur, causing frequent contention for the entry. is there. If an entry conflict occurs, the entry is replaced with newer data, and the cache hit rate decreases.
  • the coded image and the reference image have different access characteristics. For example, in motion vector detection in MPEG, encoding is performed for a coded image. Power that is frequently accessed for a block of 16 ⁇ 16 pixels s, and for a reference image, a block of a search range is searched. (For example, 48 x 48 pixels, assuming ⁇ 16 pixels in both X and Y directions). If the same control method is used for different access characteristics, there is a problem that the capacity is increased.
  • the second problem is that the cache memory uses an address to determine the data entry that stores data in units of blocks in order to increase the cache hit ratio of pixels in the vertical direction.
  • the size of the direction is limited to a power of two. If the horizontal size of the image is other than a power of two, entry conflicts will occur, and the vertical pixel cache hit rate will decrease.
  • a first object of the present invention is to solve the first problem and increase the cache hit rate by preventing entry conflicts between an encoded image and a reference image.
  • Another object of the present invention is to provide a signal processing device capable of performing optimal cache control for each image in terms of capacity, entry determination method, and the like, and a system using the same.
  • a second object of the present invention is to solve the second problem and increase the vertical hit ratio by preventing a rectangular block in the vertical direction from causing contention of an entry.
  • the present invention has a cache memory for an encoded image and its cache control unit, a cache memory for a reference image and its cache control unit, and is accessed by a selection circuit. It determines whether the image is a coded image or a reference image based on the address, and performs cache control for the coded image if access to the coded image, and cache control for the reference image if access to the reference image.
  • the data to be cached is stored in each independent entry. This control prevents entry conflicts between the encoded image and the reference image, and increases the cache hit rate.
  • cache control since cache control is performed independently, it is possible to perform optimal cache control for each image using the capacity and entry determination method.
  • one entry stores image data that is a rectangular block on an image, and specifies the pixel data to be accessed. Specifies the horizontal and vertical positions of the rectangular block, the horizontal and vertical pixel positions of the rectangular block ⁇ , and determines the entry based on the horizontal and vertical positions of the rectangular block. It is.
  • the cached unit is a rectangular block, neighboring pixels exist in the horizontal and vertical directions in one entry, and the cache hit ratio in the vertical direction can be increased.
  • the entry of pixel data to be accessed is determined using the horizontal position and the vertical position of the rectangular block.
  • the rectangular block in the vertical direction does not cause entry competition, so that the cache hit ratio in the vertical direction can be increased, and the size of the image can be freely selected.
  • the cache hit rate for image data can be improved. Therefore, the bus occupation ratio due to the transfer of image data can be reduced in an image processing apparatus employing the unified memory architecture. As a result, it is possible to realize high-speed processing and low power consumption.
  • FIG. 1 is a block diagram illustrating a cache system according to a first embodiment to which the signal processing device according to the present invention is applied
  • FIG. 2 is a flowchart illustrating an operation in the cache system according to the first embodiment
  • FIG. FIG. 4 is an explanatory diagram showing an access range upon detection of a motion vector
  • FIG. 4 is a block diagram showing a cache system according to a second embodiment to which the signal processing device according to the present invention is applied
  • FIG. 5 is a signal processing device according to the present invention.
  • FIG. 6 is a block diagram showing a cache system according to a third embodiment to which the present invention is applied
  • FIG. 6 is an explanatory diagram showing an address designation method in the third embodiment
  • FIG. 7 is an explanatory diagram showing an entry determination method
  • FIG. FIG. 9 is a block diagram showing a cache system according to a fourth embodiment to which the signal processing device according to the present invention is applied
  • FIG. 10 is a signal processing device according to the present invention. It is a block diagram showing a mobile phone system of the fifth embodiment according to the. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 shows a key according to the first embodiment to which the signal processing device according to the present invention is applied. An example of the configuration of the cache system will be described.
  • FIG. 1 shows a block diagram of a cache system according to the present embodiment.
  • the cache system is, for example, a system that realizes image compression / decompression processing, and includes a cache control unit 100 for controlling a cache operation of image data, and an image processing for processing image data. It comprises a device 101 and an image memory 102 for storing image data.
  • a cache control unit 100 functioning as a signal processing device is provided with a cache memory for an encoded image and a reference image and a cache control unit therefor, independently of each other. You.
  • the cache control unit 100 0 is a part that functions as a signal processing device, and includes a coded image cache control unit 110, a coded image cache memory 111, and a reference image cache control unit 112. It consists of image cache memory 113, control section selection circuit 114, signal line selection circuit 115, etc., and is connected to image processing apparatus 101 through a path from the image processing apparatus interface, and image memory Is connected to the image memory 102 through the bus from the user interface. In particular, in the cache control unit 100, the encoded image cache control unit 110 and the reference image cache control unit 112 are independently provided.
  • the image processing device 101 includes an encoded image cache control unit 110 in the cache control unit 100, a reference image cache control unit 112, and a control unit.
  • the selection circuit 114 is connected to the signal line selection circuit 115 through the address path 120, and is connected to the signal line selection circuit 115 through the data bus 122.
  • the image memory 102 is connected to the signal line selection circuit 115 in the cache control unit 100 through address and data paths.
  • the encoded image cache control unit 110, the reference image cache control unit 112, and the control unit selection circuit 114 are connected through a control line 122, and the control unit Selection circuit 1 1 4, Signal line selection The selection circuit 1 15 is connected through another control line 1 2 3. Also, between the coded image cache control unit 110 and the signal line selection circuit 115, between the reference image cache control unit 112 and the signal line selection circuit 115, and furthermore, the coded image cache Between the control unit 110 and the coded image cache memory 111, and between the reference image cache control unit 112 and the reference image cache memory 113 through address and data signal lines, respectively. It is connected.
  • FIG. 2 shows a flow chart of the operation in the cache system of the present embodiment.
  • encoding associated with image compression processing is performed between the image processing device 101, the cache memory for encoded image 111, and the cache memory for reference image 113. This is performed, and the data in the image memory 102 is used as needed.
  • the decoding accompanying the image decompression process is performed between the image processing device 101 and the image memory 102.
  • a description will be given of an encoding operation associated with image compression processing which is an object of the present invention.
  • the control section selection circuit 114 in the cache control section 100 has an address path 120. Since the connection is established, an address to be accessed through this address path 120 is input (step S 1).
  • the control unit selection circuit 114 has information on the start address of the encoded image, the image size of the encoded image, the start address of the reference image, and the image size of the reference image. From this information, it is determined whether the input address is an access to an encoded image, an access to a reference image, or an access to any other (steps S2 and S3). .
  • control is performed so that the encoded image cache control unit 110 performs a cache control operation. Controlled by line 122.
  • the signal line selection circuit 115 selects the coded image cache control unit 110 that has been accessed, and connects it to the image memory 102 and the image processing device 101 by controlling the signal line. Control is performed by 1 2 3 (Step S 4). Also, if the result of the determination is that the reference image is to be accessed, the reference image cache control unit 112 is controlled by the control line 12′2 so as to perform the cache control operation.
  • step S 5 When the reference image is cached, data to be cached is stored in the reference image cache memory 113.
  • the signal line selection circuit 115 selects the accessed reference image cache control unit 112 so that the control line is connected to the image memory 102 and the image processing device 101. Control is performed by 1 2 3 (step S 5).
  • step S6 the signal line selection circuit 1 15 is controlled.
  • the dedicated cache memories 1 1 1 1 and 1 1 3 and the cache controllers 1 1 0 and 1 1 2 are provided for the encoded image and the reference image, respectively, the encoded image and the reference image are Always stored in separate memory, no entry conflicts.
  • the cache operation is not performed, so that the coded image and the reference image are not evicted from the cache memories 111 and 113. As a result, each cache hit rate is improved.
  • FIG. Figure 3 shows an explanatory diagram of the access range when a motion vector is detected.
  • the coded image cache control unit 110 and the reference image cache control unit 112 operate independently of each other, their control methods may not be the same.
  • the motion vector detection is 16 x 1
  • the coding block requires 16 X 16 pixels
  • the reference image requires 48 X 48 pixels.
  • the cache capacity of the encoded image is 16 ⁇ 16 pixels and the cache capacity of the reference image is 48 ⁇ 48 pixels, the efficiency in terms of capacity is improved.
  • the coded image cache control unit 110 and the reference image cache control unit 112 are operated independently of each other, so that the coded image and the reference image are controlled. There is no entry conflict between the image and other data, and the cache hit rate is improved. Also, since independent control methods can be used for the coded image and the reference image, the capacity, the control method, and the like can be optimized according to the characteristics of the image.
  • FIG. 4 shows a block diagram of the cache system of the present embodiment.
  • the cache system according to the present embodiment is, for example, a system that realizes image compression / decompression processing.
  • a cache control unit 100 a, an image processing device 101 A difference from the first embodiment is that a cache memory for a reference image and its cache control unit are further referred to in forward prediction as an extended example of the first embodiment. In that it is divided into an image and a backward prediction reference image.
  • the cache control unit 100a functioning as a signal processing device includes: a coded image cache control unit 110; a coded image cache memory 111; Reference image cache control unit 210, forward reference image cache memory 211, backward reference image cache control unit 212, backward reference image cache memory 211, control unit selection circuit 114, Signal line selection circuit
  • a forward reference image cache control unit 210 and a backward reference image cache control unit 212 are independently provided as reference image cache control units.
  • the cache control unit 110 for encoded images the cache control unit 110 for encoded images
  • the cache control unit 210 for forward reference images the cache control unit 212 for backward reference images
  • the control unit selection The circuit 1 1 4 is connected through a control line 1 2 2
  • the control section selection circuit 1 1 4 and the signal line selection circuit 1 1 5 are connected through another control line 1 2 3.
  • Other connections between the devices are the same as in the first embodiment.
  • the coded image cache control unit 110 and the forward has its own cache memory 111, 211, 213, and operates independently. There is no entry conflict between the two, and the cache hit rate is improved.
  • the capacity and control method can be optimized according to the characteristics of each image.
  • FIG. 5 shows a block diagram of the cache system of the present embodiment.
  • the unit of data stored in one entry is a rectangular block that is continuous in the horizontal and vertical directions on the image, and the method of specifying pixel data depends on the block position and the position in the block. It is to be done.
  • the cache control of the reference image will be described as an example, but it goes without saying that the present invention can be similarly applied to the cache control of the encoded image.
  • the cache system is a system that realizes, for example, image compression / decompression processing. It comprises an image processing device 101, a cache control unit 112 for reference images and a cache memory 113, a control unit selection circuit 114, a main memory 300, and the like.
  • the main memory 300 corresponds to the image memory 102 of the first embodiment.
  • the reference image cache control unit 112 includes an entry determination circuit 310, a cache hit determination circuit 3111, a tag memory 3112, a memory controller 3113, and the like.
  • the entry determination circuit 310 has information on the starting address of the reference image and the image size in the X direction, and the address of the accessed pixel in the main memory 300 is determined by the block position and the position in the block. It can be calculated.
  • the upper 16 bits of the address specify whether the access is for the reference image or for an access other than the reference image. For example, assuming that the identification code of the reference image is H ': FF 00, if the upper 16 bits of the input address are H, FF 00, the access is to the reference image, otherwise, It is usually used as a non-cached access specified by 32 bits. For this reason, the address used for the identification code is a prohibited area in normal access.
  • the pixel to be accessed is specified by the block position of the pixel and the position in the block.
  • the size of the block is 16 X I 6 pixels.
  • the block position is specified by the register set of the entry decision circuit 310, and the position of the pixel in the block is specified by the lower 16 bits of the address.
  • the lower 16 bits of the address indicate the pixel position in the block.
  • the cache memory address is calculated by specifying the position, and the cache access is performed.
  • the position within the block is specified by the position in the X and Y directions.
  • the lower 8 bits are specified as the X direction position in the block, and the upper 8 bits are specified as the Y direction position in the block.
  • FIG. 6 shows an explanatory diagram of the address designation method.
  • FIG. 7 shows an explanatory diagram of the entry determination method.
  • the entry is determined by the following formula, assuming that the horizontal position of the rectangular block is X, the vertical position is y, and the number of entries is mXn.
  • Entry number ⁇ Remainder of (Xm) ⁇ + ⁇ Remainder of (y / n) ⁇ Xm (1)
  • the entry number is determined according to equation (1), the block on the image It will be described whether it is stored.
  • the entry number increases by one in the horizontal direction, and returns to the original state at the third. In the vertical direction, the entry number increases by three, and returns to the original state at the third.
  • the tag at this time is represented by the following equation.
  • Tag ⁇ quotient of (x / m) ⁇ + ⁇ quotient of (y / n) ⁇ X m (2)
  • the formula ( 2) is stored.
  • the X-direction block position and the Y-direction block position of the reference image to be accessed by the image processing apparatus 101 are set in the internal register of the entry determination circuit 310.
  • the control unit selection circuit 114 checks the upper 16 bits to determine whether the access is to the reference image or to an access other than the reference image. If the access is to the reference image, the reference image control selection signal is output to the entry decision circuit 310.
  • the entry determination circuit 310 determines the entry and tag according to the expressions (1) and (2) according to the value set in the internal register, and the cache hit determination circuit 310 1 Output to 1. Also, it calculates the address for the main memory at the time of a miss from the reference image start address, the X-direction image size, the block position, and the cache memory address from the position in the block, and outputs them to the memory controller 313.
  • the cache hit determination circuit 311 compares the value of the tag memory 312 corresponding to the input entry with the input tag. As a result of the comparison, a hit signal is output to the memory controller 3 13 if they match, and a mismatch signal is output if they do not match. In the case of a miss, the tag memory 3 1 2 is rewritten with the input tag.
  • the memory controller 3 1 when the hit determination, accessing Kiya' Shumemori 1 1 3 in accordance with key Yasshu memory for real Adoresu inputted from the entry determination circuits 3 1 0, and outputs the data to the data path 1 2 1 c In the case of a mishit determination, replace all 16 x 16 pixels of the corresponding entry, and then output the data.
  • FIG. Fig. 8 is an explanatory diagram of the operation during a miss.
  • the memory controller 3 13 accesses the main memory 3 0 0, and first transfers one line (16 bytes) of H 'OB 1 0, which is the first address, to the entry number 4 of the cache memory 1 13 from above. Store in order. The Y-direction increment value ( ⁇ 'BO) is added to the address of main memory 300, and the next address ( ⁇ '0BC0) is accessed, and the entry number of cache memory 113 is added. Store in order in 4. This is repeated for 16 lines. One block (16 x 16 pixels) is replaced. Then, it accesses the cache memory 113 according to the actual address for the cache memory, outputs data to the data bus 121, and completes the operation.
  • a rectangular block is stored in one entry, and the pixel is specified at the block position and the position in the block.
  • the cache hit ratio of nearby pixels is improved.
  • the size of the image can be freely selected.
  • FIG. 9 shows a block diagram of the cache system of the present embodiment.
  • a feature of the present embodiment is that a cache control unit for an image and a cache control unit for a normal arithmetic processing device are separately provided, and are connected to a main memory via a path.
  • the cache system includes an image processing device 101 for processing image data, an image cache control unit 400 for controlling the image data caching operation, and a cache operation image.
  • the image processing apparatus 101 performs processing relating to image data.
  • the image processing device 101 requests the image cache controller 400 to access the image data. If the image data is a cache hit, the cache control unit 400 accesses the image cache memory 401 and outputs the data to the image processing device 101. If it is a miss, the main memory 402 is accessed via the bus 420, the data is replaced with the data of the image cache memory 401, and the data is output to the image processing apparatus 101.
  • the control method of the cache adopts the method described in the first embodiment, and is suitable for an image.
  • the arithmetic processing unit 403 mainly handles data other than image data.
  • the arithmetic processing unit 403 issues a data access request to the arithmetic processing unit cache control unit 404.
  • the cache control unit 404 if the data is a cache hit, it is stored in the cache memory 405 for the arithmetic processing unit. And outputs data to the arithmetic processing unit 403. If it is a miss, the main memory 402 is accessed through the path 420, the data is replaced with the data in the cache memory for the processing unit 405, and the data is output to the processing unit 403.
  • the arithmetic processing unit 403 mainly handles data other than images, such as instruction codes, so that a conventional cache control suitable for such control is performed.
  • the image processing device 101 has the image cache control unit 400, and the arithmetic processing device 400 has the arithmetic processing device cache control unit 400.
  • a cache control method suitable for each process can be applied.
  • the cache hit rate increases in each process.
  • FIG. 10 shows a block diagram of the mobile phone system of the present embodiment.
  • the feature of this embodiment is that it is applied to a mobile phone system as a specific product.
  • the mobile phone system includes a mobile phone main unit 500 on which the main part of the mobile phone system is mounted, a microphone 501 for inputting voice, and a speaker for uttering voice. It is composed of a device 502, a camera 503 for capturing an image of an object, an LCD 504 for displaying an image, and the like.
  • the mobile phone main body 500 has an RF circuit 510 that has the function of modulating and demodulating transmitted and received signals, a baseband processor 511 that has a function of controlling transmission and reception, and stores data such as voice and images Main memory 511, Camera DSP 513 for digitally processing image signals captured by camera 503, Application processor 515 including cache memory 514 for executing various application processes, LCD 505 It is composed of an LCD interface 516 that controls the interface with the ing.
  • the main memory 512 is connected to the baseband processor 511 and the cache memory 514 via a path 520, and stores audio data, image data, and the like.
  • the basic operation during reception is as follows.
  • a radio wave received by an antenna is converted into an intermediate frequency signal via a filter, an amplifier, a mixer, and the like.
  • the baseband processor 511 the intermediate frequency signal is demodulated into a baseband signal, which is then decomposed by a channel codec, and the necessary channel audio signal is converted into an analog audio signal by an audio codec. It is uttered from 02.
  • the baseband processor 511 stores data in the main memory 512 at any time, reads out necessary data and executes each processing.
  • the basic operation at the time of transmission is as follows.
  • step 1 a signal input from microphone 501 and digitized by a voice codec is converted by a channel codec, and shaped into a waveform suitable for transmission by a waveform shaping circuit.
  • the baseband processor 511 stores data in the main memory 512 as needed, reads out necessary data, and executes each process. Thereafter, in the RF circuit 510, the signal is modulated at an intermediate frequency, further converted to a radio frequency via a mixer or the like, amplified by an amplifier, and then transmitted from an antenna via a filter.
  • the operations related to the image capturing function of the camera 503 and the display function on the LCD 504 are performed by digitally processing the image signal captured by the camera 503 by the camera DSP 513, and further by the application processor 515. It performs data processing for display on the LCD 504 and data processing for transmission on radio waves together with voice.
  • the application processor 515 stores data in the main memory 512 as needed, and stores necessary data in the cache memory 514 by a cache operation to execute each process.
  • the signal processed for display on the LCD 504 is displayed as an image on the LCD 504. Also, put it on the radio wave with the sound
  • the signal processed for transmission is transmitted from the antenna together with the voice, and displayed as an image on the other party's LCD.
  • the signal processing device is particularly applicable to a control system for an image cache memory, and further to a control system cache system in which an image cache memory and a normal operation device cache memory are separately provided. It is useful when applied, and can be widely applied to mobile terminal systems such as mobile phones.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

L'invention concerne une unité de traitement de signal pouvant augmenter le taux de réussite tout en évitant les conflits d'entrée entre une image codée et une image de référence, effectuant une commande de cache optimale pour chaque image par la capacité, le procédé de détermination d'entrée, etc., et augmentant le taux de réussite dans le sens longitudinal tout en évitant les conflits d'entrée avec un bloc rectangulaire à proximité du sens longitudinal. L'invention concerne également un système utilisant cette unité de traitement de signal. Un système cache selon l'invention comprend une mémoire cache (111) pour image codée et une unité de commande de cache (110) associée, ainsi qu'une mémoire cache (113) pour image de référence et une unité de commande de cache (112) associée. Un circuit de sélection d'unité de commande (114) détermine si l'image est une image codée ou une image de référence d'après l'adresse à laquelle l'accès est effectué. Si l'accès est effectué à l'image codée, une commande de cache est effectuée pour l'image codée. Si l'accès est effectué à l'image de référence, une commande de cache est effectuée pour l'image de référence. De cette manière, les données à mettre en cache sont stockées dans chaque entrée indépendante.
PCT/JP2002/008236 2002-08-13 2002-08-13 Unite de traitement de signal et systeme Ceased WO2004017640A1 (fr)

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WO2008102446A1 (fr) * 2007-02-22 2008-08-28 Fujitsu Limited Dispositif de codage d'image dynamique et procédé de codage d'image dynamique
JP2009098822A (ja) * 2007-10-16 2009-05-07 Sony Corp データ処理装置及び共有メモリのアクセス方法
JP2011193453A (ja) * 2010-02-22 2011-09-29 Panasonic Corp 復号化装置及び復号化方法
JP2014513883A (ja) * 2011-03-07 2014-06-05 日本テキサス・インスツルメンツ株式会社 ビデオ符号化のためのキャッシュ方法およびシステム
CN107038127A (zh) * 2017-02-08 2017-08-11 阿里巴巴集团控股有限公司 应用系统及其缓存控制方法和装置

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JP2008061151A (ja) * 2006-09-04 2008-03-13 Fujitsu Ltd 動画像処理装置及びプリフェッチ制御方法
WO2008102446A1 (fr) * 2007-02-22 2008-08-28 Fujitsu Limited Dispositif de codage d'image dynamique et procédé de codage d'image dynamique
JP2009098822A (ja) * 2007-10-16 2009-05-07 Sony Corp データ処理装置及び共有メモリのアクセス方法
JP2011193453A (ja) * 2010-02-22 2011-09-29 Panasonic Corp 復号化装置及び復号化方法
JP2014513883A (ja) * 2011-03-07 2014-06-05 日本テキサス・インスツルメンツ株式会社 ビデオ符号化のためのキャッシュ方法およびシステム
CN107038127A (zh) * 2017-02-08 2017-08-11 阿里巴巴集团控股有限公司 应用系统及其缓存控制方法和装置

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