WO2004092913A3 - Appareil a processeur numerique avec compression de code et procede correspondant - Google Patents

Appareil a processeur numerique avec compression de code et procede correspondant Download PDF

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Publication number
WO2004092913A3
WO2004092913A3 PCT/US2004/011562 US2004011562W WO2004092913A3 WO 2004092913 A3 WO2004092913 A3 WO 2004092913A3 US 2004011562 W US2004011562 W US 2004011562W WO 2004092913 A3 WO2004092913 A3 WO 2004092913A3
Authority
WO
WIPO (PCT)
Prior art keywords
compression
compressed
digital processor
instruction cache
uncompressed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2004/011562
Other languages
English (en)
Other versions
WO2004092913A2 (fr
Inventor
Elena G Nikolova
David J Mulvaney
Vassilios Chouliaras
Jose L Nunez-Yanez
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ARC International
ARC International UK Ltd
Original Assignee
ARC International
ARC International UK Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ARC International, ARC International UK Ltd filed Critical ARC International
Publication of WO2004092913A2 publication Critical patent/WO2004092913A2/fr
Anticipated expiration legal-status Critical
Publication of WO2004092913A3 publication Critical patent/WO2004092913A3/fr
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30178—Runtime instruction translation, e.g. macros of compressed or encrypted instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/324—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address using program counter relative addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

La présente invention concerne une architecture de processeur numérique et les techniques connexes de compression de code, convenant particulièrement notamment pour des applications du type système sur microcircuit ou des applications incluses dans les cas où l'on est limité par certaines contraintes telles que la taille de mémoire. Pour un mode de réalisation particulier, la frontière entre l'espace du code comprimé, et l'espace du code non comprimé est situé entre l'antémémoire d'instruction et le coeur du processeur, coeur pour lequel la compression est complètement transparente et dont les fonctionnalités sont entièrement conservées. L'invention concerne également des mécanismes permettant la résolution des difficultés issues de non-alignement des données de l'antémémoire d'instruction et de la mise en correspondance des adresses comprimées avec les adresses non comprimées. Les techniques de compression de la présente invention réduisent l'encombrement mémoire pour la conception des circuits intégrés, ce qui amène des économies par rapport au silicium. Sinon, l'invention permet de concevoir des programmes plus encombrants, comportant plus de fonctionnalités, et ce, au même prix par comparaison à un système correspondant sans l'invention. L'invention amène aussi une réduction de la consommation d'énergie.
PCT/US2004/011562 2003-04-14 2004-04-14 Appareil a processeur numerique avec compression de code et procede correspondant Ceased WO2004092913A2 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US46318503P 2003-04-14 2003-04-14
US60/463,185 2003-04-14
US82412004A 2004-04-13 2004-04-13
US10/824,120 2004-04-13

Publications (2)

Publication Number Publication Date
WO2004092913A2 WO2004092913A2 (fr) 2004-10-28
WO2004092913A3 true WO2004092913A3 (fr) 2005-11-03

Family

ID=33303115

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/011562 Ceased WO2004092913A2 (fr) 2003-04-14 2004-04-14 Appareil a processeur numerique avec compression de code et procede correspondant

Country Status (1)

Country Link
WO (1) WO2004092913A2 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7849241B2 (en) * 2006-03-23 2010-12-07 International Business Machines Corporation Memory compression method and apparatus for heterogeneous processor architectures in an information handling system
CN111384958B (zh) * 2018-12-27 2024-04-05 上海寒武纪信息科技有限公司 数据压缩装置及相关产品
US10983915B2 (en) 2019-08-19 2021-04-20 Advanced Micro Devices, Inc. Flexible dictionary sharing for compressed caches

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6049862A (en) * 1996-07-19 2000-04-11 U.S. Philips Corporation Signal processor executing compressed instructions that are decoded using either a programmable or hardwired decoder based on a category bit in the instruction
US6138229A (en) * 1998-05-29 2000-10-24 Motorola, Inc. Customizable instruction set processor with non-configurable/configurable decoding units and non-configurable/configurable execution units
US6185670B1 (en) * 1998-10-12 2001-02-06 Intel Corporation System for reducing number of opcodes required in a processor using an instruction format including operation class code and operation selector code fields
US6199126B1 (en) * 1997-09-23 2001-03-06 International Business Machines Corporation Processor transparent on-the-fly instruction stream decompression
US6412066B2 (en) * 1996-06-10 2002-06-25 Lsi Logic Corporation Microprocessor employing branch instruction to set compression mode

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6412066B2 (en) * 1996-06-10 2002-06-25 Lsi Logic Corporation Microprocessor employing branch instruction to set compression mode
US6049862A (en) * 1996-07-19 2000-04-11 U.S. Philips Corporation Signal processor executing compressed instructions that are decoded using either a programmable or hardwired decoder based on a category bit in the instruction
US6199126B1 (en) * 1997-09-23 2001-03-06 International Business Machines Corporation Processor transparent on-the-fly instruction stream decompression
US6138229A (en) * 1998-05-29 2000-10-24 Motorola, Inc. Customizable instruction set processor with non-configurable/configurable decoding units and non-configurable/configurable execution units
US6185670B1 (en) * 1998-10-12 2001-02-06 Intel Corporation System for reducing number of opcodes required in a processor using an instruction format including operation class code and operation selector code fields

Also Published As

Publication number Publication date
WO2004092913A2 (fr) 2004-10-28

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