WO2004093162A3 - Siliziumsubstrat mit positiven ätzprofilen mit definiertem böschungswinkel und verfahren zur herstellung - Google Patents

Siliziumsubstrat mit positiven ätzprofilen mit definiertem böschungswinkel und verfahren zur herstellung Download PDF

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Publication number
WO2004093162A3
WO2004093162A3 PCT/DE2004/000804 DE2004000804W WO2004093162A3 WO 2004093162 A3 WO2004093162 A3 WO 2004093162A3 DE 2004000804 W DE2004000804 W DE 2004000804W WO 2004093162 A3 WO2004093162 A3 WO 2004093162A3
Authority
WO
WIPO (PCT)
Prior art keywords
etching
silicon substrate
steps
slope angle
production method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/DE2004/000804
Other languages
English (en)
French (fr)
Other versions
WO2004093162A2 (de
Inventor
Karola Richter
Daniel Fischer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Technische Universitaet Dresden
Original Assignee
Technische Universitaet Dresden
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Technische Universitaet Dresden filed Critical Technische Universitaet Dresden
Priority to US10/553,728 priority Critical patent/US20060219654A1/en
Priority to EP04727512A priority patent/EP1614145A2/de
Publication of WO2004093162A2 publication Critical patent/WO2004093162A2/de
Publication of WO2004093162A3 publication Critical patent/WO2004093162A3/de
Anticipated expiration legal-status Critical
Priority to US11/261,241 priority patent/US7498266B2/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H10P50/244—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials comprising alternated and repeated etching and passivation steps
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00103—Structures having a predefined profile, e.g. sloped or rounded grooves
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00555—Achieving a desired geometry, i.e. controlling etch rates, anisotropy or selectivity
    • B81C1/00563—Avoid or control over-etching
    • B81C1/00571—Avoid or control under-cutting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2203/00—Basic microelectromechanical structures
    • B81B2203/03—Static structures
    • B81B2203/0323—Grooves
    • B81B2203/033—Trenches
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2203/00—Basic microelectromechanical structures
    • B81B2203/03—Static structures
    • B81B2203/0369—Static structures characterized by their profile
    • B81B2203/0384—Static structures characterized by their profile sloped profile

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Drying Of Semiconductors (AREA)
  • Micromachines (AREA)
  • Weting (AREA)

Abstract

Die Erfindung betrifft ein Siliziumsubstrat mit positiven Ätzprofilen mit definiertem Böschungswinkel, erhältlich durch Ätzen des Siliziumsubstrates, das mit einer Maske abgedeckt ist und den folgenden Schritten : a) isotropes Ätzen des Siliziumsubstrates, wobei die Maskenunterätzung u annähernd gleich der Ätztiefe Ät ist; b) Vergrößern der Ätztiefe durch anisotropes Ätzen mit alternierend aufeinanderfolgenden Ätzund Polymerisationsschritten, wobei die Maskenunterätzung konstant bleibt und die Ätzfront einen neuen Verlauf erhält, und mit diesem Schritt die Seitenwände der Struktur mit einem Polymer belegt werden; c) Entfernen des Polymers von der Struktur; und d) Wiederholen der Schritte a) bis c) bis das vorgegebene Ätzprofil erreicht ist. Ein Verfahren ist beschrieben.
PCT/DE2004/000804 2003-04-15 2004-04-15 Siliziumsubstrat mit positiven ätzprofilen mit definiertem böschungswinkel und verfahren zur herstellung Ceased WO2004093162A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US10/553,728 US20060219654A1 (en) 2003-04-15 2004-04-15 Silicon substrate comprising positive etching profiles with a defined slope angle, and production method
EP04727512A EP1614145A2 (de) 2003-04-15 2004-04-15 Siliziumsubstrat mit positiven tzprofilen mit definiertem b schungswinkel und verfahren zur herstellung
US11/261,241 US7498266B2 (en) 2003-04-15 2005-10-27 Method for structuring of silicon substrates for microsystem technological device elements and associated silicon substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10318568.2 2003-04-15
DE10318568A DE10318568A1 (de) 2003-04-15 2003-04-15 Siliziumsubstrat mit positiven Ätzprofilen mit definiertem Böschungswinkel und Verfahren zur Herstellung

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US10/553,728 A-371-Of-International US20060219654A1 (en) 2003-04-15 2004-04-15 Silicon substrate comprising positive etching profiles with a defined slope angle, and production method
US11/261,241 Continuation-In-Part US7498266B2 (en) 2003-04-15 2005-10-27 Method for structuring of silicon substrates for microsystem technological device elements and associated silicon substrate

Publications (2)

Publication Number Publication Date
WO2004093162A2 WO2004093162A2 (de) 2004-10-28
WO2004093162A3 true WO2004093162A3 (de) 2005-02-24

Family

ID=33185711

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2004/000804 Ceased WO2004093162A2 (de) 2003-04-15 2004-04-15 Siliziumsubstrat mit positiven ätzprofilen mit definiertem böschungswinkel und verfahren zur herstellung

Country Status (4)

Country Link
US (2) US20060219654A1 (de)
EP (1) EP1614145A2 (de)
DE (1) DE10318568A1 (de)
WO (1) WO2004093162A2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10318568A1 (de) * 2003-04-15 2004-11-25 Technische Universität Dresden Siliziumsubstrat mit positiven Ätzprofilen mit definiertem Böschungswinkel und Verfahren zur Herstellung
DE102006043389A1 (de) * 2006-09-06 2008-03-27 Technische Universität Dresden Verfahren zum Plasmaätzen zur Erzeugung positiver Ätzprofile in Siliziumsubstraten
CN102910572B (zh) * 2011-08-05 2015-08-19 美新半导体（无锡）有限公司 释放mems悬桥结构的刻蚀方法
TWI513993B (zh) 2013-03-26 2015-12-21 Ind Tech Res Inst 三軸磁場感測器、製作磁場感測結構的方法與磁場感測電路
US20150011073A1 (en) * 2013-07-02 2015-01-08 Wei-Sheng Lei Laser scribing and plasma etch for high die break strength and smooth sidewall
US12188893B2 (en) 2016-08-30 2025-01-07 Analog Devices International Unlimited Company Electrochemical sensor, and a method of forming an electrochemical sensor
US11268927B2 (en) 2016-08-30 2022-03-08 Analog Devices International Unlimited Company Electrochemical sensor, and a method of forming an electrochemical sensor
US10620151B2 (en) 2016-08-30 2020-04-14 Analog Devices Global Electrochemical sensor, and a method of forming an electrochemical sensor
US11022579B2 (en) 2018-02-05 2021-06-01 Analog Devices International Unlimited Company Retaining cap
CN109725375A (zh) * 2018-12-21 2019-05-07 中国电子科技集团公司第四十四研究所 一种ⅲ-ⅴ族材料纳米光栅刻蚀方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4241045C1 (de) * 1992-12-05 1994-05-26 Bosch Gmbh Robert Verfahren zum anisotropen Ätzen von Silicium
EP0822582A2 (de) * 1996-08-01 1998-02-04 Surface Technology Systems Limited Verfahren zur Behandlung der Oberfläche von halbleitenden Substraten
DE19736370A1 (de) * 1997-08-21 1999-03-04 Bosch Gmbh Robert Verfahren zum anisotropen Ätzen von Silizium
US6180466B1 (en) * 1997-12-18 2001-01-30 Advanced Micro Devices, Inc. Isotropic assisted dual trench etch
US6198150B1 (en) * 1996-12-23 2001-03-06 Intersil Corporation Integrated circuit with deep trench having multiple slopes

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US4639288A (en) * 1984-11-05 1987-01-27 Advanced Micro Devices, Inc. Process for formation of trench in integrated circuit structure using isotropic and anisotropic etching
US4855017A (en) * 1985-05-03 1989-08-08 Texas Instruments Incorporated Trench etch process for a single-wafer RIE dry etch reactor
US4902377A (en) * 1989-05-23 1990-02-20 Motorola, Inc. Sloped contact etch process
JPH0428229A (ja) * 1990-05-23 1992-01-30 Mitsubishi Electric Corp コンタクトホールの形成方法およびエッチング装置
JPH08186095A (ja) * 1994-12-28 1996-07-16 Kawasaki Steel Corp コンタクトホールの形成方法およびエッチング装置
US6117786A (en) * 1998-05-05 2000-09-12 Lam Research Corporation Method for etching silicon dioxide using fluorocarbon gas chemistry
US6235643B1 (en) * 1999-08-10 2001-05-22 Applied Materials, Inc. Method for etching a trench having rounded top and bottom corners in a silicon substrate
US6458615B1 (en) * 1999-09-30 2002-10-01 Carnegie Mellon University Method of fabricating micromachined structures and devices formed therefrom
US6582861B2 (en) * 2001-03-16 2003-06-24 Applied Materials, Inc. Method of reshaping a patterned organic photoresist surface
GB2378314B (en) * 2001-03-24 2003-08-20 Esm Ltd Process for forming uniform multiple contact holes
DE10318568A1 (de) * 2003-04-15 2004-11-25 Technische Universität Dresden Siliziumsubstrat mit positiven Ätzprofilen mit definiertem Böschungswinkel und Verfahren zur Herstellung
US7179717B2 (en) * 2005-05-25 2007-02-20 Micron Technology, Inc. Methods of forming integrated circuit devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4241045C1 (de) * 1992-12-05 1994-05-26 Bosch Gmbh Robert Verfahren zum anisotropen Ätzen von Silicium
EP0822582A2 (de) * 1996-08-01 1998-02-04 Surface Technology Systems Limited Verfahren zur Behandlung der Oberfläche von halbleitenden Substraten
US6198150B1 (en) * 1996-12-23 2001-03-06 Intersil Corporation Integrated circuit with deep trench having multiple slopes
DE19736370A1 (de) * 1997-08-21 1999-03-04 Bosch Gmbh Robert Verfahren zum anisotropen Ätzen von Silizium
US6180466B1 (en) * 1997-12-18 2001-01-30 Advanced Micro Devices, Inc. Isotropic assisted dual trench etch

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
VOLLAND B ET AL: "Dry etching with gas chopping without rippled sidewalls", JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B: MICROELECTRONICS PROCESSING AND PHENOMENA, AMERICAN VACUUM SOCIETY, NEW YORK, NY, US, vol. 17, no. 6, November 1999 (1999-11-01), pages 2768 - 2771, XP012007814, ISSN: 0734-211X *

Also Published As

Publication number Publication date
DE10318568A1 (de) 2004-11-25
US20060099811A1 (en) 2006-05-11
US20060219654A1 (en) 2006-10-05
US7498266B2 (en) 2009-03-03
EP1614145A2 (de) 2006-01-11
WO2004093162A2 (de) 2004-10-28

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