WO2004107402A2 - Capture smart pour une production de modele de test automatique (atpg) et simulation de defaillances de circuits integres a balayage - Google Patents

Capture smart pour une production de modele de test automatique (atpg) et simulation de defaillances de circuits integres a balayage Download PDF

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Publication number
WO2004107402A2
WO2004107402A2 PCT/US2004/014525 US2004014525W WO2004107402A2 WO 2004107402 A2 WO2004107402 A2 WO 2004107402A2 US 2004014525 W US2004014525 W US 2004014525W WO 2004107402 A2 WO2004107402 A2 WO 2004107402A2
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Prior art keywords
clock
blocks
clock domain
cross
scan
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Ceased
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PCT/US2004/014525
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English (en)
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WO2004107402A3 (fr
Inventor
Laung-Terng Wang (L.-T.)
Khader S. Abdel-Hafez
Xiaoqing Wen
Boryau Jack Sheu
Shun-Miin Sam Wang
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Syntest Technologies Inc
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Syntest Technologies Inc
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Priority claimed from US10/850,460 external-priority patent/US7124342B2/en
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Publication of WO2004107402A2 publication Critical patent/WO2004107402A2/fr
Publication of WO2004107402A3 publication Critical patent/WO2004107402A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/318547—Data generators or compressors

Definitions

  • the present invention generally relates to the field of scan-based design and test using design-for-test (OFT) techniques. Specifically, the present invention relates to the field of Scan/ ATPG (automatic test pattern generation), Logic BIST (built-in self-test), and Compressed Scan/ATPG.
  • OFT design-for-test
  • integrated circuit is used to describe a chip or MCM (multi-chip module) embedded with DFT (design-for- test) techniques.
  • An integrated circuit or circuit assembly generally contains multiple clocks, which are either generated internally or supplied externally. Each clock is distributed to a set of storage elements via a skew-minimized network, which supplies clock pulses to all storage elements essentially at the same time. Such a clock, its related storage elements, and all combinational logic blocks bounded by these storage elements, form a clock domain. While the clock skew within a single clock domain is designed to be negligible, the clock skew between different clock domains is unbounded and can vary greatly for different storage elements.
  • Scan-based design is the most widely used design-for-test (DFT) approach for producing high-quality integrated circuits.
  • DFT design-for-test
  • Scan-based design requires that all storage elements in an integrated circuit, such as D flip-flops, be replaced with their scan-equivalent storage elements, such as Scan D flip- flops, otherwise known as scan cells.
  • These scan cells are connected to form one or more scan chains, with each scan chain being controlled by one or more scan enable (SE) signals and capture clocks (CK) each belonging to a separate clock or frequency domain.
  • SE scan enable
  • CK capture clocks
  • a scan-based integrated circuit proceeds in a sequence of shift-in/shift-out operation and capture operation, repeated for a predetermined number of test patterns.
  • scan enable (SE) signals local to all scan cells in a clock domain, are used to configure all scan cells in an integrated circuit into scan chains by selecting the scan data inputs as the input source of all scan cells in the scan chains, and a predetermined stimuli during scan-test or a pseudorandom stimuli during self-test is shifted serially through the scan chains into all scan cells in the circuit.
  • the scan enable (SE) signal is used to select the data inputs as the input source of all scan cells to test the functional path of the circuit using the stimulus loaded during the shift operation.
  • Prior-art solution #2 see FIG. 3, is described in U.S. Pat. No. 6,195,776 by Ruiz et al. (2001).
  • a clock order is used to apply selected capture clocks sequentially during the capture operation.
  • these capture clocks are simulated in parallel while selectively setting unknown values ('X') on different logic paths, depending on the clock order. This guarantees that the results of the parallel cycle-based simulation will match the results of the sequential application of the clocks during the actual capture operation of the test pattern.
  • the main advantage of this approach is that it achieves the same fault coverage as prior-art #1 using a smaller set of test vectors and reduced CPU time.
  • test size still large, since the ATPG and fault simulator are pessimistic in calculating the fault coverage of different scan test patterns due to the unknown values.
  • Prior-art solution #3 see FIG. 4, is described by Lin et al.
  • a clock order is used to apply selected capture clocks sequentially during the capture operation.
  • Multi-timeframe ATPG and fault simulation is used during the capture operation to calculate the exact fault coverage of the test patterns applied.
  • the main advantage of this approach is that the test size is smaller than the previous two approaches, and can approach the optimal set of test vectors, provided that all clocks are applied during the capture operation of the ATPG and fault simulation. In practice, this is difficult to perform, since it results in a dramatic increase in CPU time requirements. In practice, the number of clocks that can be applied is limited, resulting in a sub-optimal set of test patterns using longer CPU time.
  • Prior-art solution #4 see FIG. 5, is described in United States Patent Application No. 20020184560 by Wang et al.
  • a clock order is used to apply selected capture clocks sequentially during the capture operation.
  • a circuit expansion process is used to transform the circuit into an equivalent combinational circuit model, where logic paths are expanded to simulate the results of a multi-timeframe simulation with a single time-frame simulation of the expanded circuit.
  • the main advantage of this approach is that its test size is small, and approaches the optimum set of test vectors for any given circuit. Furthermore, this is accomplished with a realistic increase in memory size, as opposed to an unrealistic increase in CPU time as in prior-art #3.
  • the main disadvantage of this approach is that the increase in memory size might prevent the circuit from being able to fit within a given system memory, and might become un-reasonable as design size continues to grow.
  • the present invention is intended to achieve three objectives: (1) providing an improved ATPG (automatic test pattern generation) and fault simulation method capable of using a cycle-based logic simulator to simulate multiple-clock events and generate an optimal set of test patterns with low memory usage and short CPU time, (2) providing a method for conducting clock grouping and clock ordering automatically and efficiently, and (3) providing a method to improve the efficiency of the method of prior-art #2 summarized in BACKGROUND and detailed in U.S. Pat. No. 6,195,776 by Ruiz et al. (2001).
  • the present invention further comprises a CAD (computer-aided design) system that implements the methods.
  • the present invention is summarized as follow:
  • the present invention comprises any method that uses a hybrid ATPG and fault simulation approach capable of selectively using the circuit expansion or multi-timeframe simulation method in conjunction with any number of other prior-art methods.
  • This hybrid method allows the testing of all cross-clock domain blocks in a circuit while meeting input constraints regarding required memory usage, required CPU time and required test-pattern count. This is done by selectively grouping the clock domains into clock domain groups, and performing circuit expansion or a multi-timeframe simulation on selected clock domain groups and cross-clock domain blocks, while selecting other prior-art methods to test the remaining clock domain groups and cross-clock domain blocks to meet the required criteria.
  • the purpose of clock grouping in the present invention is to conduct circuit expansion on the combinational logic blocks related to the grouped clocks.
  • the present invention comprises any method that identifies those clocks which, when grouped together and for which circuit expansion is conducted, will best improve the performance of ATPG and fault simulation.
  • the present invention comprises any method that merges a set of clock domains together. For example, suppose that one clock domain CDl interacts to another clock domain CD2 through a cross-clock domain logic block CCD12. Also suppose that CDl is captured before CD2. Merging CDl and CD2 together means that two-time frames will be used for circuit transformation related to the two clock domains and their corresponding cross- clock domain logic blocks.
  • the benefits are as follows: Even the clock domain CD2 is captured after the clock domain CDl is captured, the controllability of the cross-clock domain logic block CCD12 is still high since the clock domain CDl is also transformed to obtain the values in the clock domain CDl after it is captured. As a result, all faults in the cross-clock domain logic block CCD12 can be detected or located.
  • the benefit of clock domain grouping is that it can reduce the number of necessary ordered sequences of capture clocks.
  • a domain-interconnect graph is a directed graph, which is used to represent the relationship among all clock domains.
  • a node represents a clock domain while a directed edge between any two nodes represents the corresponding cross-clock domain logic block.
  • Such a domain-interconnect graph can be built based on the result of analyzing clock domains. Based on such a domain-interconnect graph, an optimal or near-optimal set of capture orders can be selected automatically.
  • prior-art #2 simulates all capture clocks in parallel by selectively setting unknown (X) values on different logic paths, depending on the clock order.
  • the present invention comprises any method that generalizes this unknown-value based method into a constrained-value method. This is achieved by allowing the constraining of a cross-clock domain logic block with logic values, 1 and 0, as well as unknown-values, X's, to force an ATPG program to generate patterns where the cross-clock domain logic block does not change its state during a capture operation.
  • a fault simulator can perform an accurate fault simulation of patterns where the cross-clock domain logic remains in a constant state during a capture operation. This further improves the accuracy of the fault simulation and ATPG of the unknown-value method. Therefore, a smaller test pattern set and greater measured fault coverage can be achieved.
  • the present invention uses a hybrid approach for ATPG and fault simulation based on circuit expansion, which is supported by automatic clock grouping and capture order selection.
  • the present invention uses a new technique to improve the efficiency of an existing multiple timeframe handling solution for ATPG and fault simulation.
  • the present invention provides an efficient solution to ATPG and fault simulation for testing complicated and large-scale scan-based integrated circuits or circuit assemblies by achieving high fault coverage for stuck-at faults, bridging faults, IDDQ faults, transition faults launched from capture, transition faults launched from shift, path-delay faults launched from capture, and path-delay faults launched from shift, with lower memory usage and a smaller number of test patterns.
  • FIG. 1 shows a block diagram of a scan-based integrated circuit with three clock domains, inter-related with each other through six cross-clock domain blocks;
  • FIG. 2A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with regard to prior-art solution #1;
  • FIG. 2B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation in order to detect or locate stuck-at faults, bridging faults, or IDDQ faults, with regard to prior-art solution #1;
  • FIG. 2C shows the scan clock waveforms in actual test application in order to detect or locate stuck-at faults, bridging faults, or IDDQ faults, with regard to prior-art solution #1 ;
  • FIG. 3A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with regard to prior-art solution #2;
  • FIG. 3B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation in order to detect or locate stuck-at faults, bridging faults, or IDDQ faults, with regard to prior-art solution #2;
  • FIG. 3C shows the scan clock waveforms in actual test application in order to detect or locate stuck-at faults, bridging faults, or IDDQ faults, with regard to prior-art solution #2;
  • FIG. 4A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with regard to prior-art solution #3;
  • FIG. 4B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation in order to detect or locate stuck-at faults, bridging faults, or IDDQ faults, with regard to prior-art solution #3;
  • FIG. 4C shows the scan clock waveforms in actual test application in order to detect or locate stuck-at faults, bridging faults, or IDDQ faults, with regard to prior-art solution #3;
  • FIG. 5A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with regard to prior-art solution #4;
  • FIG. 5B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation in order to detect or locate stuck-at faults, bridging faults, or IDDQ faults, with regard to prior-art solution #4;
  • FIG. 5C shows the scan clock waveforms in actual test application in order to detect or locate stuck-at faults, bridging faults, or IDDQ faults, with regard to prior-art solution #4;
  • FIG. 6A shows a flow diagram of the method for ATPG (automatic test pattern generation) and fault simulation with clock grouping and circuit expansion in scan-test mode, in accordance with the present invention
  • FIG. 6B shows a flow diagram of the method for fault simulation with clock grouping and circuit expansion in self-test mode, in accordance with the present invention
  • FIG. 7A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in a first embodiment of the present invention
  • FIG. 7B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation in order to detect or locate stuck-at faults, bridging faults, or IDDQ faults, with regard to clock grouping in a first embodiment of the present invention
  • FIG. 7C shows the scan clock waveforms in actual test application in order to detect or locate stuck-at faults, bridging faults, or IDDQ faults, with regard to clock grouping in a first embodiment of the present invention
  • FIG. 8A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in a second embodiment of the present invention
  • FIG. 8B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation in order to detect or locate stuck-at faults, bridging faults, or IDDQ faults, with regard to clock grouping in a second embodiment of the present invention
  • FIG. 8C shows the scan clock waveforms in actual test application in order to detect or locate stuck-at faults, bridging faults, or IDDQ faults, with regard to clock grouping in a second embodiment of the present invention
  • FIG. 9A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in a third embodiment of the present invention
  • FIG. 9B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation in order to detect or locate stuck-at faults, bridging faults, or IDDQ faults, with regard to clock grouping in a third embodiment of the present invention
  • FIG. 9C shows the scan clock waveforms in actual test application in order to detect or locate stuck-at faults, bridging faults, or IDDQ faults, with regard to clock grouping in a third embodiment of the present invention
  • FIG. 10A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in a fourth embodiment of the present invention
  • FIG. 10B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation in order to detect or locate transition faults or path-delay faults launched from capture, with regard to clock grouping in a fourth embodiment of the present invention
  • FIG. 10C shows the scan clock waveforms in actual test application in order to detect or locate transition faults or path-delay faults launched from capture, with regard to clock grouping in a fourth embodiment of the present invention
  • FIG. 1 1 A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in a fifth embodiment of the present invention
  • FIG. 1 IB shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation in order to detect or locate transition faults or path-delay faults launched from capture, with regard to clock grouping in a fifth embodiment of the present invention
  • FIG. 1 1C shows the scan clock waveforms in actual test application in order to detect or locate transition faults or path-delay faults launched from capture, with regard to clock grouping in a fifth embodiment of the present invention
  • FIG. 12A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in a sixth embodiment of the present invention
  • FIG. 12B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation in order to detect or locate transition faults or path-delay faults launched from capture, with regard to clock grouping in a sixth embodiment of the present invention
  • FIG. 12C shows the scan clock waveforms in actual test application in order to detect or locate transition faults or path-delay faults launched from capture, with regard to clock grouping in a sixth embodiment of the present invention
  • FIG. 13A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in a seventh embodiment of the present invention
  • FIG. 13B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation in order to detect or locate transition faults or path-delay faults launched from shift, with regard to clock grouping in a seventh embodiment of the present invention
  • FIG. 13C shows the scan clock waveforms in actual test application in order to detect or locate transition faults or path-delay faults launched from shift, with regard to clock grouping in a seventh embodiment of the present invention
  • FIG. 14A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in an eighth embodiment of the present invention
  • FIG. 14B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation in order to detect or locate transition faults or path-delay faults launched from shift, with regard to clock grouping in an eighth embodiment of the present invention
  • FIG. 14C shows the scan clock waveforms in actual test application in order to detect or locate transition faults or path-delay faults launched from shift, with regard to clock grouping in an eighth embodiment of the present invention
  • FIG. 15A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in a ninth embodiment of the present invention
  • FIG. 15B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation in order to detect or locate transition faults or path-delay faults launched from shift, with regard to clock grouping in a ninth embodiment of the present invention
  • FIG. 15C shows the scan clock waveforms in actual test application in order to detect or locate transition faults or path-delay faults launched from shift, with regard to clock grouping in a ninth embodiment of the present invention
  • FIG. 16A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in a tenth embodiment of the present invention
  • FIG. 16B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation in order to detect or locate stuck-at faults, bridging faults, or IDDQ faults, with regard to clock grouping in a tenth embodiment of the present invention
  • FIG. 16C shows the scan clock waveforms in actual test application in order to detect or locate stuck-at faults, bridging faults, or IDDQ faults, with regard to clock grouping in a tenth embodiment of the present invention
  • FIG. 17A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in an eleventh embodiment of the present invention
  • FIG. 17B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation in order to detect or locate stuck-at faults, bridging faults, or IDDQ faults, with regard to clock grouping in an eleventh embodiment of the present invention
  • FIG. 17C shows the scan clock waveforms in actual test application in order to detect or locate stuck-at faults, bridging faults, or IDDQ faults, with regard to clock grouping in an eleventh embodiment of the present invention
  • FIG. 18A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in a twelfth embodiment of the present invention
  • FIG. 18B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation in order to detect or locate transition faults or path-delay faults launched from capture, with regard to clock grouping in a twelfth embodiment of the present invention
  • FIG. 18C shows the scan clock waveforms in actual test application in order to detect or locate transition faults or path-delay faults launched from capture, with regard to clock grouping in a twelfth embodiment of the present invention
  • FIG. 19A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in a thirteenth embodiment of the present invention
  • FIG. 19B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation in order to detect or locate transition faults or path-delay faults launched from capture, with regard to clock grouping in a thirteenth embodiment of the present invention
  • FIG. 19C shows the scan clock waveforms in actual test application in order to detect or locate transition faults or path-delay faults launched from capture, with regard to clock grouping in a thirteenth embodiment of the present invention
  • FIG. 20A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in a fourteenth embodiment of the present invention
  • FIG. 20B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation in order to detect or locate transition faults or path-delay faults launched from shift, with regard to clock grouping in a fourteenth embodiment of the present invention
  • FIG. 20C shows the scan clock waveforms in actual test application in order to detect or locate transition faults or path-delay faults launched from shift, with regard to clock grouping in a fourteenth embodiment of the present invention
  • FIG. 21 A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in a fifteenth embodiment of the present invention
  • FIG. 21 B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation in order to detect or locate transition faults or path-delay faults launched from shift, with regard to clock grouping in a fifteenth embodiment of the present invention
  • FIG. 21C shows the scan clock waveforms in actual test application in order to detect or locate transition faults or path-delay faults launched from shift, with regard to clock grouping in a fifteenth embodiment of the present invention
  • FIG. 22A shows a domain-interconnect graph for 8 inter-related clock domains
  • FIG. 22B shows the fault detection or location range for one ordered sequence of capture clocks for the clock domains shown in FIG. 22A, in accordance with the present invention, where clock domain grouping is conducted;
  • FIG. 23 A shows a domain-interconnect graph for 5 inter-related clock domains
  • FIG. 23B shows the fault detection or location range for one ordered sequence of capture clocks for the clock domains shown in FIG. 23 A, in accordance with the present invention
  • FIG. 23C shows the fault detection or location range for one more ordered sequence of capture clocks for the clock domains shown in FIG. 23 A, in accordance with the present invention
  • FIG. 23D shows the fault detection or location range for one ordered sequence of capture clocks for the clock domains shown in FIG. 23 A, in accordance with the present invention, where clock domain merging is conducted;
  • FIG. 24A shows a prior art solution for handling uncontroUability when using a single time-frame for the multiple-capture scheme
  • FIG. 24B shows an embodiment of the method for handling uncontroUability when using a single time-frame for the multiple-capture scheme, in accordance with the present invention.
  • FIG. 25 shows an electronic design automation system, where a computer-readable program, in accordance with the present invention, performs clock grouping and circuit expansion based ATPG (automatic test pattern generation) and fault simulation for a scan-based integrated circuit.
  • ATPG automatic test pattern generation
  • FIG. 1 shows a block diagram of a scan-based integrated circuit 101 with three inter-related clock domains, CDl 102 to CD3 104, and three scan clocks, CK1 120 to CK3 122. Each clock controls one clock domain.
  • CDl 102 interacts to CD2 103 through the cross-clock domain block CCD12 105
  • CD2 103 interacts to CDl 102 through the cross-clock domain block CCD21 106
  • CD2 103 interacts to CD3 104 through the cross-clock domain block CCD23 107
  • CD3 104 interacts to CD2 103 through the cross- clock domain block CCD32 108
  • CDl 102 interacts to CD3 104 through the cross-clock domain block CCD13 109
  • CD3 104 interacts to CDl 102 through the cross-clock domain block CCD31 110.
  • the CUT (circuit-under-test) 101 is a scan-based integrated circuit, in which all of its storage cells are replaced with scan cells SC and all scan cells SC are connected into one or more scan chains SCN.
  • a scan cell is usually a clocked storage cell with two input ports, one called a data input port and the other called a scan input port, selectable with a scan enable (SE) signal.
  • SE scan enable
  • the data input port is connected to functional logic, which is used to capture test responses.
  • the scan input port is connected to the output port of another scan cell or to an external scan input signal; this way, a scan chain, i.e. shift register, can be formed to bring in test stimuli or bring out captured test responses.
  • the CUT 101 can be tested in either scan-test mode or self-test mode.
  • the two modes differ in how test stimuli, 114 to 116, are generated and provided, how test responses, 1 17 to 119, are collected and analyzed, and how scan enable signals, SE1 111 to SE3 113, and scan clocks, CK1 120 to CK3 122, are controlled.
  • test stimuli, 114 to 116 are generated by an ATPG (automatic test pattern generation) program and applied by an ATE (automatic test equipment).
  • the ATE also collects and analyzes test responses, 117 to 119, and controls all scan enable signals SE1 111 to SE3 113, and scan clocks, CK1 120 to CK3 122.
  • test stimuli 114 to 116
  • PRPG pseudo-random pattern generator
  • test responses 117 to 119
  • MISR multi-input signature register
  • Scan enable signals, SE1 111 to SE3 113, and scan clocks, CK1 120 to CK3 122, are also controlled by on- chip circuitry in self-test mode.
  • test is conducted by repeating two operations: namely shift and capture.
  • all scan cells SC are configured into one or more scan chains SCN, i.e. shift registers, by properly controlled scan enable signals, SE1 111 to SE3 113.
  • Test stimuli, 114 to 116 are then shifted into these scan chains SCN.
  • all scan cells SC are configured by properly controlled scan enable signals, SE1 111 to SE3 113, to catch data from their data input ports.
  • test responses, 117 to 119, corresponding to the test stimuli, 114 to 116, shifted into scan cells during the shift operation are captured into scan cells SC by activating scan clocks CK1 120 to CK3 122 in one way or another.
  • captured test responses are shifted out of the CUT to either ATE in scan-test mode or to MISR in self-test mode.
  • new test stimuli are also shifted in. 0095
  • both scan-test and self-test consist of an ATPG and fault simulation process. Test stimuli are either generated by an ATPG or by a PRPG and fault simulation is often needed to check if a fault is detected by a test stimulus or test pattern. In ATPG and fault simulation, it is necessary to assume what logic values are captured as test responses during a capture operation.
  • FIG. 2A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with regard to prior-art solution #1.
  • 3 nodes are used to represent the 3 clock domains, CDl 102 to CD3 104.
  • the corresponding scan clocks, CK1 120 to CK3 122, are also shown in the nodes for easy comprehension.
  • the directed edge between two nodes represents a cross-clock domain block.
  • the edge 201 represents the cross-clock domain block CCD12 105 as shown in FIG. 1.
  • FIG. 2B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation and FIG. 2C shows the scan clock waveforms in actual test application, both for detecting or locating stuck-at faults, bridging faults, or IDDQ faults (referred to as faults) and with regard to prior-art solution #1.
  • this solution also called the one-hot technique, requires that only one scan clock be activated during each capture operation as shown in FIG. 2C.
  • scan clocks are activated in this manner, the circuit behavior during a capture operation can be fully represented by only one copy of the corresponding combinational logic portion in the circuit, for the purpose of ATPG and fault simulation.
  • the impact of unpredictable clock skews can be easily avoided in ATPG and fault simulation.
  • FIG. 3 A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with regard to prior-art solution #2.
  • the meanings of nodes and edges are the same as explained for FIG. 2A.
  • FIG. 3B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation and FIG. 3C shows the scan clock waveforms in actual test application, both for detecting or locating stuck-at faults, bridging faults, or IDDQ faults (referred to as faults) and with regard to prior-art solution #2.
  • this solution requires that scan clocks, CKl 120 to CK3 122, be activated one by one in a selected order during each capture operation, and that the capture pulse delays between CKl 120 and CK2 121 and between CK2 121 and CK3 122 are larger than the possible corresponding clock skews. This will guarantee that the test responses captured during a capture operation are not affected by unpredictable clock skews.
  • FIG. 4A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with regard to prior-art solution #3.
  • the meanings of nodes and edges are the same as explained for FIG. 2A.
  • FIG. 4B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation and FIG. 4C shows the scan clock waveforms in actual test application, both for detecting or locating stuck-at faults, bridging faults, or IDDQ faults (referred to as faults) and with regard to prior-art solution #3.
  • this solution requires that scan clocks, CKl 120 to CK3 122, be activated one by one in a selected order during each capture operation, and that the capture pulse delays between CKl 120 and CK2 121 and between CK2 121 and CK3 122 are larger than the possible corresponding clock skews. This will guarantee that the test responses captured during a capture operation are not affected by unpredictable clock skews.
  • FIG. 5A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with regard to prior-art solution #4.
  • the meanings of nodes and edges are the same as explained for FIG. 2A.
  • FIG. 5B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation and FIG. 5C shows the scan clock waveforms in actual test application, both for detecting or locating stuck-at faults, bridging faults, or IDDQ faults (referred to as faults) and with regard to prior-art solution #4.
  • this solution requires that scan clocks, CKl 120 to CK3 122, be activated one by one in a selected order during each capture operation, and that the capture pulse delays between CKl 120 and CK2 121 and between CK2 121 and CK3 122 are larger than the possible corresponding clock skews. This will guarantee that the test responses captured during a capture operation are not affected by unpredictable clock skews.
  • circuit expansion is a circuit modeling technique that uses multiple copies of a block to represent the different state of the block at different times. Note that circuit expansion needs to be conducted under a given order of capture clock pulses. In the example shown in FIG. 5B and FIG.
  • the capture order is CKl 120 ⁇ CK2 121 ⁇ CK3 122.
  • Different capture orders will result in different results of circuit expansion. Obviously, after circuit expansion, it is not necessary to handle scan clocks explicitly and ATPG and fault simulation can be complete conducted on a combinational circuit model.
  • This solution can use a combinational ATPG program when test patterns are to be generated deterministically. Fault coverage is high since all faults in a whole circuit can be targeted in ATPG and fault simulation. The CPU time is also less than that of prior-art solution #3 since the latter needs to use a sequential ATPG program. The number of test pattern is smaller than that of prior-art solution #1 and prior-art solution #2 since a fault in any clock domain or any cross-clock domain block can be targeted in ATPG and fault simulation corresponding to any capture operation. However, the memory usage may be high in some cases since multiple copies of the same block may be needed at the same time.
  • FIG. 6A shows a flow diagram of the method for ATPG (automatic test pattern generation) and fault simulation with clock grouping and circuit expansion in scan-test mode, in accordance with the present invention.
  • the method accepts the user-supplied RTL (register-transfer level) or gate-level HDL (hardware design language) code 601 representing a scan-based integrated circuit design.
  • input constraints 602 and an optional foundry library 603 are also provided.
  • the input constraints 602 contain input constraint information on all clocks and scan enable (SE) signals.
  • This method consists of compilation 604, model transformation 607, predetermined pattern fault simulation 609, ATPG 610, and post-processing 611.
  • the compilation step 604 compiles the HDL code 601 into a sequential circuit model 605.
  • the model transformation step 607 converts the sequential circuit model 605 into an equivalent combinational circuit model 608. Circuit expansion based on the clock grouping information 606 is also conducted at this step.
  • the predetermined pattern fault simulation step 609 identifies the faults that are detected by a set of predetermined patterns.
  • the ATPG step 610 generates test patterns for detecting faults.
  • the post-processing step 611 generates HDL test benches and ATE (automatic test equipment) test programs 612. All reports and errors are stored in the report files 613.
  • FIG. 6B shows a flow diagram of the method for fault simulation with clock grouping and circuit expansion in self-test mode, in accordance with the present invention.
  • the method accepts the user-supplied RTL (register-transfer level) or gate-level HDL (hardware design language) code 651 representing a scan-based integrated circuit design.
  • input constraints 652 and an optional foundry library 653 are also provided.
  • the input constraints 652 contain input constraint information on all clocks and scan enable (SE) signals.
  • This method consists of compilation 654, model transformation 657, pseudo-random pattern fault simulation 659, and postprocessing 660.
  • the compilation step 654 compiles the HDL code 651 into a sequential circuit model 655.
  • the model transformation step 657 converts the sequential circuit model 655 into an equivalent combinational circuit model 658. Circuit expansion based on the clock grouping information 656 is also conducted at this step.
  • the pseudo-random pattern fault simulation step 659 identifies the faults that are detected by a set of pseudo-random patterns.
  • the post-processing step 660 generates HDL test benches and ATE (automatic test equipment) test programs 661. All reports and errors are stored in the report files 662.
  • FIG. 7A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in a first embodiment of the present invention. 3 nodes are used to represent the 3 clock domains, CDl 102 to CD3 104. The corresponding scan clocks, CKl
  • the directed edge between two nodes represents a cross-clock domain block.
  • the edge 701 represents the cross-clock domain block CCD12 105 as shown in FIG. 1.
  • FIG. 7B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation and FIG. 7C shows the scan clock waveforms in actual test application, both for detecting or locating stuck-at faults, bridging faults, or IDDQ faults, (referred to as faults) with regard to clock grouping in a first embodiment of the present invention.
  • clock group CGI 707 captures, a capture order of CKl 120 ⁇ CK2 121 is used.
  • scan clocks CKl 120 and CK2 121 are allowed to capture one by one during a capture operation but the capture pulse delay between CKl 120 and CK2 121 should be larger than the possible corresponding clock skew.
  • a clock group contains only one scan clock, the circuit behavior when the scan clock captures can be fully represented by only one copy of the corresponding combinational logic portion in the circuit. If a clock group contains multiple scan clocks, this embodiment conducts circuit expansion in order to represent the circuit behavior with only one set of circuit data. The reason why this is possible is that circuit expansion uses multiple copies of a logic block to represent the different state of the block at different times. In FIG.
  • circuit expansion is conducted for clock domains CDl 102 and CD2 103.
  • circuit expansion can also be conducted for cross-clock domain blocks between CDl 102 and CD2 103.
  • scan clocks CKl 120 and CK2 121 capture, all faults in clock domains CDl 102 and CD2 103 as well as cross-clock domain blocks between CDl 102 and CD2 103 can be targeted.
  • scan clock CK3 122 captures, all faults in clock domains CD3 104 as well as cross-clock domain blocks CCD13 109 and CCD23 107 can be targeted.
  • This embodiment of the present invention only needs a combinational ATPG program when test patterns are to be generated deterministically.
  • this embodiment can alleviate the disadvantages of both prior-art solution #1 and prior-art solution #4.
  • the number of test patterns will be smaller than that of prior-art solution #1 since any fault in clock domains CDl 102 and CD2 103 can be targeted during the same capture operation.
  • the memory usage will be less than that of prior-art solution #4 since circuit expansion is only conducted for part of a circuit.
  • FIG. 8 A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in a second embodiment of the present invention.
  • the meanings of nodes, edges, and clock groups are the same as explained in FIG. 7A.
  • FIG. 8B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation and
  • FIG. 8C shows the scan clock waveforms in actual test application, both for detecting or locating stuck-at faults, bridging faults, or IDDQ faults, (referred to as faults) with regard to clock grouping in a second embodiment of the present invention.
  • This embodiment requires that all scan clocks be grouped into a set of clock groups and that the clock groups be activated one by one in a selected order during each capture operation. In addition, the capture pulse delays between each clock group should be larger than the possible corresponding clock skew. Furthermore, if a clock group contains multiple scan clocks, this embodiment requires that the scan clocks are activated one by one in a selected order and that the capture pulse delay between any scan clocks is larger than the possible corresponding clock skew.
  • a capture order of CKl 120 ⁇ CK2 121 is used. That is, scan clocks CKl 120 and CK2 121 are allowed to capture one by one during a capture operation but the capture pulse delay between CKl 120 and CK2 121 should be larger than the possible corresponding clock skew.
  • the circuit behavior during a capture operation can only be fully represented by several copies of the corresponding combinational logic portion in the circuit, each with a different set of constraints on its inputs and outputs and each corresponding to a different timeframe, for the purpose of ATPG and fault simulation.
  • This embodiment only selects one copy of the combinational logic portion. Obviously, some constraints on the inputs and outputs of the selected copy have to be set to unknown (X) values since other related copies are discarded.
  • this embodiment conducts circuit expansion in order to represent the corresponding circuit behavior with only one set of circuit data.
  • circuit expansion uses multiple copies of a logic block to represent the different state of the block at different times.
  • circuit expansion is conducted for clock domains CDl 102 and CD2 103.
  • circuit expansion can also be conducted for cross-clock domain blocks between CDl 102 and CD2 103.
  • ATPG and fault simulation for the clock domains CDl 102 and CD2 103, it is necessary to assign unknown values to the signal lines coming from CCD31 110 and CCD32 108.
  • only one expanded copy of the clock domains CDl 102 and CD2 103 is used. This way, the ATPG results are guaranteed to be accurate even clock skews may exist between different clock domains.
  • This embodiment of the present invention only needs a combinational ATPG program when test patterns are to be generated deterministically.
  • this embodiment can alleviate the disadvantages of both prior-art solution #2 and prior-art solution #4.
  • the fault coverage of this embodiment will be higher than that of prior-art solution #2 since a smaller number of unknown values are assigned.
  • the memory usage will be less than that of prior-art solution #4 since circuit expansion is only conducted for part of a circuit.
  • FIG. 9A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1 , with clock grouping in a third embodiment of the present invention.
  • the meanings of nodes, edges, and clock groups are the same as explained in FIG. 7A.
  • FIG. 9B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation
  • FIG. 9C shows the scan clock waveforms in actual test application, both for detecting or locating stuck-at faults, bridging faults, or IDDQ faults, (referred to as faults) with regard to clock grouping in a third embodiment of the present invention.
  • This embodiment requires that all scan clocks be grouped into a set of clock groups and that the clock groups be activated one by one in a selected order during each capture operation. In addition, the capture pulse delays between each clock group should be larger than the possible corresponding clock skew.
  • clock group CGI 908 captures
  • a capture order of CKl 120 - CK2 121 is assumed. That is, scan clocks CKl 120 and CK2 121 are allowed to capture one by one during a capture operation but the capture pulse delay between CKl 120 and CK2 121 should be larger than the possible corresponding clock skew.
  • circuit behavior during a capture operation can only be fully represented by several copies of the corresponding combinational logic portion in the circuit, each with a different set of constraints on its inputs and outputs and each corresponding to a different timeframe, for the purpose of ATPG and fault simulation.
  • This embodiment processes the multiple circuit model copies for different timeframes in a series manner one by one.
  • this embodiment conducts circuit expansion in order to represent the corresponding circuit behavior with only one set of circuit data. The reason why this is possible is that circuit expansion uses multiple copies of a logic block to represent the different state of the block at different times.
  • circuit expansion is conducted for clock domains CDl 102 and CD2 103.
  • circuit expansion can also be conducted for cross-clock domain blocks between CDl 102 and CD2 103.
  • 00134 When scan clocks CKl 120 and CK2 121 are activated one by one, all stuck-at faults in the clock domains CDl 102 and CD2 103, as well as the cross-clock domain blocks CCD12 105 and CCD21 106, can be targeted in the same run of ATPG and fault simulation, corresponding to test stimuli shifted- in through scan chains in three clock domains, CDl 102 to CD3 104.
  • all stuck-at fault in the clock domain CD3 104 and the cross-clock domain blocks CCD13 109 and CCD23 107 can be targeted in ATPG and fault simulation, corresponding to test stimuli shifted-in through scan chains in two clock domains, CD2 103 and CD3 104, as well as test responses captured by CKl 120 and CK2 121.
  • This embodiment of the present invention can alleviate the disadvantages of both prior-art solution #3 and prior-art solution #4.
  • a sequential ATPG program needs to be used but with fewer timeframes. This will result in less CPU time and memory usage than prior-art solution #3. The memory usage will be less than that of prior-art solution #4 since circuit expansion is only conducted for part of a circuit.
  • FIG. 10A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in a fourth embodiment of the present invention.
  • the meanings of nodes, edges, and clock groups are the same as explained in FIG. 7A.
  • FIG. 10B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation
  • FIG. 10C shows the scan clock waveforms in actual test application, both for detecting or locating transition faults or path-delay faults launched from capture, with regard to clock grouping in a fourth embodiment of the present invention.
  • This embodiment is basically the same as the embodiment shown in FIG. 7. The only difference is that this embodiment uses two at-speed pulses for each capture. This allows this embodiment to detect or locate transition faults or path-delay faults launched from capture. Refer to the descriptions of FIG. 7 for more details.
  • FIG. HA shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in a fifth embodiment of the present invention.
  • the meanings of nodes, edges, and clock groups are the same as explained in FIG. 7A.
  • FIG. 11 B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation
  • FIG. 11C shows the scan clock waveforms in actual test application, both for detecting or locating transition faults or path-delay faults launched from capture, with regard to clock grouping in a fifth embodiment of the present invention.
  • This embodiment is basically the same as the embodiment shown in FIG. 8. The only difference is that this embodiment uses two at-speed pulses for each capture. This allows this embodiment to detect or locate transition faults or path-delay faults launched from capture. Refer to the descriptions of FIG. 8 for more details.
  • FIG. 12A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in a sixth embodiment of the present invention.
  • the meanings of nodes, edges, and clock groups are the same as explained in FIG. 7A.
  • FIG. 12B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation and FIG. 12C shows the scan clock waveforms in actual test application, both for detecting or locating transition faults or path-delay faults launched from capture, with regard to clock grouping in a sixth embodiment of the present invention.
  • This embodiment is basically the same as the embodiment shown in FIG. 9. The only difference is that this embodiment uses two at-speed pulses for each capture. This allows this embodiment to detect or locate transition faults or path-delay faults launched from capture. Refer to the descriptions of FIG. 9 for more details.
  • FIG. 13A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in a seventh embodiment of the present invention.
  • the meanings of nodes, edges, and clock groups are the same as explained in FIG. 7A.
  • FIG. 13B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation
  • FIG. 13C shows the scan clock waveforms in actual test application, both for detecting or locating transition faults or path-delay faults launched from shift with regard to clock grouping in a seventh embodiment of the present invention.
  • This embodiment is basically the same as the embodiment shown in FIG. 7. The only difference is that this embodiment uses one at-speed pulse for each capture. This allows this embodiment to detect or locate transition faults or path-delay faults launched from shift. Refer to the descriptions of FIG. 7 for more details.
  • FIG. 14A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in an eighth embodiment of the present invention.
  • the meanings of nodes, edges, and clock groups are the same as explained in FIG. 7A.
  • FIG. 14B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation
  • FIG. 14C shows the scan clock waveforms in actual test application, both for detecting or locating transition faults or path-delay faults launched from shift, with regard to clock grouping in an eighth embodiment of the present invention.
  • This embodiment is basically the same as the embodiment shown in FIG. 8. The only difference is that this embodiment uses one at-speed pulse for each capture. This allows this embodiment to detect or locate transition faults or path-delay faults launched from shift. Refer to the descriptions of FIG. 8 for more details.
  • FIG. 15A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in a ninth embodiment of the present invention.
  • the meanings of nodes, edges, and clock groups are the same as explained in FIG. 7A.
  • FIG. 15B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation
  • FIG. 15C shows the scan clock waveforms in actual test application, both for detecting or locating transition faults or path-delay faults launched from shift, with regard to clock grouping in a ninth embodiment of the present invention.
  • This embodiment is basically the same as the embodiment shown in FIG. 9. The only difference is that this embodiment uses one at-speed pulse for each capture. This allows this embodiment to detect or locate transition faults or path-delay faults launched from shift. Refer to the descriptions of FIG. 9 for more details.
  • FIG. 16A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in a tenth embodiment of the present invention.
  • the meanings of nodes, edges, and clock groups are the same as explained in FIG. 7A.
  • FIG. 16B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation
  • FIG. 16C shows the scan clock waveforms in actual test application, both for detecting or locating stuck-at faults, bridging faults, or IDDQ faults, with regard to clock grouping in a tenth embodiment of the present invention.
  • This embodiment requires that all scan clocks be grouped into a set of clock groups and that the scan clocks in only one clock group be activated during each capture operation. In addition, if a clock group contains multiple scan clocks, this embodiment requires that the scan clocks be activated one by one in a selected order and that the capture pulse delay between any scan clocks is larger than the possible corresponding clock skew.
  • a clock group contains only one scan clock
  • the circuit behavior when the scan clock captures can be fully represented by only one copy of the corresponding combinational logic portion in the circuit.
  • a clock group contains multiple scan clocks that are activated one by one in a selected order
  • the circuit behavior during a capture operation can only be fully represented by several copies of the corresponding combinational logic portion in the circuit, each with a different set of constraints on its inputs and outputs and each corresponding to a different timeframe, for the purpose of ATPG and fault simulation.
  • This embodiment processes the multiple circuit model copies for different timeframes in a serial manner one by one.
  • This embodiment of the present invention only needs a sequential ATPG program when test patterns are to be generated deterministically.
  • this embodiment can alleviate the disadvantage of prior-art solution #3 by reducing CPU time and memory usage.
  • FIG. 17A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in an eleventh embodiment of the present invention.
  • the meanings of nodes, edges, and clock groups are the same as explained in FIG. 7A.
  • FIG. 17B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation and FIG. 17C shows the scan clock waveforms in actual test application, both for detecting or locating stuck-at faults, bridging faults, or IDDQ faults, with regard to clock grouping in an eleventh embodiment of the present invention.
  • This embodiment requires that all scan clocks be grouped into a set of clock groups and that the scan clocks in all clock groups be activated during each capture operation. In addition, this embodiment requires that the scan clocks be activated one by one in a selected order and that the capture pulse delay between any scan clocks is larger than the possible corresponding clock skew.
  • the circuit behavior during a capture operation can only be fully represented by several copies of the corresponding combinational logic portion in the circuit, each with a different set of constraints on its inputs and outputs and each corresponding to a different timeframe, for the purpose of ATPG and fault simulation.
  • This embodiment processes the multiple circuit model copies for different timeframes in a series manner one by one for scan clocks in the clock group CGI 1707. However, for the scan clock in the clock group CG2 1708, some constraints on the inputs and outputs of the corresponding circuit copy are set to unknown (X) values.
  • This embodiment of the present invention only needs a sequential ATPG program when test patterns are to be generated deterministically.
  • this embodiment can alleviate the disadvantages of prior-art solution #2 and prior-art solution #3 by achieving higher fault coverage with lower memory usage.
  • FIG. 18A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in a twelfth embodiment of the present invention.
  • the meanings of nodes, edges, and clock groups are the same as explained in FIG. 7A.
  • FIG. 18B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation
  • FIG. 18C shows the scan clock waveforms in actual test application, both for detecting or locating transition faults or path-delay faults launched from capture, with regard to clock grouping in a twelfth embodiment of the present invention.
  • This embodiment is basically the same as the embodiment shown in FIG. 16. The only difference is that this embodiment uses two at-speed pulses for each capture. This allows this embodiment to detect or locate transition faults or path-delay faults launched from capture. Refer to the descriptions of FIG. 16 for more details.
  • FIG. 19A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in a thirteenth embodiment of the present invention.
  • the meanings of nodes, edges, and clock groups are the same as explained in FIG. 7A.
  • FIG. 19B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation
  • FIG. 19C shows the scan clock waveforms in actual test application, both for detecting or locating transition faults or path-delay faults launched from capture, with regard to clock grouping in a thirteenth embodiment of the present invention.
  • This embodiment is basically the same as the embodiment shown in FIG. 17. The only difference is that this embodiment uses two at-speed pulses for each capture. This allows this embodiment to detect or locate transition faults or path-delay faults launched from capture. Refer to the descriptions of FIG. 17 for more details.
  • FIG. 20A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in a thirteenth embodiment of the present invention.
  • the meanings of nodes, edges, and clock groups are the same as explained in FIG. 7A.
  • FIG. 20B shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation
  • FIG. 20C shows the scan clock waveforms in actual test application, both for detecting or locating transition faults or path-delay faults launched from shift, with regard to clock grouping in a thirteenth embodiment of the present invention.
  • This embodiment is basically the same as the embodiment shown in FIG. 16. The only difference is that this embodiment uses one at-speed pulse for each capture. This allows this embodiment to detect or locate transition faults or path-delay faults launched from shift. Refer to the descriptions of FIG. 16 for more details.
  • FIG. 21 A shows the domain-interconnect graph used to represent the relationship among the clock domains shown in FIG. 1, with clock grouping in a fifteenth embodiment of the present invention.
  • the meanings of nodes, edges, and clock groups are the same as explained in FIG. 7A.
  • FIG. 2 IB shows the scan clock waveforms in ATPG (automatic test pattern generation) and fault simulation
  • FIG. 21C shows the scan clock waveforms in actual test application, both for detecting or locating transition faults or path-delay faults launched from shift, with regard to clock grouping in a fifteenth embodiment of the present invention.
  • This embodiment is basically the same as the embodiment shown in FIG. 17. The only difference is that this embodiment uses one at-speed pulse for each capture. This allows this embodiment to detect or locate transition faults or path-delay faults launched from shift. Refer to the descriptions of FIG. 17 for more details.
  • FIG. 22 A shows a domain-interconnect graph used to represent the relationship among 8 inter-related clock domains, CDl 2201 to CD8 2208.
  • 8 vertexes are used to represent the 8 clock domains, CDl 2201 to CD8 2208.
  • the corresponding clocks, CKl 2221 to CK8 2228, for the clock domains are also shown in the vertexes for the purpose of easy comprehension.
  • the directed arc between any two vertexes represents a cross-clock domain logic block.
  • the arc 2232 represents the cross-clock domain logic block from the clock domain CD2 2202 to the clock domain CDl 2201.
  • FIG. 22B shows the fault detection or location range for one ordered sequence of capture clocks for the clock domains shown in FIG. 22A, in accordance with the present invention, where clock domain grouping is conducted.
  • clock domains CD7 2207 and CD8 2208 do not interact with each other, they can be captured at the same time.
  • clock domains CD3 2203 and CD5 2205 do not interact with each other, they can be captured at the same time.
  • clock domains CD3 2203 and CD6 2206 do not interact with each other, they can be captured at the same time.
  • clock domains CD5 2205 and CD6 2206 interact with each other, they cannot be captured at the same time.
  • the ordered sequence of capture clocks can be picked up as follows: ⁇ CK7 2227, CK8 2228 ⁇ -> CKl 2221 -> CK2 2222 -> ⁇ CK3 2223, CK5 2225 ⁇ -> CK6 2226 -> CK4 2224.
  • the ordered sequence of capture clocks can be picked up as follows: ⁇ CD7 2227, CD8 2228 ⁇ -> CDl 2221 -> CK2 2222 -> ⁇ CK3 2223, CK6 2224 ⁇ -> CK5 2225 -> CK4 2224. That is, some clock domains can be grouped together and captured simultaneously. This will reduce test time.
  • FIG. 23 A shows a domain-interconnect graph used to represent the relationship among 5 inter-related clock domains, CDl 2301 to CD4 2305.
  • 5 vertexes are used to represent the 5 clock domains, CDl 2301 to CD4 2305.
  • the corresponding clocks, CKl 2321 to CK5 2325, for the clock domains are also shown in the vertexes for the purpose of easy comprehension.
  • the directed arc between any two vertexes represents a cross-clock domain logic block.
  • the arc 2351 represents the cross-clock domain logic block from the clock domain CD2 2302 to the clock domain CDl 2301. 00170 FIG.
  • FIG. 23B shows the fault detection or location range for one ordered sequence of capture clocks, ⁇ CKl 2321, CK5 2325 ⁇ -> CK2 2322 -> CK3 2323 -> CK4 2324, for the clock domains, CDl 2321 to CD4 2324, shown in FIG. 23A, in accordance with the present invention.
  • the ordered sequence of capture clocks is determined automatically based on the domain- interconnect graph shown in FIG. 23A. It can also be specified directly.
  • test stimuli are shifted into the scan chains in all clock domains simultaneously.
  • the capture operation is conducted in the following manner: First, the clocks CKl 2321 and CK5 2325, which do not interact with each other, capture. As a result, faults in the clock domain CDl 2301 as well as in the cross-clock domain logic blocks 2351 and 2357 can be detected or located. In addition, faults in the clock domain CD5 2305 as well as in the cross-clock domain logic blocks 2356 and 2359 can be detected or located. Second, the clock CK2 2322 captures. As a result, faults in the clock domain CD2 2302 as well as in the cross-clock domain logic block 2352 can be detected or located. Third, the clock CK3 2323 captures.
  • FIG. 23C shows the fault detection or location range for one more ordered sequence of capture clocks, CK4 2324 -> CK3 2323, for the clock domains, CD4 2304 to CD3 2303, shown in FIG. 23A, in accordance with the present invention.
  • the ordered sequence of capture clocks is determined automatically based on the domain-interconnect graph shown in FIG. 23A. It can also be specified directly.
  • test stimuli are shifted into the scan chains in all clock domains simultaneously.
  • the capture operation is conducted in the following manner: First, the clock CK42324 captures. As a result, faults in the clock domain CD4 2304 as well as in the cross-clock domain logic block 2355 can be detected or located. Second, the clock CK3 2323 captures. As a result, faults in the clock domain CD3 2303 as well as in the cross-clock domain logic block 2353 can be detected or located.
  • FIG. 23D shows the fault detection or location range for one ordered sequence of capture clocks, ⁇ CKl 2321, CK5 2325 ⁇ -> CK2 2322 -> CK3 2323 -> CK4 2324, for the clock domains, CDl 2301 to CD4 2304, shown in FIG. 23A, in accordance with the present invention, where clock domain merging is conducted.
  • the controllability of the cross-clock domain logic block 2355 is still high since the clock domains CD2 2302 and CD3 2303 as well as the cross-clock domain logic block 2353 are also transformed to obtain the values in the clock domains CD2 2302 and CD3 2303 as well as the cross-clock domain logic block 2353 after the clocks CK2 2322 and CK3 2323 capture. As a result, all faults in the cross-clock domain logic block 2355 can be detected or located. That is, by merging the 3 clock domains, CD2 2302, CD3 2303, and CD4 2304, only one ordered sequence of capture clocks is enough to detect or locate all faults in the scan-based integrated circuit.
  • FIG. 24A shows a prior art solution for handling uncontroUability when using a single time-frame in the multiple-capture scheme.
  • the clock domain CDl 2401 interacts to the clock domain CD2 2402 through the cross- clock domain logic block CCD12 2403.
  • the Q output 2409 of the scan cell SCI 2404, driven by the clock CKl 2406, is connected to the cross-clock domain logic block CCD12 2403.
  • the D input 2410 of the D input of the scan cell SC2 2405, driven by the clock CK2 2407, is connected to the cross-clock domain logic block CCD12 2403.
  • the clock CK 1 2406 is activated before the clock CK2 2407 is activated in the multiple-capture scheme.
  • the clock domain CDl 2401 needs to be transformed during ATPG (automatic test pattern generation) for detecting or locating all faults in the clock domain CDl 2401. Note that, after the clock CKl 2406 is activated, test responses will be captured into all scan cells in the clock domain CDl 2401, replacing any previous values shifted into these scan cells.
  • the clock domain CDl 2401, the cross-clock domain CCD12 2403, and the clock domain CD2 2402 need to be transformed during ATPG for detecting or locating all faults in the cross-clock domain logic block CCD12 303 and the clock domain CD2 2402.
  • two time- frames are involved: the first one for CKl 2406 and the second one for CK2 2407.
  • the purpose of transforming the clock domain CDl 2401 is to get the values for the first time-frame for CKl 2406.
  • 00181 A prior art solution for handling this uncontroUability issue is to use unknown values, represented by X. As shown in FIG. 24A, X is assigned to the Q output 2409 of the scan cell SCI 2404. The disadvantage of this solution is that it reduces the controllability significantly, which will results in a larger set of test patterns with lower fault coverage.
  • FIG. 24B shows an embodiment of the method for handling uncontroUability when using a single time-frame in the multiple-capture scheme, in accordance with the present invention.
  • the present invention makes sure that the value of the Q output 2409 of the scan cell SCI 2404 remains the same before and after the clock CKl 2406 captures. This can be achieved by setting a proper value either to the D input 2408 or the R (reset) input 2411 of the scan cell SCI 2404. Since a logic value, 0 or 1, is used instead of an unknown value X, the controllability for the cross-clock domain CCD12 2403 and the clock domain CD2 2402 can be improved significantly. This will result in a smaller set of test patterns with higher fault coverage.
  • FIG. 25 shows an electronic design automation system which includes a processor 2502, a bus 2505 coupled to the processor, a computer- readable memory 2501 coupled to the bus, an input device 2503, and an output device 2504.
  • the computer-readable memory 2501 contains a computer- readable program, in accordance with the present invention and described in FIG. 6A and FIG. 6B, to cause the electronic design automation system to perform a method of ATPG (automatic test pattern generation) and fault simulation based on clock grouping and circuit expansion for testing a scan- based integrated in scan-test mode or self-test mode.
  • ATPG automated test pattern generation
  • the processor 2502 may represent a central processing unit of a personal computer, workstation, mainframe computer or other suitable digital processing device.
  • the memory 2501 can be an electronic memory or a magnetic or optical disk-based memory, or various combinations thereof.
  • a designer interacts with the clock grouping and circuit expansion based ATPG and fault simulation software run by the processor 2502 to provide appropriate inputs via an input device 2503, which may be a keyboard, disk drive or other suitable source of design information.
  • the processor 2502 provides outputs to the designer via an output device 2504, which may be a display, a printer, a disk drive or various combinations of these and other elements.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

L'invention concerne un procédé pour produire des stimuli et des réponses au test permettant de tester les défaillances dans un circuit intégré à balayage dans un mode de test à balayage ou un mode de test automatique, ledit circuit intégré à balayage contenant une pluralité de chaînes de balayage, de domaines à n horloges, et des blocs entre des domaines d'horloges, chaque chaîne à balayage comprenant de nombreuses cellules de balayage couplées en série, chaque domaine d'horloge présentant une horloge de capture, chaque bloc entre des domaines d'horloge comprenant un réseau de logique combinatoire. Ledit procédé comprend les étapes suivantes : compilation d'un circuit intégré à balayage en un modèle de circuit séquentiel ; spécification des contraintes d'entrées sur le circuit intégré à balayage lors d'une opération de décalage et de capture ; spécification d'un groupe d'horloge pour faire correspondre les domaines à n horloges à un groupes de domaines d'horloges G, N>G>1 ; transformation du modèle de circuit séquentiel en un modèle de circuit combinatoire équivalent selon les contraintes d'entrée et le groupe d'horloges ; et production des stimuli et des réponses au test sur le modèle du circuit combinatoire équivalent selon les contraintes d'entrée.
PCT/US2004/014525 2003-05-23 2004-05-24 Capture smart pour une production de modele de test automatique (atpg) et simulation de defaillances de circuits integres a balayage Ceased WO2004107402A2 (fr)

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US47278603P 2003-05-23 2003-05-23
US60/472,786 2003-05-23
US10/850,460 US7124342B2 (en) 2004-05-21 2004-05-21 Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuits
US10/850,460 2004-05-21

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9552449B1 (en) 2016-01-13 2017-01-24 International Business Machines Corporation Dynamic fault model generation for diagnostics simulation and pattern generation
US10372853B2 (en) 2017-03-20 2019-08-06 International Business Machines Corporation Implementing enhanced diagnostics with intelligent pattern combination in automatic test pattern generation (ATPG)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5949692A (en) * 1996-08-28 1999-09-07 Synopsys, Inc. Hierarchical scan architecture for design for test applications
US6195776B1 (en) * 1998-11-02 2001-02-27 Synopsys, Inc. Method and system for transforming scan-based sequential circuits with multiple skewed capture events into combinational circuits for more efficient automatic test pattern generation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9552449B1 (en) 2016-01-13 2017-01-24 International Business Machines Corporation Dynamic fault model generation for diagnostics simulation and pattern generation
US10372853B2 (en) 2017-03-20 2019-08-06 International Business Machines Corporation Implementing enhanced diagnostics with intelligent pattern combination in automatic test pattern generation (ATPG)

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