WO2006058850A1 - Metallisierte folie zur flächigen kontaktierung - Google Patents
Metallisierte folie zur flächigen kontaktierung Download PDFInfo
- Publication number
- WO2006058850A1 WO2006058850A1 PCT/EP2005/056094 EP2005056094W WO2006058850A1 WO 2006058850 A1 WO2006058850 A1 WO 2006058850A1 EP 2005056094 W EP2005056094 W EP 2005056094W WO 2006058850 A1 WO2006058850 A1 WO 2006058850A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- insulating film
- substrate
- metallization
- contact surface
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
- H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W40/00—Arrangements for thermal protection or thermal control
- H10W40/10—Arrangements for heating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W42/00—Arrangements for protection of devices
- H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W42/261—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons characterised by their shapes or dispositions
- H10W42/276—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons characterised by their shapes or dispositions the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/688—Flexible insulating substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
- H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
Definitions
- the invention relates to a method for contacting one or more electrical contact surfaces on a surface of a substrate and / or at least one component, comprising the step of laminating at least one insulating film of electrically insulating plastic material on the surfaces of the substrate and the component under vacuum, so that the insulating film the surface is tightly covered with the contact surface or surfaces and adheres to this surface.
- WO03 / 030247 discloses a method of contacting, comprising the further steps of exposing each contact surface to be contacted on the surface by opening respective windows in the film, and contacting each exposed contact surface with a layer of electrically conductive material. According to this method, at least one printed conductor is produced after the surface contacting in and / or on the layer of the electrically conductive material. To produce a multilayer device, the steps of laminating, exposing, contacting and producing the printed conductor are carried out several times.
- a disadvantage of the conventional contacting method is the effort to be made for contacting, in particular of components on a surface of a substrate. A large number of process steps are required.
- Allow components on a substrate surface The object is achieved by a method according to the main claim and a device according to the independent claim. Advantageous embodiments can be found in the subclaims.
- the present method is used to contact only a substrate structure or at least one component on a substrate or at least one component with a substrate together.
- At least one metallization formed on at least one surface side of the insulating film. This serves to provide interconnects or trace or
- connection structures can already be formed by means of conventional methods prior to lamination.
- the films can be produced with one-sided metallization or with two-sided metallization on an insulating film.
- a metallized insulating film is particularly suitable over the entire surface, part of the surface or pre-structured with conductor tracks copper coating a plastic film.
- Other metals in particular comparable in electrical resistivity or in processability, may also be used.
- Windows can be easily generated mechanically, eg, by punching, chemically, eg by etching, or physically, by lasing, plasma opening, before or after the respective laminating step.
- the contacting may be performed by inserting the metallization toward the electrical contact surface or by leading the electrical contact surface out to the metallization.
- the contacting takes place at an advantageous pressure and at an advantageous temperature. Surface contact is preferred.
- Suitable components are electronic components, LEDs, semiconductor chips or power semiconductor chips. A multiplicity of process steps of conventional contacting methods can be dispensed with.
- Suitable substrates are any circuit carriers based on organic or inorganic substances.
- Such substrates include PCB (Printed Circuit Board), DCB, IM (Insulated Metal), HTCC (High Temperature Cofired Ceramics) and LTCC (Low Temperature Cofired Ceramics) substrates.
- the lamination is advantageously carried out in a vacuum press. Vacuum thermoforming, hydraulic vacuum pressing, vacuum gas pressure pressing or similar laminating methods are conceivable for this purpose.
- the pressure is advantageously applied isostatically.
- the lamination takes place for example at temperatures of 100 0 C to 25O 0 C and a pressure of 1 bar to 10 bar.
- the exact process parameters of the lamination, ie pressure, temperature, time, etc., depend inter alia on the topology of the substrate, the plastic material of the insulating film and the thickness of the insulating film.
- a physical or chemical deposition of the electrically conductive material is advantageously carried out.
- Such physical methods are sputtering and vapor deposition (Physical Vapor Deposition, PVD).
- the chemical deposition can be carried out from the gaseous phase (chemical vapor deposition, CVD) and / or liquid phase (liquid phase chemical vapor deposition). It is also conceivable that initially by one of these methods, a thin electrically conductive sub-layer is applied, on which then a thicker electrically conductive sub-layer is electrodeposited.
- a substrate having a surface which is equipped with one or more semiconductor chips, in particular power semiconductor chips, on each of which one or more contact surfaces to be contacted is or are present, and wherein the at least one insulating film
- This surface is vacuum-laminated so that the insulating film closely covers and adheres to this surface including each semiconductor chip and each pad, including each semiconductor chip.
- the insulating film is designed, for example, so that in particular a height difference of up to about 5 mm can be overcome.
- the height difference is caused inter alia by the topology of the substrate and by the semiconductor chips arranged on the substrate.
- SMD surface mounted device components can be applied, for example soldered on.
- the insulating film may consist of any thermoplastics, thermosets and mixtures thereof.
- a film of a plastic material on polyimide (PI), polyethylene (PE), polyphenol, is advantageously used as film.
- the film may have an adhesive coating to improve the adhesion on the surface.
- This additional insulating film has no opening, but preferably in the region of the opening on the metallization.
- a substrate with a surface equipped with one or more power semiconductor chips is used.
- Metallizations on different surface sides electrically connected to each other. This can be done via pins.
- Insulating films made of a plastic material on polyimide, polyethylene, polyphenol, Polyetheretherketon- and / or epoxy-based and used as one-sided or two-sided metallizations copper, aluminum, iron and / or silver or similar electrical conductors.
- Plastic film can thus be coated on one side of the surface or on both surfaces with metal.
- pure metal layers can also be used.
- connection structure corresponds to the required connection of electrical or electronic components that can be applied to a substrate by conventional methods.
- the metal structure can be produced, for example, via a photolithographic process. Conventional structuring methods are equally applicable.
- the metallization of the insulating film can be structured by laser ablation, stamping, etching or by a photolithographic process.
- each exposed contact surface can be carried out by means of thermal pressing, soldering and / or gluing the metalized insulating foil having the metallization.
- additional metallized connecting foils having at least one metallization may be used.
- the connecting foils can be fixed by soldering or gluing.
- the Antitle ist each exposed contact surface by means of soldering and / or gluing the metallized insulating film, that is, the metallization having insulating performed.
- the contacting takes place areally.
- the contacting can take place from the metallized insulating film into the exposed contact surface.
- the execution of the exposed contact surface outwards to the metal interconnects is also feasible with appropriate provision of the contact surfaces.
- the lamination of the Isolier Anlagen von Heidelberg Kunststoffmaschine is repeated such that a multilayer structure is generated. Likewise, insulating layer thicknesses can thereby be increased.
- a metallized insulating film with a thickness (d), for example, in particular in the range of 25 to 250 microns is used.
- an insulating covering on the side of the uppermost insulating film facing away from the substrate, and a metal layer applied to this insulating cover to produce a hermetic seal and direct contact of the metal layer by means of a direct metal connection to an edge region of the substrate.
- the metal layer serves as a mechanical protection, as a cover, with heat-dissipating properties. Between metal layer and the one Metallized insulating foil, the insulating cover serves as electrical insulation.
- FIG. 1 shows an illustration of a first exemplary embodiment of a device or the method according to the invention
- FIG. 2 shows an illustration of a second exemplary embodiment of the device according to the invention or of the method
- FIG. 3 shows an illustration of a third embodiment of the device according to the invention
- Fig. 4 is a highly simplified plan view of the third embodiment of the device according to the invention Shen.
- FIG. 1 shows the construction of a device according to an embodiment with at least one electrical contact surface 1 on a surface of a substrate 2 and / or at least one arranged on the substrate
- Component 3 On the surfaces of the substrate 1 and the component 3 is at least one electrically insulating Insulating film 4, which bears tightly against the underlying surface and adheres, laminated by vacuum. At least one metallization 5 is applied to at least one surface side of the at least one insulating film 4.
- the insulating film 4 has at least one window 6 in the contact surface 1, in which the contact surface 1 is in contact with the metallization 5 in a planar manner.
- an insulating cover 7 is applied to the insulating film 4, and a metal layer 8 is applied to the insulating cover 7, wherein a direct contact of the
- Metal layer is produced by means of a direct metal connection to an edge region of the substrate for producing a hermetic seal of the device.
- a cooling body 9 is arranged above the hermetic seal and below the substrate.
- each exposed contact surface 1 by means of soldering and / or gluing the metallized insulating film 4a is performed. Comparable connection methods are also applicable.
- the contacting takes place areally.
- the contacting can take place from the metallized insulating film 4a into the exposed contact surface.
- the execution of metallized connecting foils 4b (provided separately or as a continuation of the contact surface 1) from the exposed contact surface 1 to the outside to the metal interconnects 5 is also feasible with appropriate provision of the contact surfaces 1.
- Fig. 3 shows how a metallized insulating film 4a exposed over the outer edges of the substrate 2 and structured for connection to external terminals can be used. This can also compensate for differences in height. This type of flexible AnAuthierung replaces or complements additional connector connections or comparable connection solutions.
- the film and copper thicknesses can be variably adapted to the respective mechanical, electrical, thermal and comparable requirements.
- the metallized insulating film 4 a is produced over an insulating film 4 on the left side of the substrate 2 beyond the substrate 2 over a support 10 with non-adhesive properties, for example a Teflon structure 10.
- the Teflon layer 10 can be removed or separated from the insulating films 4 and 4a in such a way that they are exposed or exposed to the substrate 2.
- Fig. 4 shows a highly simplified view of FIG. 3 from above.
- the exposed insulating films 4 and 4a are clearly visible. These each extend beyond the surface of the substrate 2.
- a hermetic cover of the device by means of a metal layer 8 over an insulating cover 7 may additionally be produced.
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
Abstract
Description
Claims
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/791,608 US7910470B2 (en) | 2004-11-29 | 2005-11-21 | Metallised film for sheet contacting |
| EP05815728A EP1817795A1 (de) | 2004-11-29 | 2005-11-21 | Metallisierte folie zur flächigen kontaktierung |
| JP2007541966A JP2008522394A (ja) | 2004-11-29 | 2005-11-21 | 面状接触形成のためのメタライズされた箔 |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102004057494A DE102004057494A1 (de) | 2004-11-29 | 2004-11-29 | Metallisierte Folie zur flächigen Kontaktierung |
| DE102004057494.4 | 2004-11-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2006058850A1 true WO2006058850A1 (de) | 2006-06-08 |
Family
ID=35735117
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/EP2005/056094 Ceased WO2006058850A1 (de) | 2004-11-29 | 2005-11-21 | Metallisierte folie zur flächigen kontaktierung |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US7910470B2 (de) |
| EP (1) | EP1817795A1 (de) |
| JP (1) | JP2008522394A (de) |
| CN (1) | CN100472783C (de) |
| DE (1) | DE102004057494A1 (de) |
| WO (1) | WO2006058850A1 (de) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102007043001A1 (de) * | 2007-09-10 | 2009-03-12 | Siemens Ag | Bandverfahren für elektronische Bauelemente, Module und LED-Anwendungen |
| DE102007057346B3 (de) * | 2007-11-28 | 2009-06-10 | Fachhochschule Kiel | Laminierte Leistungselektronikbaugruppe |
| DE102008003788A1 (de) * | 2008-01-10 | 2009-07-16 | Robert Bosch Gmbh | Elektrische Schaltungsanordnung mit mindestens einem Leistungshalbleiter und Verfahren zu deren Herstellung |
| US8410600B2 (en) * | 2009-10-02 | 2013-04-02 | Arkansas Power Electronics International, Inc. | Semiconductor device with protecting film and method of fabricating the semiconductor device with protecting film |
| US20110126880A1 (en) * | 2009-11-30 | 2011-06-02 | Du Pont Apollo Limited | Thin-Film Photovoltaic Panel and Method of Producing the Same |
| DE102010012457B4 (de) * | 2010-03-24 | 2015-07-30 | Semikron Elektronik Gmbh & Co. Kg | Schaltungsanordnung mit einer elektrischen Komponente und einer Verbundfolie |
| DE102011083423A1 (de) * | 2011-09-26 | 2013-03-28 | Siemens Aktiengesellschaft | Kontaktfederanordnung und Verfahren zur Herstellung derselben |
| US8716870B2 (en) * | 2011-12-16 | 2014-05-06 | General Electric Company | Direct write interconnections and method of manufacturing thereof |
| US20130264721A1 (en) | 2012-04-05 | 2013-10-10 | Infineon Technologies Ag | Electronic Module |
| DE102012218561A1 (de) * | 2012-10-11 | 2014-04-17 | Siemens Aktiengesellschaft | Elektronikmodul, Mehrfachmodul und Verfahren zum Herstellen eines Elektronikmoduls |
| WO2016080333A1 (ja) * | 2014-11-21 | 2016-05-26 | 株式会社村田製作所 | モジュール |
| DE102017210894A1 (de) * | 2017-06-28 | 2019-01-03 | Robert Bosch Gmbh | Elektronikmodul und Verfahren zur Herstellung eines Elektronikmoduls |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0588603A2 (de) * | 1992-09-18 | 1994-03-23 | General Electric Company | Dicht versiegeltes Gehäuse für elektronische Systeme und Verfahren zu seiner Herstellung |
| US5359496A (en) * | 1989-12-21 | 1994-10-25 | General Electric Company | Hermetic high density interconnected electronic system |
| DE19617055C1 (de) * | 1996-04-29 | 1997-06-26 | Semikron Elektronik Gmbh | Halbleiterleistungsmodul hoher Packungsdichte in Mehrschichtbauweise |
| US6294741B1 (en) * | 1995-07-10 | 2001-09-25 | Lockheed Martin Corporation | Electronics module having high density interconnect structures incorporating an improved dielectric lamination adhesive |
| DE10121970A1 (de) * | 2001-05-05 | 2002-11-28 | Semikron Elektronik Gmbh | Leistungshalbleitermodul in Druckkontaktierung |
| WO2003012856A2 (de) * | 2001-07-27 | 2003-02-13 | Epcos Ag | Verfahren zur hermetischen verkapselung eines bauelementes |
| WO2004086502A1 (de) * | 2003-03-28 | 2004-10-07 | Siemens Aktiengesellschaft | Anordnung aus einem elektrischen bauelement auf einem substrat und verfahren zum herstellen der anordnung |
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| NL159818B (nl) * | 1972-04-06 | 1979-03-15 | Philips Nv | Halfgeleiderinrichting, bevattende een flexibele isolerende folie, die aan een zijde is voorzien van metalen geleider- sporen. |
| US4918811A (en) * | 1986-09-26 | 1990-04-24 | General Electric Company | Multichip integrated circuit packaging method |
| DE4219410A1 (de) * | 1992-06-13 | 1993-12-16 | Hoechst Ag | Heißsiegelfähige, antistatisch beschichtete Folien und Folienlaminate, Verfahren zu deren Herstellung und deren Verwendung |
| US5492586A (en) * | 1993-10-29 | 1996-02-20 | Martin Marietta Corporation | Method for fabricating encased molded multi-chip module substrate |
| US6239980B1 (en) * | 1998-08-31 | 2001-05-29 | General Electric Company | Multimodule interconnect structure and process |
| US6710456B1 (en) * | 2000-08-31 | 2004-03-23 | Micron Technology, Inc. | Composite interposer for BGA packages |
| TW550672B (en) * | 2001-02-21 | 2003-09-01 | Semiconductor Energy Lab | Method and apparatus for film deposition |
| US6788724B2 (en) * | 2001-07-06 | 2004-09-07 | Intel Corporation | Hermetically sealed external cavity laser system and method |
| EP1430524A2 (de) * | 2001-09-28 | 2004-06-23 | Siemens Aktiengesellschaft | Verfahren zum kontaktieren elektrischer kontaktflächen eines substrats und vorrichtung aus einem substrat mit elektrischen kontaktflächen |
| DE10164502B4 (de) * | 2001-12-28 | 2013-07-04 | Epcos Ag | Verfahren zur hermetischen Verkapselung eines Bauelements |
| CN100468670C (zh) * | 2003-02-28 | 2009-03-11 | 西门子公司 | 带有大面积接线的功率半导体器件的连接技术 |
| DE10308928B4 (de) * | 2003-02-28 | 2009-06-18 | Siemens Ag | Verfahren zum Herstellen freitragender Kontaktierungsstrukturen eines ungehäusten Bauelements |
| CN100499053C (zh) * | 2003-02-28 | 2009-06-10 | 西门子公司 | 用于具有遵循表面轮廓的电绝缘材料层的功率半导体的布线工艺 |
| JP4471735B2 (ja) * | 2004-05-31 | 2010-06-02 | 三洋電機株式会社 | 回路装置 |
| DE102006009723A1 (de) * | 2006-03-02 | 2007-09-06 | Siemens Ag | Verfahren zum Herstellen und planaren Kontaktieren einer elektronischen Vorrichtung und entsprechend hergestellte Vorrichtung |
-
2004
- 2004-11-29 DE DE102004057494A patent/DE102004057494A1/de not_active Ceased
-
2005
- 2005-11-21 CN CNB2005800393086A patent/CN100472783C/zh not_active Expired - Fee Related
- 2005-11-21 WO PCT/EP2005/056094 patent/WO2006058850A1/de not_active Ceased
- 2005-11-21 JP JP2007541966A patent/JP2008522394A/ja active Pending
- 2005-11-21 EP EP05815728A patent/EP1817795A1/de not_active Withdrawn
- 2005-11-21 US US11/791,608 patent/US7910470B2/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5359496A (en) * | 1989-12-21 | 1994-10-25 | General Electric Company | Hermetic high density interconnected electronic system |
| EP0588603A2 (de) * | 1992-09-18 | 1994-03-23 | General Electric Company | Dicht versiegeltes Gehäuse für elektronische Systeme und Verfahren zu seiner Herstellung |
| US6294741B1 (en) * | 1995-07-10 | 2001-09-25 | Lockheed Martin Corporation | Electronics module having high density interconnect structures incorporating an improved dielectric lamination adhesive |
| DE19617055C1 (de) * | 1996-04-29 | 1997-06-26 | Semikron Elektronik Gmbh | Halbleiterleistungsmodul hoher Packungsdichte in Mehrschichtbauweise |
| DE10121970A1 (de) * | 2001-05-05 | 2002-11-28 | Semikron Elektronik Gmbh | Leistungshalbleitermodul in Druckkontaktierung |
| WO2003012856A2 (de) * | 2001-07-27 | 2003-02-13 | Epcos Ag | Verfahren zur hermetischen verkapselung eines bauelementes |
| WO2004086502A1 (de) * | 2003-03-28 | 2004-10-07 | Siemens Aktiengesellschaft | Anordnung aus einem elektrischen bauelement auf einem substrat und verfahren zum herstellen der anordnung |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100472783C (zh) | 2009-03-25 |
| US20080093727A1 (en) | 2008-04-24 |
| EP1817795A1 (de) | 2007-08-15 |
| JP2008522394A (ja) | 2008-06-26 |
| CN101061582A (zh) | 2007-10-24 |
| US7910470B2 (en) | 2011-03-22 |
| DE102004057494A1 (de) | 2006-06-08 |
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