WO2006087497A3 - Procede et dispositif de synchronisation trame - Google Patents

Procede et dispositif de synchronisation trame Download PDF

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Publication number
WO2006087497A3
WO2006087497A3 PCT/FR2006/050145 FR2006050145W WO2006087497A3 WO 2006087497 A3 WO2006087497 A3 WO 2006087497A3 FR 2006050145 W FR2006050145 W FR 2006050145W WO 2006087497 A3 WO2006087497 A3 WO 2006087497A3
Authority
WO
WIPO (PCT)
Prior art keywords
frame
window
syndrome
synchronisation method
frame received
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/FR2006/050145
Other languages
English (en)
Other versions
WO2006087497A2 (fr
Inventor
Sebastien Houcke
Guillaume Sicot
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Orange SA
IMT Atlantique Bretagne Pays de la Loire
Original Assignee
France Telecom SA
Ecole Nationale Superieure des Telecommunications de Bretagne
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by France Telecom SA, Ecole Nationale Superieure des Telecommunications de Bretagne filed Critical France Telecom SA
Priority to US11/884,562 priority Critical patent/US7995692B2/en
Priority to EP06709524A priority patent/EP1897264A2/fr
Priority to JP2007555674A priority patent/JP5214977B2/ja
Publication of WO2006087497A2 publication Critical patent/WO2006087497A2/fr
Publication of WO2006087497A3 publication Critical patent/WO2006087497A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/048—Speed or phase control by synchronisation signals using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

La présente invention se rapporte à un procédé et à un dispositif de synchronisation trame. Le procédé consiste à déterminer la position D de début de trame. Cette position D est égale à une position d'une fenêtre H glissante le long de la trame reçue Tr. Pour différentes positions possibles de la fenêtre H et pour différents blocs Bi de la fenêtre H, le procédé calcule un syndrome S(i)d, la position D de début de la trame reçue Tr est celle pour laquelle le nombre d'éléments nuls d'un syndrome S(i)d est le plus grand.
PCT/FR2006/050145 2005-02-18 2006-02-20 Procede et dispositif de synchronisation trame Ceased WO2006087497A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US11/884,562 US7995692B2 (en) 2005-02-18 2006-02-20 Frame-synchronization method and device
EP06709524A EP1897264A2 (fr) 2005-02-18 2006-02-20 Procede et dispositif de synchronisation trame
JP2007555674A JP5214977B2 (ja) 2005-02-18 2006-02-20 フレーム同期化方法及び装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0501748A FR2882480B1 (fr) 2005-02-18 2005-02-18 Procede et dispositif de synchronisation trame
FR0501748 2005-02-18

Publications (2)

Publication Number Publication Date
WO2006087497A2 WO2006087497A2 (fr) 2006-08-24
WO2006087497A3 true WO2006087497A3 (fr) 2006-12-28

Family

ID=34954531

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2006/050145 Ceased WO2006087497A2 (fr) 2005-02-18 2006-02-20 Procede et dispositif de synchronisation trame

Country Status (5)

Country Link
US (1) US7995692B2 (fr)
EP (1) EP1897264A2 (fr)
JP (1) JP5214977B2 (fr)
FR (1) FR2882480B1 (fr)
WO (1) WO2006087497A2 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69122265T2 (de) 1990-12-11 1997-03-13 Johnston David A Signalgeber
WO2009062357A1 (fr) * 2007-11-13 2009-05-22 Huawei Technologies Co., Ltd. Système et procédé de synchronisation de données dans des réseaux optiques passifs
US8365050B2 (en) * 2009-11-09 2013-01-29 Research In Motion Limited System and method for decoding a message using a priori information
WO2018122134A1 (fr) 2016-12-29 2018-07-05 Borealis Ag Catalyseurs
CN118677568B (zh) * 2020-04-10 2025-05-02 华为技术有限公司 码字同步方法、接收器、网络设备及网络系统
CN115250162A (zh) 2021-04-26 2022-10-28 华为技术有限公司 码字同步方法、接收器、网络设备及网络系统

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4404676A (en) * 1981-03-30 1983-09-13 Pioneer Electric Corporation Partitioning method and apparatus using data-dependent boundary-marking code words
EP0230066A1 (fr) * 1985-12-13 1987-07-29 Philips Electronique Grand Public Procédé de décodage de données transmises le long d'un canal de données et appareil pour la mise en oeuvre de la méthode
US5852639A (en) * 1994-10-28 1998-12-22 Murata Kikai Kabushiki Kaisha Resynchronization apparatus for error correction code decoder

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0738626B2 (ja) * 1993-03-01 1995-04-26 日本電気株式会社 ワード同期検出回路
JP2600581B2 (ja) * 1993-08-26 1997-04-16 日本電気株式会社 符号同期回路
KR970004256B1 (ko) * 1994-06-29 1997-03-26 한국전기통신공사 순환코드를 이용한 프레임/버스트 동기 및 에러 검출장치
JP2817638B2 (ja) * 1994-12-06 1998-10-30 村田機械株式会社 誤り訂正符号復号器の再同期化装置
JP2001308810A (ja) * 2000-04-27 2001-11-02 Nec Corp マルチキャリアフレーム同期回路
US7725800B2 (en) * 2005-08-05 2010-05-25 Hitachi Global Stroage Technologies Netherlands, B.V. Decoding techniques for correcting errors using soft information

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4404676A (en) * 1981-03-30 1983-09-13 Pioneer Electric Corporation Partitioning method and apparatus using data-dependent boundary-marking code words
EP0230066A1 (fr) * 1985-12-13 1987-07-29 Philips Electronique Grand Public Procédé de décodage de données transmises le long d'un canal de données et appareil pour la mise en oeuvre de la méthode
US5852639A (en) * 1994-10-28 1998-12-22 Murata Kikai Kabushiki Kaisha Resynchronization apparatus for error correction code decoder

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SODHA J ET AL: "SOFT-DECISION SYNDROME BASED NODE SYNCHRONISATION", ELECTRONICS LETTERS, IEE STEVENAGE, GB, vol. 26, no. 15, 19 July 1990 (1990-07-19), pages 1108 - 1109, XP000107168, ISSN: 0013-5194 *

Also Published As

Publication number Publication date
FR2882480A1 (fr) 2006-08-25
EP1897264A2 (fr) 2008-03-12
JP2008530933A (ja) 2008-08-07
JP5214977B2 (ja) 2013-06-19
WO2006087497A2 (fr) 2006-08-24
US20090154623A1 (en) 2009-06-18
FR2882480B1 (fr) 2007-07-13
US7995692B2 (en) 2011-08-09

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