WO2006107651A1 - Memoire a etats multiples possedant une recuperation de donnees apres un echec de programme - Google Patents

Memoire a etats multiples possedant une recuperation de donnees apres un echec de programme Download PDF

Info

Publication number
WO2006107651A1
WO2006107651A1 PCT/US2006/011232 US2006011232W WO2006107651A1 WO 2006107651 A1 WO2006107651 A1 WO 2006107651A1 US 2006011232 W US2006011232 W US 2006011232W WO 2006107651 A1 WO2006107651 A1 WO 2006107651A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
page
memory
memory cells
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2006/011232
Other languages
English (en)
Inventor
Yan Li
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SanDisk Corp
Original Assignee
SanDisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/097,517 external-priority patent/US7158421B2/en
Priority claimed from US11/304,783 external-priority patent/US7345928B2/en
Priority claimed from US11/304,960 external-priority patent/US7420847B2/en
Application filed by SanDisk Corp filed Critical SanDisk Corp
Publication of WO2006107651A1 publication Critical patent/WO2006107651A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5621—Multilevel programming verification

Definitions

  • This invention relates generally to non-volatile semiconductor memory such as electrically erasable programmable read-only memory (EEPROM) and flash EEPROM, and specifically to methods of implementing quick pass write or other multi-phase programming techniques.
  • EEPROM electrically erasable programmable read-only memory
  • flash EEPROM flash EEPROM
  • Solid-state memory capable of nonvolatile storage of charge, particularly in the form of EEPROM and flash EEPROM packaged as a small form factor card, has recently become the storage of choice in a variety of mobile and handheld devices, notably information appliances and consumer electronics products.
  • RAM random access memory
  • flash memory is non-volatile, retaining its stored data even after power is turned off.
  • flash memory is increasingly being used in mass storage applications.
  • Conventional mass storage, based on rotating magnetic medium such as hard drives and floppy disks, is unsuitable for the mobile and handheld environment. This is because disk drives tend to be bulky, are prone to mechanical failure and have high latency and high power requirements.
  • flash memory both embedded and in the form of a removable card is ideally suited in the mobile and handheld environment because of its small size, low power consumption, high speed and high reliability features.
  • EEPROM and electrically programmable read-only memory are non- volatile memory that can be erased and have new data written or "programmed" into their memory cells. Both utilize a floating (unconnected) conductive gate, in a field effect transistor structure, positioned over a channel region in a semiconductor substrate, between source and drain regions. A control gate is then provided over the floating gate. The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, for a given level of charge on the floating gate, there is a corresponding voltage (threshold) that must be applied to the control gate before the transistor is turned “on” to permit conduction between its source and drain regions.
  • the floating gate can hold a range of charges and therefore can be programmed to any threshold voltage level within a threshold voltage window.
  • the size of the threshold voltage window is delimited by the minimum and maximum threshold levels of the device, which in turn correspond to the range of the charges that can be programmed onto the floating gate.
  • the threshold window generally depends on the memory device's characteristics, operating conditions and history. Each distinct, resolvable threshold voltage level range within the window may, in principle, be used to designate a definite memory state of the cell.
  • the transistor serving as a memory cell is typically programmed to a "programmed" state by one of two mechanisms.
  • hot electron injection a high voltage applied to the drain accelerates electrons across the substrate channel region.
  • control gate pulls the hot electrons through a thin gate dielectric onto the floating gate.
  • tunnel injection a high voltage is applied to the control gate relative to the substrate. In this way, electrons are pulled from the substrate to the intervening floating gate.
  • the memory device may be erased by a number of mechanisms.
  • EPROM the memory is bulk erasable by removing the charge from the floating gate by ultraviolet radiation.
  • EEPROM a memory cell is electrically erasable, by applying a high voltage to the substrate relative to the control gate so as to induce electrons in the floating gate to tunnel through a thin oxide to the substrate channel region (i.e., Fowler-Nordheim tunneling.)
  • the EEPROM is erasable byte by byte.
  • flash EEPROM the memory is electrically erasable either all at once or one or more blocks at a time, where a block may consist of 512 bytes or more of memory.
  • the memory devices typically comprise one or more memory chips that may be mounted on a card.
  • Each memory chip comprises an array of memory cells supported by peripheral circuits such as decoders and erase, write and read circuits.
  • peripheral circuits such as decoders and erase, write and read circuits.
  • the more sophisticated memory devices also come with a controller that performs intelligent and higher level memory operations and interfacing.
  • non-volatile solid-state memory devices may employ different types of memory cells, each type having one or more charge storage element.
  • FIGs. 1A-1E illustrate schematically different examples of non-volatile memory cells.
  • FIG. IA illustrates schematically a non-volatile memory in the form of an EEPROM cell with a floating gate for storing charge.
  • An electrically erasable and programmable read-only memory (EEPROM) has a similar structure to EPROM, but additionally provides a mechanism for loading and removing charge electrically from its floating gate upon application of proper voltages without the need for exposure to UV radiation. Examples of such cells and methods of manufacturing them are given in United States patent no. 5,595,924.
  • FIG. IB illustrates schematically a flash EEPROM cell having both a select gate and a control or steering gate.
  • the memory cell 10 has a "split-channel" 12 between source 14 and drain 16 diffusions.
  • a cell is formed effectively with two transistors Tl and T2 in series.
  • Tl serves as a memory transistor having a floating gate 20 and a control gate 30.
  • the floating gate is capable of storing a selectable amount of charge. The amount of current that can flow through the Tl's portion of the channel depends on the voltage on the control gate 30 and the amount of charge residing on the intervening floating gate 20.
  • T2 serves as a select transistor having a select gate 40.
  • T2 When T2 is turned on by a voltage at the select gate 40, it allows the current in the Tl 's portion of the channel to pass between the source and drain.
  • the select transistor provides a switch along the source-drain channel independent of the voltage at the control gate.
  • One advantage is that it can be used to turn off those cells that are still conducting at zero control gate voltage due to their charge depletion (positive) at their floating gates.
  • the other advantage is that it allows source side injection programming to be more easily implemented.
  • One simple embodiment of the split-channel memory cell is where the select gate and the control gate are connected to the same word line as indicated schematically by a dotted line shown in FIG. IB. This is accomplished by having a charge storage element (floating gate) positioned over one portion of the channel and a control gate structure (which is part of a word line) positioned over the other channel portion as well as over the charge storage element.
  • a more refined embodiment of the split-channel cell shown in FIG. IB is when the select gate and the control gate are independent and not connected by the dotted line between them.
  • One implementation has the control gates of one column in an array of cells connected to a control (or steering) line perpendicular to the word line. The effect is to relieve the word line from having to perform two functions at the same time when reading or programming a selected cell. Those two functions are (1) to serve as a gate of a select transistor, thus requiring a proper voltage to turn the select transistor on and off, and (2) to drive the voltage of the charge storage element to a desired level through an electric field (capacitive) coupling between the word line and the charge storage element.
  • FIG. 1C illustrates schematically another flash EEPROM cell having dual floating gates and independent select and control gates.
  • the memory cell 10 is similar to that of FIG. IB except it effectively has three transistors in series.
  • two storage elements i.e., that of Tl - left and Tl - right
  • the memory transistors have floating gates 20 and 20' 5 and control gates 30 and 30', respectively.
  • the select transistor T2 is controlled by a select gate 40. At any one time, only one of the pair of memory transistors is accessed for read or write.
  • both the T2 and Tl - right are turned on to allow the current in the Tl - left's portion of the channel to pass between the source and the drain.
  • T2 and Tl - left are turned on.
  • Erase is effected by having a portion of the select gate polysilicon in close proximity to the floating gate and applying a substantial positive voltage (e.g. 20V) to the select gate so that the electrons stored within the floating gate can tunnel to the select gate polysilicon.
  • FIG. ID illustrates schematically a string of memory cells organized into an NAND cell.
  • a pair of select transistors Sl, S2 controls the memory transistors chain's connection to the external via the NAND cell's source terminal 54 and drain terminal 56.
  • the source select transistor Sl when the source select transistor Sl is turned on, the source terminal is coupled to a source line.
  • the drain select transistor S2 is turned on, the drain terminal of the NAND cell is coupled to a bit line of the memory array.
  • Each memory transistor in the chain has a charge storage element to store a given amount of charge so as to represent an intended memory state.
  • a control gate of each memory transistor provides control over read and write operations.
  • a control gate of each of the select transistors Sl, S2 provides control access to the NAND cell via its source terminal 54 and drain terminal 56 respectively.
  • FIG. IE illustrates schematically a non-volatile memory with a dielectric layer for storing charge.
  • a dielectric layer is used.
  • Such memory devices utilizing dielectric storage element have been described by Eitan et al., "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, no. 11, November 2000, pp. 543-545.
  • An ONO dielectric layer extends across the channel between source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source.
  • United States patents nos. 5,768,192 and 6,011,725 disclose a nonvolatile memory cell having a trapping dielectric sandwiched between two silicon dioxide layers. Multi-state data storage is implemented by separately reading the binary states of the spatially separated charge storage regions within the dielectric.
  • a memory device typically comprises of a two-dimensional array of memory cells arranged in rows and columns and addressable by word lines and bit lines.
  • the array can be formed according to an NOR type or an NAND type architecture.
  • FIG. 2 illustrates an example of an NOR array of memory cells.
  • Memory devices with an NOR type architecture have been implemented with cells of the type illustrated in FIGs. IB or 1C.
  • Each row of memory cells are connected by their sources and drains in a daisy-chain manner. This design is sometimes referred to as a virtual ground design.
  • Each memory cell 10 has a source 14, a drain 16, a control gate 30 and a select gate 40.
  • the cells in a row have their select gates connected to word line 42.
  • the cells in a column have their sources and drains respectively connected to selected bit lines 34 and 36.
  • a steering line 36 also connects the control gates of the cells in a column.
  • FIG. 3 illustrates an example of an NAND array of memory cells, such as that shown in FIG. ID.
  • a bit line is coupled to the drain terminal 56 of each NAND cell.
  • a source line may connect all their source terminals 54.
  • the control gates of the NAND cells along a row are connected to a series of corresponding word lines. An entire row of NAND cells can be addressed by turning on the pair of select transistors (see FIG. ID) with appropriate voltages on their control gates via the connected word lines.
  • a non-volatile memory such as EEPROM is referred to as a "Flash" EEPROM when an entire array of cells, or significant groups of cells of the array, is electrically erased together (i.e., in a flash). Once erased, the group of cells can then be reprogrammed.
  • the group of cells erasable together may consist one or more addressable erase unit.
  • the erase unit or block typically stores one or more pages of data, the page being the unit of programming and reading, although more than one page may be programmed or read in a single operation.
  • Each page typically stores one or more sectors of data, the size of the sector being defined by the host system.
  • An example is a sector of 512 bytes of user data, following a standard established with magnetic disk drives, plus some number of bytes of overhead information about the user data and/or the block in with it is stored.
  • At least one current breakpoint level is established so as to partition the conduction window into two regions.
  • a cell is read by applying predetermined, fixed voltages, its source/drain current is resolved into a memory state by comparing with the breakpoint level (or reference current I RE F)- If the current read is higher than that of the breakpoint level, the cell is determined to be in one logical state (e.g., a "zero" state). On the other hand, if the current is less than that of the breakpoint level, the cell is determined to be in the other logical state (e.g., a "one" state). Thus, such a two-state cell stores one bit of digital information.
  • a reference current source which may be externally programmable, is often provided as part of a memory system to generate the breakpoint level current.
  • flash EEPROM devices are being fabricated with higher and higher density as the state of the semiconductor technology advances.
  • Another method for increasing storage capacity is to have each memory cell store more than two states.
  • the conduction window is partitioned into more than two regions by more than one breakpoint such that each cell is capable of storing more than one bit of data.
  • the information that a given EEPROM array can store is thus increased with the number of states that each cell can store.
  • EEPROM or flash EEPROM with multi-state or multi-level memory cells have been described in U.S. Patent No. 5,172,338.
  • the memory state of a cell is usually read by sensing the conduction current across the source and drain electrodes of the cell when a reference voltage is applied to the control gate.
  • a corresponding conduction current with respect to a fixed reference control gate voltage may be detected.
  • the range of charge programmable onto the floating gate defines a corresponding threshold voltage window or a corresponding conduction current window.
  • the threshold voltage for a given memory state under test is set at the control gate and detect if the conduction current is lower or higher than a threshold current.
  • the detection of the conduction current relative to a threshold current is accomplished by examining the rate the conduction current is discharging through the capacitance of the bit line.
  • FIG. 4 illustrates the relation between the source-drain current I D and the control gate voltage V CG for four different charges Q1-Q4 that the floating gate may be selectively storing at any one time.
  • the four solid I D versus V CG curves represent four possible charge levels that can be programmed on a floating gate of a memory cell, respectively corresponding to four possible memory states.
  • the threshold voltage window of a population of cells may range from 0.5V to 3.5V.
  • Six memory states may be demarcated by partitioning the threshold window into five regions in interval of 0.5V each.
  • Q4 is in a memory state "5".
  • United States Patent No. 4,357,685 discloses a method of programming a 2-state EPROM in which when a cell is programmed to a given state, it is subject to successive programming voltage pulses, each time adding incremental charge to the floating gate. In between pulses, the cell is read back or verified to determine its source-drain current relative to the breakpoint level. Programming stops when the current state has been verified to reach the desired state.
  • the programming pulse train used may have increasing period or amplitude.
  • Prior art programming circuits simply apply programming pulses to step through the threshold window from the erased or ground state until the target state is reached. Practically, to allow for adequate resolution, each partitioned or demarcated region would require at least about five programming steps to transverse. The performance is acceptable for 2-state memory cells. However, for multi-state cells, the number of steps required increases with the number of partitions and therefore, the programming precision or resolution must be increased. For example, a 16-state cell may require on average at least 40 programming pulses to program to a target state.
  • FIG. 5 illustrates schematically a memory device with a typical arrangement of a memory array 100 accessible by read/write circuits 170 via row decoder 130 and column decoder 160.
  • a memory transistor of a memory cell in the memory array 100 is addressable via a set of selected word line(s) and bit line(s).
  • the row decoder 130 selects one or more word lines and the column decoder 160 selects one or more bit lines in order to apply appropriate voltages to the respective gates of the addressed memory transistor.
  • Read/write circuits 170 are provided to read or write (program) the memory states of addressed memory transistors.
  • the read/write circuits 170 comprise a number of read/write modules connectable via bit lines to memory elements in the array.
  • FIG. 6 A is a schematic block diagram of an individual read/write module 190.
  • a sense amplifier determines the current flowing through the drain of an addressed memory transistor connected via a selected bit line. The current depends on the charge stored in the memory transistor and its control gate voltage. For example, in a multi-state EEPROM cell, its floating gate can be charged to one of several different levels. For a 4-level cell, it may be used to store two bits of data. The level detected by the sense amplifier is converted by a level-to-bits conversion logic to a set of data bits to be stored in a data latch.
  • a logical "page" of memory elements are read or programmed together.
  • a row typically contains several interleaved pages. All memory elements of a page will be read or programmed together.
  • the column decoder will selectively connect each one of the interleaved pages to a corresponding number of read/write modules.
  • the memory array is designed to have a page size of 532 bytes (512 bytes plus 20 bytes of overheads.) If each column contains a drain bit line and there are two interleaved pages per row, this amounts to 8512 columns with each page being associated with 4256 columns.
  • the read/write modules forming the read/write circuits 170 can be arranged into various architectures.
  • the read/write circuits 170 is organized into banks of read/write stacks 180.
  • Each read/write stack 180 is a stack of read/write modules 190.
  • the column spacing is determined by the size of the one or two transistors that occupy it.
  • the circuitry of a read/write module will likely be implemented with many more transistors and circuit elements and therefore will occupy a space over many columns. In order to service more than one column among the occupied columns, multiple modules are stacked up on top of each other.
  • FIG. 6B shows the read/write stack of FIG. 5 implemented conventionally by a stack of read/write modules 190.
  • a read/write module may extend over sixteen columns, then a read/write stack 180 with a stack of eight read/write modules can be used to service eight columns in parallel.
  • the read/write stack can be coupled via a column decoder to either the eight odd (1, 3, 5, 7, 9, 11, 13, 15) columns or the eight even (2, 4, 6, 8, 10, 12, 14, 16) columns among the bank.
  • the interleaving page architecture is disadvantageous in at least three respects. First, it requires additional multiplexing circuitry. Secondly, it is slow in performance. To finish read or program of memory cells connected by a word line or in a row, two read or two program operations are required. Thirdly, it is also not optimum in addressing other disturb effects such as field coupling between neighboring charge storage elements at the floating gate level when the two neighbors are programmed at different times, such as separately in odd and even pages.
  • United States Patent Publication No. US -2004-0060031 -Al discloses a high performance yet compact non-volatile memory device having a large block of read/write circuits to read and write a corresponding block of memory cells in parallel.
  • the memory device has an architecture that reduces redundancy in the block of read/write circuits to a minimum.
  • Significant saving in space as well as power is accomplished by redistributing the block of read/write modules into a block read/write module core portions that operate in parallel while interacting with a substantially smaller sets of common portions in a time-multiplexing manner.
  • data processing among read/write circuits between a plurality of sense amplifiers and data latches is performed by a shared processor.
  • the exemplary embodiment uses a quick pass write technique where a single programming pass is used, but the biasing of the selected memory cells is altered to slow programming as the memory cells approach their target values.
  • the memory is verified at a first, lower verify value, followed by a second verify at a second higher level.
  • the second level is used to lock out a selected cell from further programming.
  • the first, lower verify level is used to change the programming phase. In the exemplary embodiment, raising the voltage level of the channels of the selected memory cells does this.
  • a principle aspect of the present invention introduces a latch associated with the read/write circuitry connectable to each selected memory cell along a corresponding bit line for the storage of the result of the verify at this lower level.
  • each memory cell selected for programming will have associated with it N+l latches, N latches to keep track of the target data and an (N+l)st latch for governing the programming phase.
  • the exemplary embodiment is a memory of the NAND-type, specifically in an all bit line architecture.
  • a programming waveform of a rising staircase form is applied along a selected word line.
  • the selected memory cells have their channels set to ground, by setting their corresponding bit lines to ground, in order to facilitate programming.
  • the bit line voltage is raised, in the exemplary embodiment through the level on a set of bit line clamps, so that the channels of the selected memory cells are allowed to come up to a higher voltage level, thereby slowing programming.
  • the exemplary embodiment utilizes a bit line clamp to adjust the bias level on the bit lines.
  • the read/write stack associated with each bit line has a set of data latches usable to govern the write process, with one of these latches used to store the result of the verify at the lower level and thereby govern the programming phase, as well as sufficient latches to monitor the standard programming process.
  • the memory in event of a program failure the memory is able to recover the data without having to maintain a copy of the data until the write is completed.
  • the integrity of the data can thus be maintained with having to save a copy, buffers can be freed up for other data or even eliminated, reducing the amount of controller space that needs to devoted data buffering.
  • the data is recovered by logically combining the verify data for the (failed) write process maintained in data latches with the results of one or more read operations to reconstitute the data.
  • the exemplary embodiments are for memory cells storing multi-state data, both in the format of independent upper page, lower page form, as well as in 2-bit form. Both the upper and lower pages of data can be recovered and then written to a new location in the memory, either as independent pages or as part of a full sequence write. This can be accomplished by a state machine and data latches in the sense amp area on the memory, without use of the controller. Examples of the process are given for various encoding of data into upper and lower pages.
  • FIGs. 1A-1E illustrate schematically different examples of non-volatile memory cells.
  • FIG. 2 illustrates an example of an NOR array of memory cells.
  • FIG. 3 illustrates an example of an NAND array of memory cells, such as that shown in FIG. ID.
  • FIG. 4 illustrates the relation between the source-drain current and the control gate voltage for four different charges Q1-Q4 that the floating gate may be storing at any one time.
  • FIG. 5 illustrates schematically a typical arrangement of a memory array accessible by read/write circuits via row and column decoders.
  • FIG. 6A is a schematic block diagram of an individual read/write module.
  • FIG. 6B shows the read/write stack of FIG. 5 implemented conventionally by a stack of read/write modules.
  • FIG. 7A illustrates schematically a compact memory device having a bank of partitioned read/write stacks, in which the improved processor of the present invention is implemented.
  • FIG. 7B illustrates a preferred arrangement of the compact memory device shown in FIG. 7A.
  • FIG. 8 illustrates schematically a general arrangement of the basic components in a read/write stack shown in FIG. 7A.
  • FIG. 9 illustrates one preferred arrangement of the read/write stacks among the read/write circuits shown in FIGs. TA and 7B.
  • FIG. 10 illustrates an improved embodiment of the common processor shown in FIG 9.
  • FIG. 11A illustrates a preferred embodiment of the input logic of the common processor shown in FIG. 10.
  • FIG. HB illustrates the truth table of the input logic of FIG. HA.
  • FIG. 12A illustrates a preferred embodiment of the output logic of the common processor shown in FIG. 10.
  • FIG. 12B illustrates the truth table of the output logic of FIG. 12A.
  • FIG. 13 shows two distributions of storage elements corresponding to the same memory state for a low and high verify level.
  • FIG. 14 illustrates an example of the programming waveform used in two pass write technique.
  • FIG. 15 illustrates an example of the programming waveform used in a quick pass write technique.
  • FIG. 16 shows a portion of a NAND-type array and its peripheral circuitry in the all bit line architecture.
  • FIG. 17 describes the use of the data latches of FIG. 10 to implement quick pass write for a lower data page.
  • FIG. 18 shows an exemplary verify waveform to illustrate the two verify levels.
  • FIG. 19 is a flowchart for a quick pass write algorithm.
  • FIG. 20 shows a distribution of memory cells for a conventional two page coding.
  • FIG. 21 describes the use of the data latches of FIG. 10 to implement quick pass write for an upper data page in conventional coding
  • FIG. 22 describes the use of the data latches of FIG. 10 to implement quick pass write for full sequence programming.
  • FIGs. 23 and 24 shows a distribution of memory cells for alternate two page codings.
  • FIG. 25 describes the use of the data latches of FIG. 10 to implement quick pass write for an upper data page in alternate two page codings.
  • FIGs.26A and 26B show different methods of assigning upper and lower pages to word lines.
  • FIG. 27 is a schematic illustration of the transfer of data from a host to a memory in a write process.
  • FIG. 28 shows a data latch assignment for upper page/lower page programming.
  • FIG. 29 illustrates a failed lower page write process.
  • FIG. 30 is a table showing a lower page data recovery operation.
  • FIG. 31 is a table showing an upper page data recovery operation when "conventional code" is used.
  • FIG. 32 shows a data latch assignment for full sequence, 2-bit programming.
  • FIG. 33 is a table showing a recovery operation when full sequence, 2-bit programming is used.
  • FIG. 34 is a table showing a data recovery operation when "LM new code" is used.
  • FIGs. 35 and 36 show data latch assignments for two embodiments to recovery lower page data in codes of FIGs. 23 and 24. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • FIG. 7A illustrates schematically a compact memory device having a bank of partitioned read/write stacks, in which the improved processor of the present invention is implemented.
  • the memory device includes a two-dimensional array of memory cells 300, control circuitry 310, and read/write circuits 370.
  • the memory array 300 is addressable by word lines via a row decoder 330 and by bit lines via a column decoder 360.
  • the read/write circuits 370 is implemented as a bank of partitioned read/write stacks 400 and allows a block (also referred to as a "page") of memory cells to be read or programmed in parallel.
  • a page is constituted from a contiguous row of memory cells.
  • a block multiplexer 350 is provided to multiplex the read/write circuits 370 to the individual blocks.
  • the control circuitry 310 cooperates with the read/write circuits 370 to perform memory operations on the memory array 300.
  • the control circuitry 310 includes a state machine 312, an on-chip address decoder 314 and a power control module 316.
  • the state machine 312 provides chip level control of memory operations.
  • the on-chip address decoder 314 provides an address interface between that used by the host or a memory controller to the hardware address used by the decoders 330 and 370.
  • the power control module 316 controls the power and voltages supplied to the word lines and bit lines during memory operations.
  • FIG. 7B illustrates a preferred arrangement of the compact memory device shown in FIG. 7A.
  • Access to the memory array 300 by the various peripheral circuits is implemented in a symmetric fashion, on opposite sides of the array so that access lines and circuitry on each side are reduced in half.
  • the row decoder is split into row decoders 330A and 330B and the column decoder into column decoders 360A and 360B.
  • the block multiplexer 350 is split into block multiplexers 350A and 350B.
  • FIG. 8 illustrates schematically a general arrangement of the basic components in a read/write stack shown in FIG. 7A.
  • the read/write stack 400 comprises a stack of sense amplifiers 212 for sensing k bit lines, an I/O module 440 for input or output of data via an I/O bus 231, a stack of data latches 430 for storing input or output data, a common processor 500 to process and store data among the read/write stack 400, and a stack bus 421 for communication among the stack components.
  • a stack bus controller among the read/write circuits 370 provides control and timing signals via lines 411 for controlling the various components among the read/write stacks.
  • FIG. 9 illustrates one preferred arrangement of the read/write stacks among the read/write circuits shown in FIGs.7A and 7B.
  • the entire bank of partitioned read/write stacks 400 operating in parallel allows a block (or page) of p cells along a row to be read or programmed in parallel.
  • p p/k.
  • the block is a run of the entire row of cells.
  • the block is a subset of cells in the row.
  • the subset of cells could be one half of the entire row or one quarter of the entire row.
  • the subset of cells could be a run of contiguous cells or one every other cell, or one every predetermined number of cells.
  • Each read/write stack such as 400-1, essentially contains a stack of sense amplifiers 212-1 to 212-k servicing a segment of k memory cells in parallel.
  • a preferred sense amplifier is disclosed in United States Patent Publication No. 2004-0109357-A1, the entire disclosure of which is hereby incorporated herein by reference. It should be noted that this is just one particular embodiment, with k as the number of bits in a byte and r is the number of bytes that are grouped together.
  • the particular data latch structure is not basic to the various aspect of the invention, as long as a sufficient number of data latches, specifically one for each bit storable on a cell, is connectable to a bit line.
  • the stack bus controller 410 provides control and timing signals to the read/write circuit 370 via lines 411.
  • the stack bus controller is itself dependent on the memory controller 310 via lines 311. Communication among each read/write stack 400 is effected by an interconnecting stack bus 431 and controlled by the stack bus controller 410.
  • Control lines 411 provide control and clock signals from the stack bus controller 410 to the components of the read/write stacks 400-1.
  • the stack bus is partitioned into a SABus 422 for communication between the common processor 500 and the stack of sense amplifiers 212, and a DBus 423 for communication between the processor and the stack of data latches 430.
  • the stack of data latches 430 comprises of data latches 430-1 to 430-k, one for each memory cell associated with the stack
  • the I/O module 440 enables the data latches to exchange data with the external via an I/O bus 231.
  • the common processor also includes an output 507 for output of a status signal indicating a status of the memory operation, such as an error condition.
  • the status signal is used to drive the gate of an n-transistor 550 that is tied to a FLAG BUS 509 in a Wired-Or configuration.
  • the FLAG BUS is preferably precharged by the controller 310 and will be pulled down when a status signal is asserted by any of the read/write stacks.
  • FIG. 10 illustrates an improved embodiment of the common processor shown in FIG 9.
  • the common processor 500 comprises a processor bus, PBUS 505 for communication with external circuits, an input logic 510, a processor latch PLatch 520 and an output logic 530.
  • the input logic 510 receives data from the PBUS and outputs to a BSI node as a transformed data in one of logical states "1", “0", or “Z” (float) depending on the control signals from the stack bus controller 410 via signal lines 411.
  • a Set/Reset latch, PLatch 520 then latches BSI, resulting in a pair of complementary output signals as MTCH and MTCH*.
  • the output logic 530 receives the MTCH and MTCH* signals and outputs on the PBUS 505 a transformed data in one of logical states "1", “0", or "Z" (float) depending on the control signals from the stack bus controller 410 via signal lines 411.
  • FIG. 10 illustrates the case for the memory cell coupled to bit line 1.
  • the corresponding sense amplifier 212-1 comprises a node where the sense amplifier data appears.
  • the node assumes the form of a SA Latch, 214-1 that stores data.
  • the corresponding set of data latches 430-1 stores input or output data associated with the memory cell coupled to bit line 1.
  • the set of data latches 430-1 comprises sufficient data latches, 434-1, ..., 434-n for storing n-bits of data.
  • the PBUS 505 of the common processor 500 has access to the SA latch 214-1 via the SBUS 422 when a transfer gate 501 is enabled by a pair of complementary signals SAP and SAN. Similarly, the PBUS 505 has access to the set of data latches 430-1 via the DBUS 423 when a transfer gate 502 is enabled by a pair of complementary signals DTP and DTN.
  • the signals SAP, SAN, DTP and DTN are illustrated explicitly as part of the control signals from the stack bus controller 410.
  • FIG. HA illustrates a preferred embodiment of the input logic of the common processor shown in FIG. 10.
  • the input logic 520 receives the data on the PBUS 505 and depending on the control signals, either has the output BSI being the same, or inverted, or floated.
  • the output BSI node is essentially affected by either the output of a transfer gate 522 or a pull-up circuit comprising p-transistors 524 and 525 in series to Vdd, or a pull-down circuit comprising n-transistors 526 and 527 in series to ground.
  • the pull-up circuit has the gates to the p-transistor 524 and 525 respectively controlled by the signals PBUS and ONE.
  • the pull-down circuit has the gates to the n-transistors 526 and 527 respectively controlled by the signals ONEB ⁇ 1> and PBUS.
  • FIG. HB illustrates the truth table of the input logic of FIG. HA.
  • the logic is controlled by PBUS and the control signals ONE, ONEB ⁇ 0>, ONEB ⁇ 1> which are part of the control signals from the stack bus controller 410.
  • PBUS control signals
  • ONE, ONEB ⁇ 0>, ONEB ⁇ 1> which are part of the control signals from the stack bus controller 410.
  • three transfer modes, PASSTHROUGH, INVERTED, and FLOATED are supported.
  • the pull-down circuit when PBUS is at "0", the pull-down circuit will be disabled while the pull-up circuit is enabled, resulting in BSI being at "1". Similarly, when PBUS is at "1", the pull-up circuit is disabled while the pull-down circuit is enabled, resulting in BSI being at "0". Finally, in the case of the FLOATED mode, the output BSI can be floated by having the signals ONE at "1", ONEB ⁇ 0> at "1" and ONEB ⁇ 1> at "0".
  • the FLOATED mode is listed for completeness although in practice, it is not used.
  • FIG. 12A illustrates a preferred embodiment of the output logic of the common processor shown in FIG. 10.
  • the signal at the BSI node from the input logic 520 is latched in the processor latch, PLatch 520.
  • the output logic 530 receives the data MTCH and MTCH* from the output of PLatch 520 and depending on the control signals, outputs on the PBUS as either in a PASSTHROUGH, INVERTED OR FLOATED mode.
  • the four branches act as drivers for the PBUS 505, actively pulling it either to a HIGH, LOW or FLOATED state. This is accomplished by four branch circuits, namely two pull-up and two pull-down circuits for the PBUS 505.
  • a first pull-up circuit comprises p-transistors 531 and 532 in series to Vdd, and is able to pull up the PBUS when MTCH is at "0".
  • a second pull-up circuit comprises p-transistors 533 and 534 in series to ground and is able to pull up the PBUS when MTCH is at "1".
  • a first pull-down circuit comprises n-transistors 535 and 536 in series to Vdd, and is able to pull down the PBUS when MTCH is at "0".
  • a second pull-up circuit comprises n-transistors 537 and 538 in series to ground and is able to pull up the PBUS when MTCH is at "1".
  • One feature of the invention is to constitute the pull-up circuits with PMOS transistors and the pull-down circuits with NMOS transistors. Since the pull by the NMOS is much stronger than that of the PMOS, the pull-down will always overcome the pull-up in any contentions. In other words, the node or bus can always default to a pull-up or "1" state, and if desired, can always be flipped to a "0" state by a pull-down.
  • FIG. 12B illustrates the truth table of the output logic of FIG. 12A.
  • the logic is controlled by MTCH, MTCH* latched from the input logic and the control signals PDIR, PINV, NDIR, NINV, which are part of the control signals from the stack bus controller 410.
  • Four operation modes, PASSTHROUGH, INVERTED, FLOATED, and PRECHARGE are supported.
  • FIG. 13 shows two distributions of storage elements corresponding to the same memory state, where in a first pass the cells have been written with a programming waveform PWl using a first, lower verify level VL, producing distribution 1301. The programming waveform then starts over at lower value for the second pass. In the second pass, a programming waveform PW2 uses a second, higher verify level VH, to shift this to distribution 1303. This allows the first pass to place the cells into a rough distribution that is then tightened up in the second pass.
  • a example of the programming waveform is shown in FIG. 14.
  • the first staircase PWl 1401 uses the lower verify level VL, while PW2 uses the upper verify level VH.
  • the second pass (PW2 1403) may use a small step size, as described in U.S. patent number 6,738,289, but, aside from the different verify levels, the processes are the same.
  • each programming sequence requires the programming waveform to go through both of the full staircases, executing 1401 and starting over with 1403. Writing could be executed more quickly if it were possible to use a single staircase, allowing for the distribution to be subjected to an initial programming phase based on a lower verify VL, but still be able to slow down the process once this initial level is reached and refine the distribution using the higher verify VH.
  • the programming waveform QPW 1501 is shown in FIG. 15 and, in a first phase, the process proceeds as for the first phase of the two-pass algorithm, except that the verify is performed at both the VL and VH level (see FIG. 18 for detail); however, once a verify at VL occurs, rather than restart the staircase waveform, the staircase continues, but with the bit line voltage raised to slow the process as it continues until the cells verify at VH. Note that this allows the pulses of the programming waveform to be monotonically non-decreasing. This is explained further with respect to FIG. 16.
  • FIG. 16 shows a portion of a NAND type array and its peripheral circuitry in the all bit line architecture. This is similar to the arrangement shown in a number of the preceding figures, but only the elements relevant to the present discussion are given here, with the other elements omitted to simplify the discussion.
  • FIG. 16 also explicitly shows the bit line clamp 621 as separate from the other elements of the read/write stack. The details of the word line clamp are described further in a U.S. patent application entitled “Non- Volatile Memory and Method with Power-Saving Read and Program- Verify Operations" filed March 16, 2005, and, particularly, numbered 11/015,199, filed December 16, 2004,, which are both incorporated by reference above.
  • FIG. 16 shows three NAND strings 610 A-C each connected along a corresponding bit line through bit line clamp 621 to a respective sense amplifier SA-A to SA-C 601A-C.
  • the selected memory cells such as 613 A are programmed by establishing a voltage difference between the control gate and channel, causing charge to accumulate on the floating gate.
  • the programming waveform, QPW 1501 of FIG. 15, is applied along the selected word line WL 625.
  • the channels are held low (ground) to establish the needed potential difference.
  • a verify is performed. Whether a cell is to be programmed corresponds to the VH value of the target state.
  • the verifies of the first pass use the lower VL level, while those of the second pass uses the VH level.
  • the present technique differs from the two-pass technique in that both the VL and the VH levels are used for the verifies are performed between pulses and in what happens once a cell verifies at this lower level.
  • the programming waveform after a successful verify at the lower VL level, the programming waveform starts over but the verifies now use the VH level; here, the programming waveform continues, but the bit line biases are altered, being raised in order to slow down the programming rate.
  • the lower verify could be dropped, leaving only the VH verify, once the second phase begins. Similarly, on the first few pulses, the VH verify could be omitted.
  • the present embodiment will include both the VL and VH verifies through out a given write process.
  • V BLC VQ PW +V T , where VQPW is less than Vdd-
  • the non-selected cells will still be program inhibited, but the channel in the selected NAND strings will raise somewhat, slowing down the programming rate even though the programming voltage waveform supplied along WL 625 continues to ascend the staircase.
  • the bit line voltage is raised, the second phase continues along the same programming waveform, but the inter-pulse verifies use the higher VH level of the target state. As the cells individual verify, they are locked out as the corresponding latch DLS 603 flips and the bit line is raised to Vdd- The process continues until the entire page is finished writing.
  • FIG. 17 describes the use of the data latches 434-i of 430 (FIG. 10) of the exemplary all bit line architecture to implement this process.
  • FIG. 17 reproduces only selected items of FIG. 10, arranged in an exemplary topology, in order to simplify discussion. These include data latch DLO 434-0, which is connected Data I/O line 231, data latch DLl 434-1, connected to common processor 500 by line 423, data latch DL2 434-2, commonly connected with the other data latches by line 435, and sense amp data latch DLS 603 (equivalent to 214 of FIG. 10), which is connected to common processor 500 by line 422.
  • each bit line has three associated data latches. (In the more general n-bit case, the number of data latches would be n+1).
  • the introduction of the extra latch, DL2 434-2, is used to manage which of the two programming phases the quick pass write algorithm is executing.
  • the data latches DLO 434-0 and DLl 434-1 are used for writing the two bits of data into the cell based upon the "standard" verify level VH: when the lower page is being programmed, only one of this latches is strictly required, but when the upper page is being programmed one of these latches is used for the data of the upper page and the other for the previously programmed lower page, since the programming of the upper page depends upon the state of the lower page in this arrangement.
  • a latch can be used to indicate the result of a verify at the lower VL level, upon which the change from the first phase of the quick pass write, where the channel a selected element is held low, to the second phase, where the channel level is raised to slow programming.
  • the registers 434-i are labeled for the quick pass write of the lower page, which is implemented similarly to the case for a binary memory.
  • the lower page original data is loaded along I/O line 231 to DLO 434-0, transferred into DLl 434-1 that serves for VH verify, and subsequently transferred into DLS 603 where it is used to determine whether the bit line is program enabled or inhibited.
  • Latch DL2 434-2 is used for VL lockout.
  • Program verify can be performed between programming pulses with a waveform such as shown in more detail in FIG. 18 applied to the selected word line WL 625.
  • the waveform is raised from ground (1801) to the first, lower verify level VL (1803) and then further raised to the higher VH (1805).
  • the other voltage levels on the array are at typical read values as described in the references incorporated above. This allows the two program verifies to be done consecutively according to the following steps:
  • a first verify level uses the lower verify level VL (1803), with the data then being transferred to data latch DL2434-2.
  • the second verify is higher verify level performed when the verify waveform is at 1805.
  • the result of VH will be transferred to data latch DLl 434-1.
  • the bit line bias setup will depend both of the VL and VH verify results.
  • VL verify result in NDL is transferred to SA data latch DLS 603 to charge bitlines from 0 to VQ PW (if the cell verified), or to keep the bit line at 0 (if the data is "0").
  • FIG. 19 is a flowchart of the program/verify sequence based on the latches of the read/write stacks of the exemplary all bit line embodiment.
  • the initial condition of the data latches is established in steps 701-703, the program bias conditions are set and the program waveform is applied in steps 711-717, and the verify phase is in steps 721-725.
  • the order here is that of an exemplary embodiment and order of many steps can be rearranged, as long as, for example, the correct bias levels are established before the word line is pulsed.
  • step 701 data is read in on line 231 into latch DLO 434-0 and subsequently transferred to latch DLl 434-1 in step 702.
  • step 703 it is further transferred into latch DL2434-2. This sets the target data for the write process, where the convention used is that where a value of "0" corresponds to program and a value of "1" to program inhibit.
  • the programming phase begins by setting the correct bias conditions based on the latches.
  • the voltage to bit line clamp line is set at V dd +V ⁇ , the normal programming levels of the first phase of quick pass write, and, in step 712 the value held in latch DL0/DL1 is transferred to into latch DLS 603 of the sense amp, where a value of "0" (program) will result in the bit line held at ground and a value of "1" (inhibit) will effect a bit line value of V dd .
  • step 713 will set the voltage to the bit line clamp lines at V dd +VT so that the channels along the selected bit lines are held at ground for programming and the channels along the non-selected bit lines are left to float in order to inhibit programming.
  • the value in DL2434-2 is transferred to sense amp data latch DLS 603 in step 715. In the first cycle through, this will be the initial value set in DL2. Once the cell verified at VL, the lowered V BLC value set in step 714 will then cause the bit line level to be raised from 0 to VQ PW in the cells being programmed, thereby slowing the programming rate and transitioning to the second quick pass write phase.
  • step 717 the programming pulse (QPW 1501, FIG. 15) is applied to the selected word line WL 625, the bias on the other lines having been established in the preceding steps.
  • the inter-pulse verify phase begins at step 721 when the various bias voltages on are established prior to raising the selected word line to VL.
  • step 722 the word line's verify waveform raises to the lower margin VL (1803 FIG. 18) and, if the cell verifies, the latch in sense SA 601 trips and the value in DLS 603 switches from "0" to "1", the result then being transferred by the common processor 500 to DL2434-2 in step 723.
  • step 724 the verify level is then raised to the higher margin VH (1805) and if the cell verifies DLS 603 is set, the result then being transferred by the common processor to DLl 434-1 in step 725.
  • step 712 the VH verify result as indicated by the value now in DLl 434-1 is transferred; if the cell verified at VH, it will be program inhibited and the sense amp bit is changed form "O" to "1" to take the bit line high and inhibit further programming.
  • the VL verify result as now indicated by the value in DL2 434-2, is transferred to sense amp data latch DLS 603 in step 715; if the cell verified at VL, the bit line voltage is then raised in step 716.
  • FIG. 20 shows a first distribution 1301 and a second distribution 1303 respectively corresponding to each state's lower verify VL, used in the first programming phase of the quick pass write, and higher verify VH, used in the second phase.
  • the "conventional" coding of these programmed states into upper and lower page data is given under the distributions. In this coding, the states with lower page data "0" will have been programmed to the 1303 -A distribution using the levels VAL and VAH in a quick pass write when the lower page was programmed as previously described.
  • the upper page write is to program the B and C states.
  • the VL lockout information will be accumulated in data latch DL2 434-2, with its initial value again transferred in from DLl 434-1 and corresponding to the original program data to indicate if the cell is to undergo upper page programming.
  • the bit line bias for the B and C state's quick pass write is the same; in a variation, additional latches can be introduced to allow the B and C states to employ different bias levels.
  • VL lockout information is only used for temporary storage. The data in the data latch DL2434-2 for VL will be changed from "0" to "1” after passing each VL verify sensing. The logic is such that it will not allow a "1" value to flip back to "0" during a given programming run.
  • VH lockout is also accumulated through many different verify sensing. As soon as the bits passed verify level of its intended program state, the data in the data latch will be changed to "11". For example, if the B state passed verify VBH, then the data in data latch "00" will be changed to ⁇ "11 ⁇ ". If the C state passed verify VCH, then the data in data latch "01" will be changed to "11". The logic is such that it will not allow a "1" value to flip back to "0" during a given programming run. Note that for upper page programming, VH lockout may occur based on only one data latch.
  • U.S. patent application number 11/013,125 filed December 14, 2004, describes a method where the programming of multiple pages held by the same set of multi-state memory elements can be overlapped. For example, if while writing a lower page the data for the corresponding upper becomes available, rather than wait for the lower page to finish before beginning to program the upper page, the write operation can switch to a full programming sequence where the upper and lower pages are programmed concurrently into the physical page.
  • the quick pass write technique can also be applied to the full sequence operation.
  • FIG. 22 shows the use of the data latches DL0-DL2 for the full sequence write and is similar to FIG. 17, but with the notation indicating the use of the different latches changed accordingly.
  • DLO 434-0 is used for the upper page lockout data and will receive the corresponding VH verify result
  • DLl 434-1 is used for the lower page lockout data and will receive the corresponding VH verify result
  • DL2 434-2 is again used to hold the VL lockout data.
  • the initial DL2 434-2 value corresponds to the initial program data
  • the initial value at the time of the full sequence transition will account for the upper and lower page data. Consequently, rather than also just loading the appropriate, single page original program data into DL2 434-2, it is now only set to "1" if both of the latches DLO and DLl are "1".
  • the full sequence operation with quick pass write can include the following steps:
  • the first page data is loaded into latch DLO 434-0 and the lower page can start programming as described above.
  • latch DLO 434-0 can be reset and be ready to sequentially load another page, allowing the upper page on the same word line WL 625 to transferred in when available.
  • the lower page original data may have been locked out to -!!H-!! for cells that passed program verify A. These data should be read at the A level to recover their original data, since the two-bit full sequence write needs both the lower and the upper page data to program.
  • the program verifies for the A, B, and C states can be performed at the same time or separately.
  • the lockout process can also lockout the both latches at the same time.
  • the upper page program then moves cells from the intermediate distribution to a final target state of either the B or C distribution and programs cells with "01" data from the "11" state's E distribution into the A distribution.
  • the upper page write using quick pass write in both LM codes is done similarly to the upper page program described above for the conventional code, the difference being that lower page will also lockout as the state B and state C are coming from intermediate state (dotted line).
  • the upper page program algorithm for the LM codes is also similar to the full sequence quick pass write algorithm in that both VH lockout data are updated after the VH verify.
  • the upper page is also the same as in the conventional code if the lower and upper page codes are switched, in which case the upper page in the LM old code is the same as full sequence program.
  • FIG.25 again shows the data latches and their assignment for the LM codes in a manner similar to FIG.22 and other similar figures above.
  • Lower page data is read into DLO 434-0, the upper page lockout data based on VH is held in DLl 434-1, and DL2 434-2 is again assigned the VL lockout data used to control the phase shift for the quick pass write technique.
  • quick pass write for the lower states but not using quick pass write for the C state can complicate the programming algorithms. For example, at certain point of the write process, a program pulse is followed by verify A (with QPW), verify B (with QPW), and verify C (no QPW), which is then followed by another program pulse. Since the quick pass write algorithm describe above uses two data transfers for program pulse (a first data transfer to lockout VH and a second data transfer to lockout VL), the first data transfer will have no problems for all three states; but the second transfer will, under the above arrangements, result in a program error for state C.
  • QPW quick pass write
  • state C will not do verify VCL at the lower level, then the DL2 434-2 data latch is not updated for this bit line. If this bit line needs to be locked out after passing the high VCH verify level for C, the VH lockout data latch will transfer "1" to the SA data latch for program inhibit after the first data transfer. However, the VL data latch (DL2 434-2) will still hold data since there is no verify result to update it. Therefore, the second data transfer will transfer a "0" to the DLS 603 of the bit line. This would result in the pre-charged bit line being discharged to 0, causing this bit line to over-program.
  • the algorithm is modified by updating the VL data latch (DL2 434-2) with a C verify at the high level of VCH.
  • VL data latch DL2 434-2
  • both VH and VL lockout data will be changed to "1" and programming will be inhibited.
  • the program algorithm can switch to standard programming with no quick pass write, or noQPW algorithm, as only the C state is left and it will only use the corresponding VH verify level. In this case, only a single data transfer (of the VH level, the VL level not being used) will be done
  • one way of storing data is to write the memory as independent pages, such that (in the four state example) each 2-bit memory cell stores a bit from an upper page and a bit from the lower page.
  • the common arrangement is to write a lower page of data and some time later, in a separate process, to write the upper page.
  • the programming of the upper page fails, the data content of the lower page data is also lost.
  • both lower and upper page data can be recovered and copied to another location without having to maintain a copy of the data buffer on the controller or with other help from the controller. This allows for the buffers on the controller to freed up for other data or to reduce the amount of buffer on the controller, which can be valuable space, to be reduced.
  • the process can be accomplished on the memory by the state machine (312, FIG. 7A) in the memory's control circuitry (310) and data latches (430, FIGs. 8 and 15) in the sense amplifier area.
  • state machine 312, FIG. 7A
  • data latches 430, FIGs. 8 and 15
  • the state machine 312, FIG. 7A
  • data latches 430, FIGs. 8 and 15
  • the state machine 312, FIG. 7A
  • data latches 430, FIGs. 8 and 15
  • the process can be accomplished on the memory by the state machine (312, FIG. 7A) in the memory's control circuitry (310) and data latches (430, FIGs. 8 and 15) in the sense amplifier area.
  • DLO 434-0 and DLl 434-1 corresponding to the two bits stored per cell in the exemplary embodiment, and do not require the use of DL2434-2.
  • the resultant improves are even greater as the page size used in memory system continues to increases.
  • FIG. 26a shows an array or portion of an array 700 and several representative word lines, where the broken line indicating the two pages can be written in together in the exemplary all bit line architecture.
  • Pages 0, 1 are the lower pages and 2,3 are the upper pages word lines 701. (0, 1 are written above the line to indicate they are written first, somewhat contrary to how they are named.) If the page 2, 3 are then programmed with errors beyond the ability of the ECC to repair, not only does the page 2,3 data need to be programmed , but also the page 0, 1 data will need to be re-programmed to another location.
  • Lower-Middle (LM) code (FIGS.23 and 24) is designed to reduce bit line to bit line and word line to word line coupling effects.
  • the page arrangement is shown in FIG. 26b.
  • the upper page sharing word line 701 with page 0,1 is now 4, 5 instead 2,3 in this case.
  • page 4, 5 are written with error and fail to verify, page 0,1 will also need to be corrected. Since the page numbers for upper pages are not sequential with the lower pages on the same word line, users will not have kept the lower page information to enable these pages re-programmed.
  • the LM lower page is also destroyed by the upper page program failure, as can be seen by referring to FIG. 24. This is caused by the initial programming of lower page not to B level, but to distribution having the broken line A level. If the lower page is initially programmed to B verify level, then the upper page failure would not affect the integrity of the lower page data, but the advantage of fast lower page program will be eliminated. It would again be a great advantage if the lower page data can be recovered even the upper page program failed. If the upper page program data is still in the controller data buffer, and if the lower page is reserved, it can be combined and copied to another good WL. The bad data will be for the whole word line, which can be marked as bad (using a flag). However, this does require maintaining the data on the controller. FIG. 27 shows this schematically.
  • FIG. 27 is a schematic drawing showing the flow of data as it is received from a host and programmed into the memory array 300.
  • the data is first received at the controller 801 (as is usually distinct from the control circuitry 310 (FIG. 7A) on the memory 811), which contains some amount cache memory 803 used to buffer the data as it collected and then transferred on to the memory 811.
  • cache memory 803 used to buffer the data as it collected and then transferred on to the memory 811.
  • buffer memory is typically expensive in terms of space of cost and area, it is preferable to not have more of such memory than is needed; however, such is the required needed for such buffering in typical memory operations that a significant portion of controller space may be given over to buffer memory. This particularly true as page size increases.
  • the data is then transferred into memory 811 to the data latches of the read/write circuits 370 from where it can be written into the memory array 300.
  • latch DLO 434-0 is used to hold the lower page data from sensing the lower page before starting the upper page program.
  • the case of upper page failure due to very slow bits can be dealt with in several ways:
  • the corresponding upper page in the controller's buffer 803 can be shifted in to the read/write circuits 370 and 2-bit programming (full sequence program) can be started in the next word line.
  • 2-bit programming full sequence program
  • FIG.29 shows the case where lower page data is under programmed and will be used as a first example of data recovery. If the memory was to have been programmed to the A state (lower page data "0"), a successful write will have verified at A states verify level and placed it somewhere in the A distribution. If the cell fails to verify, it may be anywhere between the E state distribution and the lower end of A distribution. When read with the value readA, it may still read as an A state (returning a "1" to the sense amp) if it is above readA even if it failed to verify. If instead it was left somewhere below readA level (as shown by the X), the sense amp will return a "0" and the cell will read, incorrectly, as the E state.
  • the top line corresponds to the lower page data to have been written into the cell and assume that there was a write failure so that some cells to have been written to the A state are left below the readA, as shown by the X of FIG. 29.
  • DLl 434-1 is the data latch holding the program lockout information and the notation is that ⁇ SA means reverse of SA data and "&" means a logic AND.
  • line (2) reads 1 for both target data states.
  • the following invention can also be implemented when two (or more) bits are programmed concurrently. Even in the upper page/lower page arrangement, 2-bit programming can occur as part of a lower page to full sequence conversion, such as is described in U.S. patent application Serial Number 11/013,125 ("Overlapped Programming of Upper and Lower MLC Pages" section), or when, after a program fail, both the upper and lower page are written concurrently to the new location.
  • the 2-bit recovery logic can also be used in systems arranged with the 2 bits are located on the same page.
  • a normal read of lower page data is (readA OR ⁇ readC); that is, the readA result is logically OR-ed with the reverse of the readC result, where both readA and readC (and readB) are the reverse data from the sense amp ( ⁇ SA).
  • the normal upper page read is just readB.
  • This step combines the readA result with the DLl 434-1 remaining data (AND logic) and saves the result in DLl 434-1.
  • This step combines reverse readC result with the DLl 434-1 previous data (OR logic) and also checks if the bits are Ol and saved the result in DLl 434-1.
  • the readC data and the DLl 434-1 data is not sufficient to recover the original data.
  • the failed C state must be confirmed by checking both DLl 434-1 and DLO 434-0 using AND logic ( ⁇ DL0 & DLl ). (This is shown as step 5' in FIG. 33, which is only explicitly shown there in some cases.)
  • FIG. 33 shows the results of these steps for the various cases.
  • line 4 shows the recovered upper page data and line 6 the recovered lower page data.
  • a logical OR is represented as
  • ⁇ readC is readA OR ⁇ readC). Where the table indicates "0/1", this indicates that either result may be returned depending on whether the cell lies.
  • the step 5' is shown only in the C error cases. As the state machine normally cannot know what type of error has occurred, the extra logic operation done in the case of C error is also applied to the cases with other errors, although it is not necessary there. Therefore all the logic operations are applied to all the cases listed here. Step (5') is not explicitly shown in many cases for simplicity, since the extra logic operation will not produce different results from the data listed in the table.
  • FIG. 33 the various cases are shown in the order corresponding to three programmed states of the example: an A-state error, followed by a B-state error, followed by a C-error for when the readA process passed and then when it failed.
  • various read processes are done in the order of the states (A, B, C), and that, consequently, the upper page recovery steps fall in the middle of the lower page recovery steps; that is, steps (1), (2), (5), and (6) respectively correspond to steps (i)-(iv) of the lower page recover described above, with (3) and (4) corresponding to (i) and (ii) of the upper page recovery.
  • step (1) the readA result will yield a 1 for the "10" state, which, when combined by the logic with the DLl contents, leads to line (2).
  • step (5) the lower page data recovery continues at step (5) with readC, which is then combined according to the logic with the result of step (2) to recover the lower page data at line (6).
  • step (3) is omitted as the error is assumed to be for the A state here.
  • step (1) readA can yield either 1 or 0 depending on where the cell ended up: in either case, the logic gives a 0 for the "00" column is line (2).
  • step (3) yielding a 1 for the "00", giving the recovered upper page data in step (4) when combined according to the logic with DLO.
  • step (6) the result of readC is taken and combined in step (6) to give the correct lower page data.
  • step (1) Assuming a C state error, the upper page data in DLO will have an erroneous 0 in the "01" column. Assuming the readA operation passes, steps (1) and (2) will correctly have (1,0,0,0) for the four states. In step (3), however, depending on how far the cell made it, it may end up either below or above the readB level and can give either 1 or 0 for the "01" column. In either case, the logic will correct this and the upper page data is recovered in line (4). Returning to the lower page recovery, as the error is assumed to be in the C state, step (5) gives 0 for all columns.
  • step (5') is used to rectify this.
  • the failed C state is then confirmed by checking both DLl 434-1 and DLO 434-0 using AND logic ( ⁇ DL0 & DLl ), which is combined with line (2) to give the restored lower page data in step (6).
  • step (l)-(3) give an erroneous 1 for the "01" column.
  • the correct data is recovered in step (4) as for the preceding C fail, A pass case.
  • step (5) readC again gives 0 for all states and needs to be rectified by step (5'), giving 1 in the "01" column, which the logic then migrates to line (6) and the restored lower page data.
  • the memory will be aware of which programming mode it is operating in (upper page, lower page, or full sequence), can select the proper recovery mode when program fail is returned.
  • the recovery process involves combining the (failed) verify data remaining in the latches with the results of one or more reads. Based on these combinations, the correct data can then be recovered on the memory using only the data latches and the state machine without having to maintain a copy of the data in a buffer on the controller (or on the memory once it is loaded into the latches).
  • the upper page normal read is consequently readA
  • the lower page normal read is then readB. Since the codes have such similarity, the recovery method is also the same with conventional.
  • This step combines the readA result with the DLl 434-1 remaining data (AND logic) and saves the result in DLl 434-1.
  • This step combines read B result with the remaining DLO 434-0 data and saves the result in DLO 434-0.
  • This step combines readA result with the remaining DLO 434-0 data and saves the result in DLO 434-0.
  • the "LM new" code is shown in FIG. 24.
  • the normal upper page read is given by (readA OR ⁇ readB ) AND readC; that is, the readA data will be combined with reverse readB data using OR logic first, with the combined result further combined with the readC result using AND logic.
  • the normal lower page read is just readB, as it is with LM old code lower page, although the LM flag needs to be checked: in this code, if the upper page has not been programmed and only a lower page has been written to the word line, readA is used instead.
  • step (1) readA then gives 1 in the "01" column, which is then corrected by ANDing with DLO in step (2).
  • Step (4) then combines ⁇ readB (from step (3)) with the result of step (2), which is then further combined in step (6) with readC (step (5)) to obtain the corrected upper page data.
  • the expressions ( ⁇ DL0 AND DLl)) and (DLO OR DLl) are not explicitly computed as they drop out of the expression.
  • FIG. 34 only shows the upper page recovery process for the LM new code.
  • the LM old and LM new codes both have the same encoding of the lower pages data and for the LM new code, the lower page data can again be recovered by (readB AND DLl) as described for the LM old code.
  • the data recovery can be done in the following simple rules regardless which code being used.
  • the remaining verify data is combined with the results of one or more read operations in logical operations to extract the intended target data by using non-overwrite logic combining the remaining data in data latches and sensing results.
  • both LM codes initially program the lower page to the broad X distribution as described in US patent application Ser. No. 11/083,514, which is incorporated herein by reference.
  • both codes separate the two bits on the same physical cell into two separate logical pages
  • an upper page program failure will destroy the lower page data that was previously program. Since the lower page may have be programmed quite some time previously, the data recovery becomes very important since this data is no longer held by the controller memory. Even if the lower page was relatively recently programmed, maintaining the lower page in the controller would require large amounts of buffering, which is not preferred.
  • the data latches are assigned in the following diagram as in FIG. 35.
  • DLO 434-0 is the lower bit data read in from the array:
  • the lower bit for erase and A, B, C states will respectively be 1, 1, 0, 0.
  • DLl 434-1 will hold the upper page program data, which was input from user for the current program.
  • the LM old code for the upper bit for erase and A, B, C states will respectively be 1, 0, 0, 1.
  • this time is normally in the order of 150 ⁇ s, which is enough time for the user to extract and toggle out the lower bit data to copy it to another location, such as buffering it on the memory or the controller or to latches for another physical page.
  • the LM new code case will be similar to the LM old code in recovering the lower bit program data during upper page program failure as the lower page is encoded the same for both codes.
  • Another embodiment that can be used obtain a good copy of the lower page data in the LM codes uses the extra latch, DL2434-2, for lockout, allowing for the original data to be kept until the end of the write.
  • the sort of cache programming described in US patent application serial number 11/097,590 may not be allowed in this case.
  • the data latch assignment here is shown in FIG. 36.
  • DL2 is used for the program lockout, rather than for the

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)

Abstract

Un dispositif de mémoire non volatile possède la capacité de récupérer des données en cas d'échec de programme sans avoir à maintenir une copie de ces données jusqu'à ce que l'écriture soit effectuée. Comme l'intégrité des données peut ainsi être maintenue sans avoir à sauvegarder une copie, des tampons peuvent être libérés pour d'autres données, voire éliminés, réduisant la quantité d'espace de contrôleur nécessaire pour mettre en tampon des données attribuées. Dans des modes de réalisation de l'invention, les données sont récupérées par combinaison logique de données de vérification du processus d'écriture (en échec) maintenues dans des verrous de données avec les résultats d'une ou de plusieurs opérations de lecture pour reconstituer ces données. Ces modes de réalisation de l'invention sont destinées à des cellules mémoire stockant des données à états multiples, dans le format de page supérieure indépendant, dans la forme de page inférieure ainsi que dans la forme 2 bits. Ceci peut être effectué par une machine état et des verrous de données dans la zone d'amplificateur de détection sur la mémoire, sans utiliser le contrôleur..
PCT/US2006/011232 2005-04-01 2006-03-27 Memoire a etats multiples possedant une recuperation de donnees apres un echec de programme Ceased WO2006107651A1 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US11/097,517 US7158421B2 (en) 2005-04-01 2005-04-01 Use of data latches in multi-phase programming of non-volatile memories
US11/097,517 2005-04-01
US11/304,960 2005-12-14
US11/304,783 US7345928B2 (en) 2004-12-14 2005-12-14 Data recovery methods in multi-state memory after program fail
US11/304,960 US7420847B2 (en) 2004-12-14 2005-12-14 Multi-state memory having data recovery after program fail
US11/304,783 2005-12-14

Publications (1)

Publication Number Publication Date
WO2006107651A1 true WO2006107651A1 (fr) 2006-10-12

Family

ID=36699115

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/011232 Ceased WO2006107651A1 (fr) 2005-04-01 2006-03-27 Memoire a etats multiples possedant une recuperation de donnees apres un echec de programme

Country Status (1)

Country Link
WO (1) WO2006107651A1 (fr)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009006513A1 (fr) * 2007-07-03 2009-01-08 Sandisk Corporation Vérification de programme brute/fine dans une mémoire non volatile utilisant différents niveaux de référence pour une meilleure détection
WO2009035834A2 (fr) 2007-09-07 2009-03-19 Sandisk Corporation Mémoire non volatile et procédé pour une distribution pseudo-aléatoire sur puce de données à l'intérieur d'une page et entre des pages
US7508715B2 (en) 2007-07-03 2009-03-24 Sandisk Corporation Coarse/fine program verification in non-volatile memory using different reference levels for improved sensing
US7599224B2 (en) 2007-07-03 2009-10-06 Sandisk Corporation Systems for coarse/fine program verification in non-volatile memory using different reference levels for improved sensing
US7606966B2 (en) 2006-09-08 2009-10-20 Sandisk Corporation Methods in a pseudo random and command driven bit compensation for the cycling effects in flash memory
US7734861B2 (en) 2006-09-08 2010-06-08 Sandisk Corporation Pseudo random and command driven bit compensation for the cycling effects in flash memory
WO2014039129A1 (fr) * 2012-09-06 2014-03-13 SanDisk Technologies, Inc. Préservation de données d'écriture pour dispositif de stockage non volatil
US8843693B2 (en) 2011-05-17 2014-09-23 SanDisk Technologies, Inc. Non-volatile memory and method with improved data scrambling
US20170038985A1 (en) * 2013-03-14 2017-02-09 Seagate Technology Llc Nonvolatile memory data recovery after power failure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030137888A1 (en) * 2002-01-18 2003-07-24 Jian Chen Techniques of recovering data from memory cells affected by field coupling with adjacent memory cells
US20040160829A1 (en) * 1998-02-16 2004-08-19 Tetsuya Tsujikawa Semiconductor, memory card, and data processing system
US20040210729A1 (en) * 2001-07-23 2004-10-21 Renesas Technology Corp. Nonvolatile memory

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040160829A1 (en) * 1998-02-16 2004-08-19 Tetsuya Tsujikawa Semiconductor, memory card, and data processing system
US20040210729A1 (en) * 2001-07-23 2004-10-21 Renesas Technology Corp. Nonvolatile memory
US20030137888A1 (en) * 2002-01-18 2003-07-24 Jian Chen Techniques of recovering data from memory cells affected by field coupling with adjacent memory cells

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7606966B2 (en) 2006-09-08 2009-10-20 Sandisk Corporation Methods in a pseudo random and command driven bit compensation for the cycling effects in flash memory
US7734861B2 (en) 2006-09-08 2010-06-08 Sandisk Corporation Pseudo random and command driven bit compensation for the cycling effects in flash memory
US7508715B2 (en) 2007-07-03 2009-03-24 Sandisk Corporation Coarse/fine program verification in non-volatile memory using different reference levels for improved sensing
WO2009006513A1 (fr) * 2007-07-03 2009-01-08 Sandisk Corporation Vérification de programme brute/fine dans une mémoire non volatile utilisant différents niveaux de référence pour une meilleure détection
US7599224B2 (en) 2007-07-03 2009-10-06 Sandisk Corporation Systems for coarse/fine program verification in non-volatile memory using different reference levels for improved sensing
WO2009035834A3 (fr) * 2007-09-07 2009-05-22 Sandisk Corp Mémoire non volatile et procédé pour une distribution pseudo-aléatoire sur puce de données à l'intérieur d'une page et entre des pages
WO2009035834A2 (fr) 2007-09-07 2009-03-19 Sandisk Corporation Mémoire non volatile et procédé pour une distribution pseudo-aléatoire sur puce de données à l'intérieur d'une page et entre des pages
US7885112B2 (en) 2007-09-07 2011-02-08 Sandisk Corporation Nonvolatile memory and method for on-chip pseudo-randomization of data within a page and between pages
US8843693B2 (en) 2011-05-17 2014-09-23 SanDisk Technologies, Inc. Non-volatile memory and method with improved data scrambling
WO2014039129A1 (fr) * 2012-09-06 2014-03-13 SanDisk Technologies, Inc. Préservation de données d'écriture pour dispositif de stockage non volatil
US9135989B2 (en) 2012-09-06 2015-09-15 Sandisk Technologies Inc. Write data preservation for non-volatile storage
US20170038985A1 (en) * 2013-03-14 2017-02-09 Seagate Technology Llc Nonvolatile memory data recovery after power failure
US10048879B2 (en) * 2013-03-14 2018-08-14 Seagate Technology Llc Nonvolatile memory recovery after power failure during write operations or erase operations

Similar Documents

Publication Publication Date Title
US7345928B2 (en) Data recovery methods in multi-state memory after program fail
US7420847B2 (en) Multi-state memory having data recovery after program fail
EP1869681B1 (fr) Utilisation de verrouillages de donnees dans la programmation a phases multiples de memoires non volatiles
EP1864289B1 (fr) Utilisation de verrous de donnees dans des operations de cache de memoire non volatile
US7885112B2 (en) Nonvolatile memory and method for on-chip pseudo-randomization of data within a page and between pages
US8154923B2 (en) Non-volatile memory and method with power-saving read and program-verify operations
US7310255B2 (en) Non-volatile memory with improved program-verify operations
CN101512668B (zh) 对于快闪存储器中的循环效应的伪随机及命令驱动位补偿及其方法
EP2070090B1 (fr) Compensation de bits pseudo-aléatoire et dirigée par la commande pour les effets de cycle en mémoire flash et ses procédés
US7606966B2 (en) Methods in a pseudo random and command driven bit compensation for the cycling effects in flash memory
WO2006107651A1 (fr) Memoire a etats multiples possedant une recuperation de donnees apres un echec de programme
TWI410974B (zh) 於編程失敗後具有資料回復之複數狀態記憶體

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: DE

NENP Non-entry into the national phase

Ref country code: RU

122 Ep: pct application non-entry in european phase

Ref document number: 06739797

Country of ref document: EP

Kind code of ref document: A1