WO2006113444A2 - Système et procédé d'impression numérique à semi-conducteurs - Google Patents

Système et procédé d'impression numérique à semi-conducteurs Download PDF

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Publication number
WO2006113444A2
WO2006113444A2 PCT/US2006/014090 US2006014090W WO2006113444A2 WO 2006113444 A2 WO2006113444 A2 WO 2006113444A2 US 2006014090 W US2006014090 W US 2006014090W WO 2006113444 A2 WO2006113444 A2 WO 2006113444A2
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Prior art keywords
memory
printing
image
print
substrate
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WO2006113444A3 (fr
Inventor
Nandakumar Vaidyanathan
Ravi Subrahmanyan
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Individual
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/015—Ink jet characterised by the jet generation process
    • B41J2/04—Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/06—Ink jet characterised by the jet generation process generating single droplets or particles on demand by electric or magnetic field

Definitions

  • the present invention generally relates to semiconductor techniques for printing.
  • PC Personal Computer
  • Drop on Demand Ink Jet technology
  • the image to be printed is constructed on an appropriate printing medium such as paper, plastic, textiles, printing plates and even silicon based substrates using print heads which eject drops of ink at the appropriate location on the printing medium. Since the ejection of ink occurs at the time the image is being printed this is often called “Drop on Demand” printing.
  • the ink ejection mechanism may be controlled using piezo electric mechanisms or thermal mechanisms (ink jet or bubble jet).
  • Continuous Ink-Jetting Method Another kind of commercial printing that is carried out using the ink-jetting technique is called the Continuous Ink-Jetting Method.
  • a continuous jet of ink is squirted through space, and using electrostatic deflector plates, the ink is selectively directed at the appropriate medium through a mesh, leading to deposition of dots to create patterns.
  • the unused ink is directed through another channel and is recycled. This is the basis of the Continuous Ink Jetting technique and this process uses both charged and uncharged inks.
  • rnagnetography Another printing technology used in the commercial printing world, called rnagnetography, is similar to electrophotography, but uses magnetic fields instead of electrostatic fields to propel charges.
  • Lithography involves a plate or an intermediate medium, on which the image to be printed is either exposed or engraved using a variety of techniques such as photography, laser ablation, thermal ablation and more recently ink jet based techniques.
  • the areas of the printing plate have areas which accept ink (olephilic - oil loving) and areas, which accept water (hydrophiiic). In general, the oil loving areas of the image do not accept water and the water loving areas do not accept ink.
  • the lithographic printing ink is an emulsion of pigments and water
  • the ink and water selectively migrate to their respective locations on the printing plates. Once the ink and water have migrated to their respective locations, it is then transferred to the medium being printed or to an intermediate cylinder called an offset cylinder and from the offset cylinder the image is deposited on the final medium.
  • ink jet based printers are quite slow.
  • There are high costs associated with electrostatic printing processes for commercial printing due to low throughput and inability to provide more than a certain number of copies (40,000 copies with current technology) on an electro-photography based machine, before the photoconductor drum is rendered useless for any other more reproduction.
  • primary costs include use of expensive printing plates or spools, and high costs for recycling and disposal of environmentally unfriendly chemicals.
  • the imaging or pre-imaging equipment used in the commercial printing world can be quite large and bulky.
  • a digital printing system uses individual memory cells within memory dies mounted on a substrate to attract or repel ink in order to produce an image. There is a dead space between adjacent individual memory cells and also between adjacent memory dies. By staggering the location of the memory dies on two or more substrates the dead spaces may be eliminated or minimized. In addition, staggering the location of the memory dies on the substrates allows for backup operations in the event that a primary memory cell fails and for resolution stepping of the printed image. The staggering of the location of the memory dies may be accomplished by an offset mapping of the locations of the memory dies between the two or more substrates. The offset mapping may be a translational mapping, a rotational mapping, or a combination of translation and rotational mappings.
  • FIGS. 1a-1b show an insulated conductive layer or medium in a fiat configuration.
  • FIGS. 1c-1d show an insulated conductive layer or medium in a cylindrical configuration.
  • FIGS. 2a-2b show how the memory layer is superimposed on the insulated conductive layer.
  • FIG. 3 shows an enlarged view of a memory cell.
  • FIGS. 4a-4b show memory cells overlaid on the insulated conductive layer for a cylindrical configuration of the print engine.
  • FiG. 5 shows an exploded view of how the different layers of the Print Engine are assembled.
  • FIG. 6 shows the cross sectional view of a single memory cell coupled to a single conductive pad.
  • FiGS. 7a-7b show a cutaway and top views of an insulated conductive layer (and memory layer)/ the print engine.
  • FIGS. 8a-8b show an insulated conductive layer in a flat geometric configuration.
  • FIGS. 9a-9b show an alternative embodiment of the present invention utilizing organic polymers to form memory.
  • FIG. 10 shows how an image can be mapped onto memory locations.
  • FIG. 11a is a block diagram of an exemplary semiconductor memory.
  • FIGS. 11 b-11 G show one storage location of the, memory.
  • FIGS. 12a-12b illustrate various embodiments of how individual memory cells may be laid out.
  • FIG. 13 shows an exemplary single ended storage ceil.
  • FIG. 14 is a cross sectional view of a semiconductor layout showing how a micro-via may be used to connect the transistors of a memory element to the surface of the chip.
  • FiG. 15 shows how an array of chips can be connected to create a large array.
  • FIG. 16 is a block diagram of how each chip can be designed to have an interface element.
  • FIG. 17 illustrates an embodiment wherein each chip has a wireless link.
  • FiGS. 18a-18b illustrate an exemplary embodiment of a printing system.
  • FIGS. 19a-19b illustrate methods of adapting a traditionally flat chip onto a curved printing surface.
  • FIG. 20 shows how a single-ended, thin film print element can be used.
  • FIG. 21 shows the connection of a storage array to a thin film substrate.
  • Figs. 22a and 22b depict the top and bottom, respectively, of a plurality of memory chips disposed on a substrate.
  • Figs. 23a and 23b depict the distribution of memory chips on a substrate formed into a cylindrical print drum.
  • Fig. 24 depicts a flat substrate that includes an array of memory dies that are positioned in a staggered configuration.
  • Figs. 25a and 25b depict a translational mapping in the printel space among a plurality of substrates and the composite printel space, respectively.
  • Figs. 26a and 26b depict a rotational mapping in the printel space among a plurality of substrates and the composite printel space, respectively.
  • Fig. 27 depicts an image that is de-composed and spatially mapped into printe! space and re-composed in the media space.
  • An electronic stored image based scheme which permits the digital printing elements to print a digitally stored image onto any medium. This is accomplished by using a semiconductor memory-based scheme in which an image is stored in an electronic memory with each digital printing element occupying one memory location. Since information is stored in memory as a voltage, by directly coupling the memory location to a conductive element, the stored voltage can be used to directly control whether or not conductive toner based inks are attracted to that conductive element.
  • the system provides for a printing drum comprising a semiconductor memory.
  • the semiconductor memory uses decoding elements to allow access to each of many storage locations without requiring an individual connection to each location. The system therefore utilizes the semiconductor memory structure to spatially map a digitally stored bit of data (e.g., 0 or 1) to a physical location.
  • the semiconductor printing system can also be composed of a flat semiconductor memory panel, over which a system of charged and uncharged rollers can translate successively, and selectively transfer charged ink (toner) to and from the semiconductor memory panel to a printing medium.
  • the digital printing engine uses low voltage electrostatics to direct toners or other conductive printing inks to its surface. This print engine does not have any intervening consumable media such as a printing plate.
  • the print engine of the disclosed embodiment comprises an insulated conductive layer and a semiconductor memory layer.
  • FIG. 1a shows an insulated conductive layer in a flat configuration.
  • FIG. Ib is an enlarged view of the insulated conductive layer of FIG. 1a.
  • the insulated conductive layer comprises an insulating medium 11 having a top surface 10 and a bottom surface 12, a plurality of micro-vias 14 that connect the top and bottom surfaces of the insulator, conductive pads 16 on the top, and conductive pads 18 on the bottom surfaces of the insulator.
  • the insulating medium can be either flexible or rigid. Typical choices for the insulating medium include, but are not limited to: plastics such as nyion, delrin, ABS, ceramics or even metais such as aluminum or steel that can be ciadded by a polymeric or ceramic insulating layer. The choice of the insulator depends on the application.
  • the insulating medium has very small holes (approximately 20 microns in diameter) drilled through its thickness. The number of micro holes are determined by the dots per inch of printing tat is required from the specific printing application.
  • the micro-vias 14 are through holes filled with a conductor. These holes can be drilled using excimer lasers or by chemical means. As future technologies become available, other machining methods can be used to drill these through holes, or micro vias 14.
  • the micro-vias 14 are filled with an appropriate conductor such as copper or silver or gold, or any appropriately solidifying conductive paste, and they terminate at both the top 10 and bottom 12 surfaces with contact pads 16 and 18.
  • the contact pads 16 and 18 can be circular or rectangular in shape. Thus the contact pads 16 and 18 help electrically connect the top and the bottom surface of the insulated conductor.
  • the thickness of the insulating medium is determined by whether the insulator is used as a rigid medium or as a flexible medium. In some cases, the insulating conducting pad can be made flexible and can be superimposed on a rigid flat plate and thus have a higher flexural rigidity. Typical thickness of the insulated medium can range from a few thousand micro inches to a few inches.
  • the insulated medium can be either flexible or rigid. Both flat and cylindrical geometries are possible in the flexible or rigid configuration. The type of application, namely flexible or rigid configuration, determines the thickness of the insulated conductive layer. [0059] FIGS.
  • 1c-1d illustrate an insulated conductive layer in a cylindrical configuration.
  • the cylindrical configuration has an inner surface 13 and an outer surface 15, with micro-vias 14 and contact pads 16 and 18 at the end of each micro-via, at the inner 13 and outer 15 surface.
  • the semiconductor memory layer contains the "brains" of the printing engine.
  • Memory can be manufactured using several different technologies, such as conventional silicon based semiconductors, organic semiconductors that use organic materials for semi-conducting purposes, or magneto-electronic materials that can be fashioned into memory cells.
  • conventional silicon based semiconductors such as silicon based semiconductors, organic semiconductors that use organic materials for semi-conducting purposes, or magneto-electronic materials that can be fashioned into memory cells.
  • the print engine construction based on conventional silicon based semiconductors and organic semiconductors are now described.
  • FIGS. 2a-2b illustrate a typical memory layer 20 as it is superimposed on the insulated conductive layer 22.
  • the memory layer 20 is generally made up of an array of individual memory cells 24.
  • Memory is made of transistors and can be directly patterned over the insulated conducting layer as shown in FIGS. 1a and 1c, using different techniques. Memory can be made using traditional silicon wafer based semiconductors or organic semiconductors which have recently been developed.
  • FIG. 3 shows an enlarged view of a memory cell.
  • an asymmetrically conductive adhesive also known as anisotropic conductive adhesive
  • anisotropic conductive adhesive is used to couple the memory cell layer to the conductive pads on the insulated conductive layer.
  • FIGS. 4a-4b show memory cells overlaid on the insulated conductive layer for a cylindrical configuration of the print engine.
  • the inner contact pads are in conformal contact with the asymmetrically conductive adhesive and are not visible in this picture.
  • FIG. 4b is an enlarged view of the cylindrical configuration of the print engine.
  • FiG. 5 shows an exploded view of how the different layers of the Print Engine are assembled.
  • the anisotropic conductive adhesive ACA
  • ACA anisotropic conductive adhesive
  • F!G. 6 shows the cross sectional view of a single memory cell coupled to a single conductive pad.
  • the insulated conductive layer 61 is shown with micro-via 14 and top and bottom conductive pads 16 and 18.
  • the insulated conductive layer is coupled to memory layer 20 using an asymmetrically conductive adhesive 52.
  • FIGS. 2a through 6 show a flexible memory structure coupled to an insulated conductive layer with conductive pads.
  • FlG. 7a shows a cutaway view of an insulated conductive layer containing micro-vias in a cylindrical configuration, coupled to packaged integrated memory chips. Part of the insulated conductive layer has been removed to show the asymmetrically conductive adhesive layer, and the location of the integrated memory chips. In this embodiment, the memory locations in the packaged integrated memory chips are directly coupled to the conductive pads on the cylinder using asymmetrically conductive adhesives.
  • F!G. 7b illustrates the top view of an insulated conductive layer coupled to a packaged integrated memory chip.
  • the dead space that exists between individual memory chips is also visible. These "dead spaces”, do not contain any printing elements. By staggering the chip locations between two or more cylinders, it is possible to eliminate all dead space and evenly provide memory locations to print continuously in a linear fashion.
  • FIGS. 8a-8b show an insulated conductive layer in a flat geometric configuration.
  • the top surface is shown, and in figure 8a the bottom surface is shown.
  • the integrated memory chip is attached to the bottom surface using different methods.
  • One method is to use an asymmetrically conductive adhesive to bond the chip to the conductive micro-vias.
  • the top surface generally represents the surface that will attract the ink.
  • the bottom surface is generally where the memory chips or memory circuits are attached.
  • the insulating layer isolates and provides mechanical isolation and electrical isolation between the chips and the ink receiving layers.
  • the functionality of the memory elements is the same.
  • the individual memory cells carry a voltage, and the voltage, when coupled to the conductive pads, is capable of attracting charged toner. What the memory circuits help avoid is the need to wire each conductive pad individually by an independent wire, which carries a voltage through it.
  • ACA asymmetrically conductive adhesive layer
  • FIG. 9a shows one such potential structure, in a flat format. This is based on memory developed by Thinfilms, inc. of Sweden.
  • FIG. 9b shows an enlarged view of the structure described in FIG. 9a. This memory structure overlaid on the insulated conductive layer is also possible in a cylindrical configuration.
  • FiG. 11a is a block diagram of an exemplary semiconductor memory, which can be on a single integrated chip (IC).
  • the address bus is used to access each memory location. Since the address is specified using a binary code, the number of connections to the chip needed to access many locations is log 2 (n) where n is the number of memory locations. For example, for a standard 8'5" by 11" page at 300 dpi, which has 8,415,000 print locations, only 24 address bits are required to access all locations.
  • the integrated chip has row (105) and column (110) decoding circuits, along with global decoding and timing circuits (120).
  • the storage locations are grouped in arrays (100), with channels (125) in between the arrays.
  • the channels carry power, ground, and un-decoded or partially decoded address lines and other signals.
  • FIGS, 12a and 12b illustrate an exemplary single storage location in the memory.
  • each element is designed to be as small as possible in order to increase density
  • these elements can be larger. This is because the pitch required for printing is much larger than the pitch achievable by semiconductor memories.
  • a 300 dpi (dots per inch) image requires a dot pitch of approximately 85 micrometers (urn), which is much larger than the pitch of storage elements or memory cells in a memory made in a modern semiconductor process.
  • the pitch of the conductive elements at the surface is coarse, while the pitch at which the transistor elements, which form the memory in the semiconductor substrate, is fine.
  • the transistor elements can therefore be larger, which makes them more robust and increases reliability and manufacturing yield.
  • the unused spacing can be used to perform local decoding which increases the uniformity of the memory array by moving some of the peripheral circuitry within the array itself, and also by making room for power, ground, and signal channels in between the elements.
  • FIG. 11b is a storage element used in a semiconductor memory. This element is generally optimized to be as small as possible in order to maximize the storage density.
  • FIG. 11b shows a diagram of a typical 6-transistor static memory (SRAM) ceil.
  • Inverters 200 and 201 are cross-coupled and connected to bit lines 241 and 241 via access gates 210 and 211.
  • the nodes 221 and 222 at the outputs of the inverters are the charge storage nodes.
  • the access gates are driven by the word line 230.
  • the access gates 210 and 211 are usually single NMOS transistors.
  • the access gates 210 and 211 may be transmission gates rather than single NMOS transistors, which can improve noise immunity and cell robustness.
  • the charge stored on a typical SRAM storage node (221 and 222) is small and so the node cannot be connected directly to the printing surface.
  • an additional inverter 250 is used to isolate the storage node 222 from the printing surface.
  • the output 251 of the inverter 250 is coupled using the metal via to the printing surface.
  • FIGS. 12a-12b shows how the relaxed pitch can be used to make the array more uniform;
  • FIG. 12a shows the layout of a conventional semiconductor memory.
  • the array consists of a grid of word lines (305 and 310) and bit line pairs (315, 320).
  • Memory cells 325 are placed at the intersections of the word lines and bit iine pairs. Since the aim is to maximize storage by optimizing density, the ceils are made as small as possible and packed as close to each other as possible. Therefore, the spacing between word lines 305 & 310 is minimized, as is the spacing between the bit line pairs 315 & 320, and these are generally just as much as is needed to fit the storage cell at the intersection. So, all decoding circuits which decode the incoming address to provide signals for the word and bit lines are placed at the periphery of the array, as shown in FIG. 11a.
  • FIG. 12b illustrates an embodiment whereby the decoding circuits are located with each memory cell, as opposed to outside of the array of memory ceils.
  • FiG. 12b shows how wires and decoding circuits can be interspersed with the storage elements of the array when the pitch is relaxed. Since the digital printing element does not have to be as densely packed as a semiconductor memory and does not have to operate as fast as a conventional memory, two modifications can be made. One, the cell (375) can be made single ended (i.e. it can use only one bit iine (365, 370) instead of a pair of complementary bit lines), and two, the spacing between word lines (355, 360) and bit lines (365, 370) can be larger than in a conventional memory. Therefore additional decoding and buffering circuits 380 can be placed in the area available at the word and bit line intersections, in order to reduce the non-uniformity caused by having to place all the decoding circuits at the edges of the array.
  • FIG. 13 One example of a single ended storage cell is shown in the circuit of a conventional master slave latch shown in FIG. 13. Many such circuits are known to those well versed in the art and can be used for this purpose.
  • FIG. 14 is a cross sectional view of a semiconductor layout and shows how a micro-via may be used to connect the transistors of a memory element to the surface of the chip to drive a print element.
  • FIG. 14 shows the typical via structure used to connect the transistors to the printing surface.
  • Transistors 410 and 420 are shown in a silicon wafer 415.
  • the p-type transistor 420 is shown in an n-well 425, as is typica! in CMOS technology.
  • the transistor 420 has a source 431 and a drain 432 and a gate 433.
  • the source 431 is connected via the metal contact and metal layer 441 as appropriate for the circuit (details not shown here).
  • the n-type transistor is constructed directly in the substrate 415 and has a source 411 and a drain 412 and a gate 413.
  • the source 411 is connected as appropriate using a contact and metal layer 442.
  • the two transistors are connected using contacts and metal layer 443.
  • a dielectric layer 450 insulates metal layer 1 (441 and 442) from higher metal layers.
  • a via and metal 2 layer 460 are used to connect down to metal layer 1 and the connection between transistors 410 and 420. Other connections (not shown) may also exist on this metal layer. There may be more meta ⁇ layers (layer 3, layer 4) etc as required by the technology used to fabricate the circuit.
  • a via 475 is used to connect the highest layer to the surface 480 of the chip.
  • Dielectric layers 470, 465, etc are used to insulate the circuit at the lower levels from the surface.
  • the topmost via 475 is finally connected to the printing surface using various means as discussed elsewhere in the document.
  • FIG. 15 shows how an array of chips 500 can be connected to create a iarge array.
  • a communication bus scheme is proposed in which a bus 500/505 is used to connect ail the chips 500.
  • An arbitration and communication protocol will be used to allow each chip to be loaded with its portion of the image. Since image loading time is not a constraint in this application, it is possible to optimize the protocol for ease of communication and low wire-count by using a low bandwidth protocol.
  • Busses 500 and 505 are used to connect the cells. These busses carry address, data, power, ground, and other signals, and are designed to reduce the wiring needed between the chips.
  • FIG. 16 is a block diagram of how each chip can be designed to have an interface element that handles the protocol, coupled with the image storage function described earlier.
  • the digital printing element array 600 is connected to conventional decoding circuits 610 that may be used in one chip.
  • a communications controller 605 listens to the narrow bus 620 that connects the chips in an array.
  • Communications controller 605 listens to the protocol on the bus 620 and recreates address and data information for the chip, which it passes to the decoding circuit 610 along a bus which is wider than 620.
  • the decoding circuit 610 finishes the decoding and drives the array 600 along a bus of appropriate (as much as needed) width, as shown in the diagram,
  • each array can be made into a sealed module with a unique address and only power and ground connections made externally. This can be used to control access to each module, and provide tracking and access control by including encryption and authentication in the communication protocol.
  • a wireless link it is also possible to use some other physical connection that is made temporarily to download the image into the module, after which the connection is broken.
  • the block 705 can be a wireless communications processor, which uses an antenna 720 as its input bus for data, address, and other information.
  • the antenna 720 can be built on to the chip 715, or can be an external metal trace that is connected to the chip. In this case, the bus 725 would only carry power and ground to the chips 715 in an array.
  • the print engine is composed of the semiconductor memory layer overlaid on the insulated conductive layer with a one to one correspondence of each memory ceil with the conductive pad on the insulated layer.
  • This combination of the memory ceil with a conductive location is called a digital printing element.
  • the memory storage array is not contiguous even within a chip.
  • This scheme will also provide a built-in redundancy mechanism by which faiied print locations on one cylinder or surface can be compensated by a corresponding location on the other surface.
  • the image to be printed is first stored in a computer as a binary bit pattern, physicaliy corresponding to a 1 or a 0 depending upon the presence or absence of a dot. From the computer, the memory can be directly downloaded to the memory location on a bit by bit basis, corresponding to the pixel value of the image stored. Thus there is a spatial map of the data corresponding to the image and the physical memory cell location. See FIG. 11a for a pictorial representation of the memory map. Thus each memory cell location will contain a digitally stored "1" or a "0" depending on whether the pixel in the original image is turned on or off.
  • the print image is stored electronically and there is an electronic map of how each image digital printing element maps on to a physical location, the print image can be aligned very easily by adjusting the specific locations in which individual image bits are stored. Physical alignment of the paper to the cylinder is not needed, and alignment can be done electronically by shifting or rotating the image, as it is stored in the print array. This problem overcomes alignment and registration of images and colors that are found in traditional lithography based printing presses.
  • FIG. 18a shows how the print engine can be configured with an offset cylinder and inking cylinders to transfer charged ink from a source to the final medium (Paper or plastic or metal) in sheet or continuous web form.
  • a source Paper or plastic or metal
  • the electrical connections, and mechanical support structures have been omitted.
  • the ink is transferred from the inking cylinders via electrostatic attraction to the print engine.
  • the ink cylinder will carry a charge that is opposite to the charge carried by the locations on the print engine, which have a digitally stored charge on them. Thus the toner ink will have the same charge as the ink cylinder.
  • FIG. 18a shows a perspective view from a different viewing angle with more details of the internal structure of the print engine.
  • F!G. 18b shows another perspective viewing angle of the print engine and the associated components. In this perspective viewing angle the contact pads on the print engine are also visible.
  • the inking cylinders can all carry black ink, in which case the printer will be configured to print in monochrome.
  • four stations each identical to the one configured in FIG. 18a can be arranged in series such that the medium such as paper or plastic or metal can successively pass through each station and acquire the component of color from each station.
  • a subtractive color printing scheme employing cyan, magenta yellow and black colors could be used in each of the stations respectively to generate the composite color density required by the final image.
  • a software based color separation scheme that will separate the color pixels from each image to be printed will be used to download the pixels into each of the print engines.
  • additional colors can also be used for highlighting and other glossy effects. An extra print engine configuration in series with the four colors would be necessary in such a situation.
  • FIG. 19a some methods of adapting the flat integrated chip 805 to a curved printing surface 800 are shown.
  • the chip has vias 810 that are connected to the storage elements and bring the stored voltage to the surface as discussed earlier.
  • a directionally conductive adhesive 815 is used to connect the vias at the chip surface to the curved printing surface. This adhesive serves as a vertical connection as well as a strain relief layer.
  • FIG. 19b shows a grid of columns 820 which are used to connect the chip surface to the printing layer. These columns are typically made of metal, though other materials may be used.
  • An insulating material 825 can be used to fill in the gaps between the columns, and this material also acts as a support and strain relief layer.
  • FIG. 20 shows how a single-ended, larger-area thin-film print element 925 can be used.
  • the inset shows the element 925, which takes in decoded row and column signals, a clock signal, and Vdd and ground. The arrangement of these elements into an array is also shown, and is similar to the conventional memory layout.
  • the grid consists of coarse row and column decoding circuits 950 and 960, which decode the incoming addresses into rows (955) and columns (970).
  • a global dock connection 975 is sent to all the storage elements 925.
  • the storage elements 925 are placed at the intersection of the decoded row and column lines, and additional decoding circuits may also be placed there as discussed earlier.
  • the address and data information for the chip is brought in on a bus 980.
  • FIG. 13 shows the circuit of a conventional latch circuit, which is traditionally used in IC design, it consists of a transmission gate 905, an inverter 910, a clocked inverter 915, and these are connected to form a storage element.
  • a transmission gate 905 an inverter 910, a clocked inverter 915, and these are connected to form a storage element.
  • Such an element may be more easily created using thin-film-transistor technology, since it is more robust because it can be made using larger transistors.
  • FIG. 21 shows the connection of a storage array on a thin-film substrate 1010 to a conventional silicon chip 1020 using a flexible bus 1015.
  • the flexible thin-film substrate can be made conformal to the printing surface 1005.
  • Figs. 22a and 22b depict top and bottom views of a plurality of memory chips assembled on a substrate.
  • a substrate 2202 has mounted thereon a plurality of memory dies 2204 having conductive interconnections 2206 therebetween.
  • the memory dies 2204 include a plurality of printing locations 2210 that correspond to individual memory cells within the die.
  • each memory cell is coupled to a first conductive pad that is electrically coupled to a second conductive pad disposed on the printing surface of the print engine.
  • the second conductive pad takes on the charge or voltage of the first conductive pad and attracts or repels ink depending upon the type of ink being used.
  • Figs. 22a and 22b depict top and bottom views of a plurality of memory chips assembled on a substrate.
  • a substrate 2202 has mounted thereon a plurality of memory dies 2204 having conductive interconnections 2206 therebetween.
  • the memory dies 2204 include a plurality of printing locations 2210 that correspond to individual memory cells within the die.
  • the memory dies 2204 are arranged in a rectilinear manner such that between each row and column of memory dies dead space 2208 exists between each adjacent memory die that, at least for the corresponding substrate is not printable.
  • the memory cells on each die are also configured in a rectilinear fashion. Accordingly, there is also dead space 2212 between adjacent memory cells that, at least for the individual memory die is not printable.
  • Figs. 23a and 23b depict an assembly of memory dies formed on a substrate that is shaped to form a cylindrical print drum.
  • the substrate 2302 is formed into a cylindrical print drum that includes a plurality of memory dies 2304 that are interconnected via conductive interconnects 2306.
  • dead space 2312 exists between adjacent memory cells in each memory die 2304.
  • the dead space 2208 and 2308 in flat or curved substrates, respectively, is not an issue and the memory dies can be placed in the rectilinear configuration and provide adequate printing resolution.
  • the die layout on a substrate is not a regular rectilinear configuration and the positions of the various memory dies are vaired in order to reduce the the number of dead spaces within the substrated and to reduce the size of any dead spaces that may remain.
  • Fig. 24 depicts a flat substrate 2402 that includes an array of memory dies 2404 that are positioned in a staggered configuration such that the dead spaces 2406 are limited in size to the areas between adjacent memory dies and do not extend for the entire row and columns between adjacent memory dies as in Figs.
  • the size of the dead spaces has been reduced.
  • the flat substrate 2402 could be formed into a cylindrical print drum or other printing surface and the dead spaces 2406 would also be limited in those configurations.
  • the memory die pattern can be repeated on multiple substrates.
  • Each substrate may be flat or formed into a shape such as a cylindrical print drum or other desired shape. In this embodiment, what ever the shape of the substrates, the different memory locations on the different substrates all overlap with one another.
  • Fig. 25a depicts an offset mapping that is a translational mapping in the printel space among a plurality of substrates 2502a, 2502b, and 2502c on which a 4x4 array of memory dies are arranged in a regular rectilinear configuration.
  • the memory dies 2504b on substrate 2502b are slightly offset by ⁇ x and ⁇ y when compared to the position of the corresponding memory dies 2504a on substrate 2502a.
  • the memory dies 2504c on substrate 2502c are slightly offset by ⁇ x and ⁇ y when compared to the position of the corresponding memory dies 2504b on substrate 2502b.
  • the use of translational mapping for the three combination of the three substrates forms a printel image depicted in Fig, 25b that shows the overall coverage of the composite printel image.
  • the combination of the three substrates 25a-c work together to provide contiguous spatial coverage of the area.
  • 800 dpi cells are positioned in a staggered format
  • no single substrate will have to have the ultimate printel density but, rather, each can have a much lower printel density.
  • a plurality of 800 dpi substrates may be formed to provide 1600 dpi or 2400 dpi printei densities.
  • Fig. 26 depicts an offset mapping that is a rotational mapping of three substrates 2602a, 2602b, and 2602c.
  • substrate 2602b is rotated when compared to substrate 2602a
  • substrate 2602c is rotated with respect to substrate 2602b.
  • the composite printel image is depicted in Fig 26b.
  • the combination of the three substrates 26a-c work together to provide contiguous spatial coverage of the area.
  • translational mapping may be used to provide redundant memory cell locations that can be used to provide backup operations in the event that a primary memory cell fails.
  • the use of translational mapping, rotational mapping, or a combination of both may be used to provide resolution stepping of an image.
  • an image is composed of individual dots and with the use of resolution stepping, the image may be printed at various levels of resolution. For example, depending on the configurations of each printing substrate and the number of substrates, an image that was originally 1000 dpi may be able to be printed from 100 dpi to over 2000 dpi in varying steps of resolution. Thus, depending on the system requirements, the printing time and cost required for an image to be printed may be reduced via the resolution stepping.
  • Fig. 27 depicts an original image that is de-composed and spatially mapped into printel space and re-composed in the media space.
  • the printel space refers to the plurality of substrates and memory dies and cell locations on each substrate.
  • the media space is the actual printed image.
  • This de-composition of the image into the printel space allows the number of cells used to print the image to be determined based on the areal density of the image in terms of the number of dots per inch and the die size.
  • a minimum resolution value of one-half the final resolution on each printel bank or substrate allows for the doubling of the resolution when a plurality of such printel banks are used to form the printel space.

Landscapes

  • Facsimile Scanning Arrangements (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un système d'impression numérique qui utilise des cellules de mémoire individuelles dans des puces de mémoire montées sur un substrat pour attirer ou repousser l'encre afin de produire une image. Un espace mort est prévu entre des cellules de mémoire individuelles adjacentes, et aussi entre des puces de mémoire adjacentes. L'empilement des puces de mémoire sur deux ou davantage de substrats permet de supprimer ou de réduire les espaces morts. De plus, l'empilement des puces de mémoire sur les substrats permet de mettre en oeuvre des opérations de sauvegarde en cas de défaillance d'une cellule de mémoire primaire, et de reproduire l'image imprimée avec divers niveaux de résolution.
PCT/US2006/014090 2005-04-13 2006-04-13 Système et procédé d'impression numérique à semi-conducteurs Ceased WO2006113444A2 (fr)

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Publication number Priority date Publication date Assignee Title
JPS57124367A (en) * 1981-01-26 1982-08-03 Canon Inc Image forming method and its device
NL8601376A (nl) * 1986-05-29 1987-12-16 Oce Nederland Bv Beeldvormingselement voor een elektrostatische drukinrichting, alsmede een drukinrichting waarin zulk een element wordt toegepast.
US5157423A (en) * 1991-05-08 1992-10-20 Cubital Ltd. Apparatus for pattern generation on a dielectric substrate
US6100909A (en) * 1998-03-02 2000-08-08 Xerox Corporation Matrix addressable array for digital xerography

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