WO2006129926A1 - Moule pour la fabrication de dispositifs semi-conducteurs et dispositif semi-conducteur fabrique a l'aide de celui-ci - Google Patents

Moule pour la fabrication de dispositifs semi-conducteurs et dispositif semi-conducteur fabrique a l'aide de celui-ci Download PDF

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Publication number
WO2006129926A1
WO2006129926A1 PCT/KR2006/001937 KR2006001937W WO2006129926A1 WO 2006129926 A1 WO2006129926 A1 WO 2006129926A1 KR 2006001937 W KR2006001937 W KR 2006001937W WO 2006129926 A1 WO2006129926 A1 WO 2006129926A1
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WO
WIPO (PCT)
Prior art keywords
mold
encapsulant
gates
cavities
semiconductor devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/KR2006/001937
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English (en)
Inventor
Dong Sun Kwak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TSP CO Ltd
Original Assignee
TSP CO Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020050047428A external-priority patent/KR100714884B1/ko
Priority claimed from KR1020060022126A external-priority patent/KR100640556B1/ko
Priority claimed from KR1020060039577A external-priority patent/KR100767194B1/ko
Application filed by TSP CO Ltd filed Critical TSP CO Ltd
Publication of WO2006129926A1 publication Critical patent/WO2006129926A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/016—Manufacture or treatment using moulds
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/481—Leadframes for devices being provided for in groups H10D8/00 - H10D48/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/014—Manufacture or treatment using batch processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • the present invention relates to a mold for manufacturing semiconductor devices and a semiconductor device manufactured using the same.
  • the present invention relates to a mold for manufacturing a semiconductor device, which is capable of saving the quantity of encapsulant to be used for manufacturing semiconductor device, suppressing the occurrence of voids in the encapsulant and the non- filling of the encapsulant, and preventing various defects from being caused in a trimming or sawing process, and a semiconductor device manufactured using such a mold.
  • a semiconductor device adapted to be capable of being mounted on a mother board or a main board includes a lead frame (or a circuit board), a semiconductor die mounted on the lead frame, plural conductive wires (or solder) for electrically interconnecting the lead frame and the semiconductor die, and an encapsulation part which is formed by encapsulant for encapsulating the lead frame, the semiconductor die, the conductive wires, etc. so as to protect them from the external environment.
  • such a semiconductor device is manufactured through a method including: a die-bonding process for mounting plural semiconductor dies on an array of plural lead frames; a wire-bonding process for electrically interconnecting the semiconductor dies and the lead frames, respectively; an encapsulating process for encapsulating the lead frames, the semiconductor dies, and the wires with encapsulant; and a trimming or sawing process for separating each semiconductor device from the lead frame array as a unit chip. That is, if only one semiconductor device is manufactured in each process, the yield is too low. Therefore, a large number of semiconductor devices are simultaneously manufactured by using an array of lead frames arranged in a form of strips.
  • FlG. 1 is a top plan view showing a number of semiconductor devices in a state of being encapsulated by a conventional mold for manufacturing semiconductor devices
  • FlG. 2 is an enlarged top plan view showing a part of FlG. Ia.
  • an array of plural lead frames 12' are provided in a strip form, and each lead frame is formed with an encapsulation part 15'in a predetermined shape.
  • one lead frame 12'and one encapsulation part 15' may be defined as a semiconductor device 10'.
  • Plural encapsulation parts 15' which are spaced from each other, may be arranged in two rows (or in more than two rows), and a small runner encapsulant 23'extends between the two rows of the encapsulation parts 15' wherein the small runner encapsulant part 23' which corresponds to a smaller of a mold. That is, the small runner encapsulant part 23' is formed as the encapsulant is cured in the small runner of a mold.
  • each of the encapsulation parts 15' is connected to the small runner encapsulant part 23' via a gate encapsulant part 24' which is formed as the encapsulant is cured in a gate of a mold, wherein the gate encapsulant part 24' is perpendicular to a corresponding encapsulation part 15'
  • the encapsulation parts 15' are formed by cavities, which are provided in the mold, the cavities, the gates, and the small runner are connected with each other.
  • reference numeral 21' denotes a ram pot encapsulant part, which corresponds to a ram pot of the mold
  • 22' denotes a large runner encapsulant part, which corresponds to a large runner of the mold.
  • arrows indicate the flow directions of encapsulant, wherein the encapsulant arrives at each of the gates and cavities through the ram pot, the large runner and the small runners.
  • the encapsulation parts that is, the semiconductor devices
  • the gate encapsulant parts 24' as well as the lead frames are cut by a punch or a sawing blade. Therefore, each of the finished semiconductor devices has a gate encapsulant part cutting trace (or an encapsulant part trace), which remains on each of the encapsulation parts 15'.
  • the encapsulation parts may be formed in a state in which the cavities in the mold are not insufficiently filled with encapsulant or a number of voids may be formed in the encapsulant. Furthermore, such voids subsequently absorb moisture or the like, whereby the moisture may be vaporized and cause the encapsulation part to be fractured when such a semiconductor device is laid under a high temperature condition.
  • the prior art has a problem in that a life span of a punch or a sawing blade which is used in a trimming or sawing process is reduced and the encapsulation part enclosing the semiconductor dies may also be fractured in the trimming or sawing process because the punch or sawing blade should remove the gate encapsulant parts as well as the lead frames.
  • an object of the present invention is to provide a mold for manufacturing semiconductor devices, which can reduce the quantity of encapsulant to be used in manufacturing semiconductor devices, suppress the occurrence of voids in the encapsulation parts of the semiconductor devices and non-filling of encapsulant, and prevent various defects from being formed during a sawing or trimming process, and a semiconductor device manufactured by using the mold.
  • a mold for manufacturing semiconductor devices including a first mold having plural cavities with a predetermined depth, the plural cavities being arranged in one or more rows in such a manner as to be spaced from each other in each row, so that plural semiconductor devices are positioned in one or more rows, the plural cavities in each row being communicated with each other through through-gates, which are shallower than the cavities; and a second mold which comes into close contact with the first mold and allows encapsulant to sequentially flow into all the cavities through the through-gates in such a manner as to surround the semiconductor devices positioned within the cavities.
  • the width of the through-gates formed in the first mold may be equal to or narrower than that of the cavities.
  • Each of the through-gates may be communicated with an end portion or a central portion of a side of a corresponding cavity.
  • another mold for manufacturing semiconductor devices including a first mold having plural cavities with a predetermined depth, the plural cavities being arranged in one or more rows in such a manner as to be spaced from each other in each row, so that plural semiconductor devices are positioned in one or more rows, the plural cavities in each row being communicated with each other through through-gates, which are shallower than the cavities; a second mold which comes into close contact with the first mold and allows encapsulant to sequentially flow into all the cavities through the through-gates in such a manner as to surround the semiconductor devices positioned within the cavities; and plural gate lock blocks installed through the second mold at the areas corresponding to the through-gates of the first mold, wherein the gate lock blocks open the through- gates during an encapsulating process and close the through-gates or reduce the open spaces of the through-gates after the encapsulating process is completed.
  • the width of the gate lock blocks may be same as that of the through-gates, and the width of the through-gates is equal to or smaller than that of the cavities.
  • Each of the through-gates may be communicated with an end portion or a central portion of a side of a corresponding cavity.
  • the mold may further include a block moving member on the gate lock blocks so as to linearly reciprocate the gate lock blocks.
  • the block moving member may be any one selected from a pneumatic cylinder, a hydraulic cylinder, and a motor.
  • another mold for manufacturing semiconductor devices including a first mold having a cavity with a predetermined depth, at least one gate of a predetermined depth being communicated with the cavity; a second mold which comes into close contact with the first mold and allows encapsulant to sequentially flow into the cavity through the gate of the first mold in such a manner as to surround all the semiconductor devices positioned within the cavity; and a split block installed through the first mold to the cavity so as to allow each of the semiconductor devices to be formed with a separate encapsulation part, wherein the split block completely opens the cavity so that encapsulant can smoothly flows during an encapsulating process, and comes into contact with or approaches each of the semiconductor devices so that the encapsulation parts of respective semiconductor devices could be separated from each other.
  • the split block may include plural crosswise and longitudinal partitions which are crossed with each other.
  • One encapsulation part may be formed in one area surrounded by two crosswise partitions and two longitudinal partitions.
  • the mold may further include a block moving member installed on the split block so as to linearly reciprocate the split block.
  • the block moving member may be any one selected from a pneumatic cylinder, a hydraulic cylinder, and a motor.
  • a semiconductor device including a semiconductor die; a lead frame, the semiconductor die being mounted on the lead frame and electrically connected with the lead frame; and an encapsulation part formed by encapsulating the semiconductor die and the lead frame with encapsulant, wherein the encapsulation part is formed, on its surface, with at least one en- capsulant cutting trace corresponding to an inlet or an outlet of the encapsulant during an encapsulating process.
  • the encapsulation part may include a first surface, which is flat and has a predetermined area, a second surface, which is positioned opposite to the first surface, and four third surfaces, which are arranged in a rectangular shape along and between the edges of the first and second surfaces, the third surfaces being narrower than either the first surface or the third surface.
  • the encapsulant cutting traces may be symmetrically formed on two third surfaces, which are positioned opposite and parallel to each other, among the four third surfaces.
  • the encapsulant cutting traces may be asymmetrically formed on two third surfaces, which are positioned opposite and parallel to each other, among the four third surfaces.
  • the lead frame may be projected outwardly from any one of the four third surfaces by a predetermined length.
  • the encapsulant cutting traces may be symmetrically formed on the two third surfaces which are positioned opposite and parallel to each other and perpendicular to the third surface, from which the lead frame is projected.
  • the encapsulant cutting traces may be asymmetrically formed on the two third surfaces which are positioned opposite and parallel to each other and perpendicular to the third surface, from which the lead frame is projected.
  • Each of the encapsulant cutting traces may be projected from a corresponding third surface of the encapsulation part by a predetermined length, recessed in the corresponding third surface by a predetermined depth, or flush with the corresponding third surface.
  • the encapsulant cutting traces may be same with or smaller than the third surfaces in width.
  • FIG. 1 is a top plan view showing an array of semiconductor devices, which are encapsulated by a conventional mold for manufacturing semiconductor devices, and FIG. 2 is an enlarged top plan view of a part of FIG. 1 ;
  • FIG. 3 is a top plan view showing an array of semiconductor devices in a state of being encapsulated in a mold for producing semiconductor devices according to the present invention
  • FIG. 4 is an enlarged top plan view showing a part of FIG. 3
  • FlGs. 5 and 6 are cross-sectional and longitudinal sectional views showing an array of semiconductor devices in a state of being encapsulated in a mold according to an embodiment of the present invention
  • FlG. 7 is a top plan view showing semiconductor devices seated in the mold
  • FlGs. 8, 9 and 10 are cross-sectional, longitudinal sectional, and top plan views showing encapsulation parts in a mold according to another embodiment of the present invention before gate lock blocks are operated, respectively, and FlGs. 11, 12 and 13 are cross-sectional, longitudinal sectional and top plan views showing the encapsulation parts in the mold after the gate lock blocks are operated, respectively;
  • FlGs. 14, 15 and 16 are cross-sectional, longitudinal sectional, and top plan views showing the condition of encapsulation parts in a mold according to another embodiment of the present invention before gate lock blocks are operated, respectively, and FlGs. 17, 18 and 19 are cross-sectional, longitudinal sectional, and top plan views showing the condition of encapsulation parts in the mold after the gate lock blocks are operated, respectively;
  • FlGs. 20, 21 and 22 are cross-sectional, longitudinal sectional, and top plan views showing the condition of encapsulation parts in a mold according to another embodiment of the present invention before gate lock blocks are operated, respectively, and FlGs. 23, 24 and 25 are cross-sectional, longitudinal sectional, and top plan views showing the condition of encapsulation parts in the mold after operating gate lock blocks are operated, respectively;
  • FlGs. 26 and 27 are top plan and cross-sectional views showing the condition of encapsulation parts in a mold according to anther embodiment of the present invention before the gate lock blocks of the inventive mold are operated, respectively, and FlGs. 28 and 29 are top plan and cross-sectional views showing the condition of encapsulation parts after the gate lock blocks are operated, respectively;
  • FlGs. 30, 31 and 32 are cross-sectional, longitudinal sectional, and top plan views showing the condition of encapsulation parts in a mold according to another embodiment of the present invention before the gate lock blocks of the inventive mold are operated, respectively, and FlGs. 33, 34 and 35 are cross-sectional, longitudinal sectional, and top plan views showing the condition of encapsulation parts after the gate lock blocks are operated, respectively;
  • FlG. 36 is a perspective view showing a semiconductor device according to an embodiment of the present invention, which is separated from a lead frame strip;
  • FlG. 37 is a top plan view showing the semiconductor device before an encapsulation part is formed, and FlGs. 38 and 39 are cross-sectional views showing the semiconductor device with the encapsulation part;
  • FlGs. 40 and 41 are top plan and side views showing various positions where en- capsulant cutting traces may be formed on an encapsulation part of the inventive semiconductor device;
  • FlGs. 42 and FlG. 43 show, in enlarged scale, gate lock blocks before and after they are operated, respectively;
  • FlG. 44 is a perspective view showing a semiconductor device according to an embodiment of the present invention.
  • FlG. 45 is a perspective view showing a semiconductor device according to another embodiment of the present invention.
  • FlG. 46 is a perspective view showing a semiconductor device according to another embodiment of the present invention.
  • FlG. 3 is a top plan view showing an array of semiconductor devices in a state of being encapsulated in a mold for producing semiconductor devices according to the present invention
  • FlG. 4 is an enlarged top plan view showing a part of FlG. 3.
  • plural lead frames 12 are positioned in a strip form, and each of the lead frames 12 is formed with an encapsulation part 15 with the plural encapsulation parts 15 being spaced from each other.
  • one lead frame 12 and one encapsulation part 15 for encapsulating the lead frame 12 may be defined as a semiconductor device 10.
  • the plural encapsulation parts 15 are spaced from each other and arranged in two rows (they may be arranged in more than two rows).
  • a through-gate encapsulant part 24 between two adjacent arranged encapsulation parts 15, wherein the through-gate encapsulant parts 24 correspond to through-gates in a mold.
  • the first encapsulation part 14, into which an encapsulant is firstly introduced, is formed with a gate encapsulant part 23, which is connected with a runner encapsulant part 22.
  • the runner encapsulant part 22 is connected with a ram pot encapsulant part 21.
  • the ram pot encapsulant part 21 is formed in correspondence with a ram pot in a mold
  • the runner encapsulant part 22 is formed in correspondence with a runner in the mold 22
  • the through-gate encapsulant part 24 is formed in correspondence with a through-gate in the mold.
  • the encapsulation parts 15 of the semiconductor devices 10 are formed in correspondence with cavities provided in the mold.
  • arrows indicate the flow directions of the encapsulant. According to the present invention, it can be appreciated that the en- capsulant flows into a cavity through a ram part, a runner, a gate and a through-gate.
  • every other cavity is filled with the encapsulant, which is introduced into the cavity through a predetermined cavity unlike the prior art. That is, one through-gate, which serves as an inlet, and another through-gate, which serves as an outlet are formed with reference to one cavity, and all the cavities are interconnected with each other through such through-gates.
  • the lead frames 12 encapsulated in this manner and hence the encapsulation parts thereof are separated from each other through the trimming or sawing process (That is, the semiconductor devices 10 are separated from each other as unit chips).
  • the semiconductor devices 10 are separated from each other as unit chips.
  • a mold with a gate lock block is employed, only the lead frames 12 are trimmed or sawed in the trimming or sawing process, whereby a life span of a punch for a trimming apparatus or a sawing blade for a sawing apparatus can be substantially increased.
  • FlGs. 5 and 6 are cross-sectional and longitudinal sectional views showing an array of semiconductor devices in a state of being encapsulated in a mold according to an embodiment of the present invention
  • FlG. 7 is a top plan view showing semiconductor devices seated in the mold.
  • the inventive mold includes a first mold 110 and a second mold 120, which is engaged with the first mold 110.
  • the first mold 110 includes plural cavities 111 which are spaced from each other and arranged in rows, wherein the cavities have a predetermined depth so that semiconductor devices can be positioned within the cavities, respectively.
  • the cavities 111 are communicated with each other via through-gates 112, which is shallower than the cavities 111.
  • the second mold 120 comes into close contact with the top of the first mold 110, so that an encapsulant can flow into all the cavities, within which the semiconductor devices 10 are positioned, via the through-gates 112, which are provided in the first mold 110.
  • the cavities 111 formed in the first mold 110 may be formed substantially in a rectangular shape.
  • the through-gates 112 formed in the first mold 110 are shallower than the cavities 111, the through-gates 112 will affect the appearance of the encapsulation parts 15 to be formed later to a minimum.
  • the through-gates 112 formed in the first mold 110 may be narrower than the cavities 111.
  • the width of the through-gates 112 may be same as that of the cavities 111.
  • each of the through-gates 112 is communicated with an end of a side of a corresponding cavity 111.
  • a through-gate 112 may be communicated with a center of a side of the corresponding cavity 111.
  • thick arrow indicates the flow direction of the encapsulant 15.
  • the encapsulant 15 fills the first cavity through the first through-gate 112, and then fills the second cavity 112 through the second through-gate 112. Therefore, the flowing path of the encapsulant 15 is not sharply curved from the runner 114 to the gate 113, the swirling of the encapsulant 14 scarcely occurs. Therefore, a finished encapsulation part contains little voids or non-filling areas.
  • reference numeral 114 denotes an air vent for discharging air within the cavities to the outside of the mold.
  • FlGs. 8, 9, and 10 are cross-sectional, longitudinal sectional, and top plan views showing the condition of encapsulation parts in a mold according to another embodiment of the present invention before gate lock blocks are operated, respectively, and FlGs. 11, 12, and 13 are cross-sectional, longitudinal sectional, and top plan views showing the condition of encapsulation parts in the mold after gate lock blocks are operated, respectively.
  • the inventive mold includes a first mold 110, a second mold 120, and plural gate lock blocks.
  • the first mold 110 has plural cavities 111, each of which has such a depth that a semiconductor device can be positioned within a cavity, wherein the cavities 111 are spaced from each other and arranged in rows. Each of the cavities 111 is communicated with a through-gate of a predetermined depth. At the first through-gate 112, into which the encapsulant 15 is firstly introduced, a gate 113, the length of which is very short, is formed, and the last cavity 111 (the cavity 111 of the right end in the drawing) is formed with an air vent 114 for discharging the air in the cavities to the outside of the mold.
  • the second mold 120 comes into close contact with the first mold 110, so that the sealant can be easily introduced into all the cavities 111, within which the semiconductor devices 10 are positioned, through the through-gates 112 formed in the first mold 110.
  • the gate lock blocks 130 are positioned through the second mold 120 in such a manner as to correspond with the through-gates 112 of the first mold 110.
  • the top ends of gate locks block 130 are provided with a block moving member 132 so as to vertically move the gate lock blocks 130.
  • a block moving member 132 may be any one selected from a pneumatic cylinder, a hydraulic cylinder, a motor and the like.
  • the present invention is not limited to the type of the block moving member 132.
  • the gate lock blocks 130 fully open the through-gates 112 during the encapsulating process as shown in FlGs. 8 to 11. Therefore, the encapsulant 14 easily flows into the first cavity 111 through the first through-gate 112, and then into the second cavity 111 through the second through-gate 112. Of course, the encapsulant 15 continuously flows through the remaining through-gates 112 and cavities 111, whereby all the cavities 111 are filled with the encapsulant 15.
  • the cavities 111 formed in the first mold 110 are preferably but not exclusively formed substantially in a rectangular shape.
  • the through-gates 112 formed in the first mold 110 are shallower than the cavities 111.
  • the through-gates 112 formed in the first mold 110 may be equal to or smaller than the cavities 111 and equal to the gate lock blocks 130 in width. Therefore, the gate lock blocks 130 may completely close the through-gates 112 or substantially reduce the open space of the through-gates 112.
  • each of the through-gates 112 may be communicated preferably but not exclusively with an end or a center of a side of a corresponding cavity 111.
  • the gate lock blocks 130 are operated. That is, as the gate lock blocks 130 are lowered by a predetermined distance by the moving members 132, all the through- gates 112 are completely closed or the open space thereof is substantially reduced. Therefore, the through-gate encapsulant parts, which correspond to the through-gates 112, are not formed. Of course, the gate lock blocks 130 should be operated before the encapsulant 15 is cured.
  • a trim punch or a sawing blade only trims or saws the lead frames 12 (or circuit boards). That is, the trim punch or the sawing blade is scarcely fractured by encapsulation or encapsulant parts. Therefore, according to the present invention, the life span of the trim punch or the sawing blade can be increased. Of course, because the read lead frames 12 (or circuit boards) are only trimmed or sawed in the trimming or sawing process, the appearance of the encapsulation parts is scarcely damaged.
  • FlGs. 14, 15, and 16 are cross-sectional, longitudinal sectional, and top plan views showing the condition of encapsulation parts in a mold according to another embodiment of the present invention before gate lock blocks are operated, respectively
  • FlGs. 17, 18 and 19 are cross-sectional, longitudinal sectional, and top plan views showing the condition of encapsulation parts in the mold after the gate lock blocks are operated, respectively.
  • the mold shown in FlGs. 14 to 5f is similar to that described above with reference to FlGs. 8 to 13 in configuration, only the different parts are described below.
  • the mold according to another embodiment of the present invention also includes a first mold 110, a second mold 120 and plural gate lock blocks 130.
  • the first mold 110 is formed with plural cavities 111, within which semiconductor devices 10 are positioned, respectively, in two rows (or in more than two rows), and the cavities in each row are communicated with each other via the through-gates 112.
  • the two rows of through-gates 112 are located as near as possible and extend parallel to each other.
  • the gate lock blocks 130 engaged with the second mold 120 open the through-gates 112, respectively.
  • the gate lock blocks 130 are operated after the encapsulating process is completed, whereby all the through-gates 112 are completely closed or the open space thereof can be substantially reduced. Therefore, through-gate encapsulant parts are scarcely formed in the areas corresponding to the through-gates 112. Of course, the gate lock blocks 130 should be operated before the encapsulant 15 is cured.
  • FlGs. 20, 21, and 22 are cross-sectional, longitudinal sectional, and top plan views showing the condition of encapsulation parts in a mold according to another embodiment of the present invention before the gate lock blocks are operated, respectively
  • FlGs. 23, 24 and 25 are cross-sectional, longitudinal sectional, and top plan views showing the condition of encapsulation parts in the mold after the gate lock blocks are operated, respectively.
  • the mold shown in FlGs. 20 to 25 is similar to that described above with reference to FlGs. 8 to 13 in configuration, only the different parts are described below.
  • the mold according to another embodiment of the present invention also includes a first mold 110, a second mold 120 and plural gate lock blocks 130.
  • the first mold 110 is formed with plural cavities 111, within which semiconductor devices 10 are positioned, respectively, in two rows (or in more than two rows), and the cavities 111 in each row are communicated with each other via through-gates 112.
  • the two rows of through-gates 112 are located as remote as possible and extend parallel to each other.
  • the lock blocks 130 engaged with the second mold 120 open the through-gates 112, respectively.
  • the gate lock blocks 130 are operated after the encapsulating process is completed, whereby all the through-gates 112 can be completely closed or the open space thereof can be substantially reduced. Therefore, through-gate encapsulant parts are scarcely formed in the areas corresponding to the through-gates 112. Of course, the gate lock blocks 130 should be operated before the encapsulant 15 is cured.
  • FlGs. 26 and 27 are top plan and cross-sectional views showing the condition of encapsulation parts in a mold according to anther embodiment of the present invention before the gate lock blocks of the inventive mold are operated, respectively, and FlGs. 28 and 29 are top plan and cross-sectional views showing the condition of encapsulation parts after the gate lock blocks are operated, respectively.
  • a ram pot 115 is formed at a side portion of the first mold 110, into which the encapsulant is introduced, wherein the ram pot 115 is connected with four runners 114, each being formed in a predetermined length and depth. At the ends of the runners 114, plural cavities 111, which are formed in a predetermined depth, are arranged in four rows with a predetermined space. Here, the cavities 111 in each row are communicated with each other through through-gates 112, the width of which is same as that of the cavities 111.
  • gate lock blocks 130 for completely closing the through-gates 112 or reducing the open space thereof, wherein the width of the gate lock blocks 130 is same as that of the through-gate 112.
  • the encapsulant 15 fed from the ram pot 115 is sequentially introduced into the first to last cavities 111 in each row, through corresponding runner 114 and gate 113 and first to last through-gates 112, whereby all the cavities 111 are filled with the encapsulant 115.
  • the gate lock blocks 130 engaged with the second mold 12 are not operated, so that all the through-gates 112 are opened.
  • the gate lock blocks 130 are lowered, thereby completely closing or substantially reducing the open space of all the through-gates 112, each being provided between two adjacent cavities 111. Therefore, through-gate encapsulant parts are not substantially formed at the areas corresponding to the through-gates 112. Of course, the gate lock blocks 130 are operated before the encapsulant 15 is cured.
  • FlGs. 30, 31 and 32 are cross-sectional, longitudinal sectional, and top plan views showing the condition of encapsulation parts in a mold according to another embodiment of the present invention before the gate lock blocks of the inventive mold are operated, respectively, and FlGs. 33, 34 and 35 are cross-sectional, longitudinal sectional, and top plan views showing the condition of encapsulation parts after the gate lock blocks are operated, respectively.
  • the mold according to another embodiment of the present invention includes a first mold 110, a second mold 120, and a split block 130.
  • the first mold 110 is formed with a cavity 111, which has a predetermined depth and area, so that plural semiconductor devices 10 can be positioned in the cavity at once, and one or more gates 113 of a predetermined depth are communicated with the cavity 111.
  • Each gate 113 is communicated with a runner 114 of a predetermined depth, which is in turn communicated with a ram pot 115.
  • the second mold 120 Upon coming into close contact with the first mold 110, the second mold 120 allows encapsulant 15 to flow into the cavity 111 so as to surround all the semiconductor devices, which are positioned in the cavity 111, through the gates 113 of the first mold 110.
  • the split block 130 is installed through the first mold 110 and extends to the cavity
  • Such a split block 130 includes plural crosswise partitions 134 and longitudinal partitions 136, which are crossed with each other. In other words, the crosswise partitions 134 and longitudinal partitions 136 are arranged in a grid form in the split block 130. By each rectangular area surrounded by the crosswise and longitudinal partitions 134 and 136, one encapsulation part 15 (i.e., one semiconductor device) is formed.
  • a block moving member 132 is further provided so as to vertically reciprocate the split block 130.
  • the block moving member 132 may be selected preferably but not exclusively from a pneumatic cylinder, a hydraulic cylinder, a motor, and the like.
  • the split block 130 is not moved toward the inside of the cavity 111 while the encapsulant 15 is being introduced into the cavity 111 through the ram pot 115, the runners 114, and the gates 113. That is, in order to ensure that the encapsulant 15 arrives at all the semiconductor devices 10 within the cavity 111, the split block 130 remains in a state of being raised from the semiconductor devices 10 by a predetermined distance. As such, the cavity 111 is completely opened.
  • the split block 130 is lowered by a predetermined distance as the block moving member 132 is driven, so that the split block 130 comes into contact with or is positioned adjacent the surfaces of the semiconductor devices 10. Specifically, the split block 130 completely closes the cavity 111 or substantially reduces the open space of the cavity 111, so that the encapsulation parts formed over the semiconductor devices are completely separated from each other. In other words, as the split block 130 is lowered, one encapsulation part 15 is formed on each semiconductor device 10. Between adjacent semiconductor devices 10, no encapsulant part is formed, or even if formed, the thickness of such an encapsulant part is very thin unlike the prior art.
  • FlG. 36 is a perspective view showing a semiconductor device according to an embodiment of the present invention, which is separated from a lead frame strip.
  • FlGs. 37 is a top plan view showing the semiconductor device before an encapsulation part is formed
  • FlGs. 38 and 39 are cross-sectional views showing the semiconductor device with the encapsulation part.
  • the inventive semiconductor device 10 includes a semiconductor die 11, a lead frame 12, on which the semiconductor die 11 is mounted, the semiconductor die 11 being electrically connected with the lead frame, and an encapsulation part 15 formed by encapsulating the semiconductor die 11 and the lead frame 12 with an encapsulant.
  • the inventive semiconductor device 10 is formed with at least two encapsulant cutting traces 16, which are formed on the lateral sides of the encapsulation part 15 due to the inlet and outlet of a through-gate.
  • the encapsulation part 15 includes a first surface 15a, which is substantially flat and has a predetermined area, a second surface 15b, which is positioned opposite to the first surface 15a, and four third surfaces which extend along and between the four edges of the first and second surfaces 15a and 15b, thereby being arranged in a rectangular form.
  • the lead frame 12 is projected through one of the four third surfaces 15c, so that the lead frame 12 can be easily connected to an external ap paratus.
  • the two encapsulant cutting traces 16 may be formed on symmetrically arranged areas of two third surfaces 15c, which are parallel to each other, among the four third surfaces 15c.
  • the two encapsulant cutting traces 15 may be symmetrically formed on the two opposite third surfaces 15c, which are parallel to each other but perpendicular to the third surface 15c, through which the lead frame 12 is projected.
  • each of the encapsulant cutting traces 16 may take a form of a protrusion projected from the encapsulation part by a predetermined length.
  • the encapsulant cutting trace 16 formed on one third surface 15c may be a trace of the inlet of a through-gate, and the encapsulant cutting trace 16 formed on another third surface 15c may be a trace of the outlet of the through-gate.
  • reference numeral 13 denotes a conductive wire for electrically interconnecting the semiconductor die 11 and the lead frame 12
  • reference numeral 14 denotes an Ag paste or solder paste for interconnecting the semiconductor die 11 and the lead frame 12.
  • the above-mentioned two encapsulant cutting traces 16 may be formed because through-gates are oppositely formed with reference to a cavity in a mold. That is, through-gate encapsulant parts are formed after the encapsulating process is completed, and cut in a cutting process, whereby the encapsulation cutting parts defined herein are formed.
  • the encapsulant cutting traces 16 are drawn in a shape projected too much from the encapsulation part 15, the length of each encapsulation part does not exceed several nanometers.
  • the encapsulant cutting traces 16 may be flush with the corresponding third surfaces 15c of the encapsulation part 15 without being projected from the third surfaces 15c.
  • the encapsulant cutting traces 16 may be also formed through the sawing process or the punching process.
  • FlGs. 40 and 41 are top plan and side views showing various positions where encapsulant cutting traces may be formed on an encapsulation part of the inventive semiconductor device.
  • the inventive semiconductor device 10 has encapsulant cutting traces 16 each formed in a protrusion shape (or merely in a trace form without being projected) wherein the encapsulant cutting traces 16 may be formed on positions of a-a , a-b , a-c , b-a , b-b , b-c , c-a , c-b or c-c on the encapsulation part of the semiconductor device 10. That is, the encapsulant cutting traces 16 may be symmetrically or asymmetrically formed on two oppositely positioned third surfaces 15c. In addition, the encapsulant cutting traces 16 may be formed on at least two positions among the positions a, b and c, and on at least two positions among the positions a , b and c .
  • the encapsulant cutting traces 16 may be formed on d, e, f, g or h position beyond the a position, and the present invention is not limited by the positions and number of the encapsulant cutting traces 16 formed on one of the third surfaces 15c.
  • the encapsulant cutting traces 16 are shown as a rectangular shape in FlG. 40, the present invention is not limited to this. That is, the encapsulant cutting traces 16 may take various forms such as a trapezoidal shape, a circular shape, a semi-circular shape, or the like. Of course, the shapes of the encapsulant cutting traces 16 are solely dependent from the cross-sectional shape of through-gates formed on opposite sides of a cavity.
  • FlG. 42 shows, in enlarged scale, gate lock blocks before they are operated
  • FlG. 43 shows, in enlarged scale, the gate lock blocks after they are operated.
  • through-gate encapsulant parts 24 may be formed, which are connected to an encapsulation part 15, during the encapsulating process, and they are removed by gate lock blocks 130 prior to being cured.
  • one or more positional errors may be caused in connection with such gate lock blocks 130. That is, a positional error in engagement between the gate lock blocks 130 and the second mold 120, a positional error between a lock block 130 and a cavity 111, a positional error between a gate lock block 130 and a through-gate 112, etc. may be caused.
  • one surface (third surface) is formed with an encapsulant cutting trace 16 in a form of a protrusion as shown in FlG. 44 but the other surface (third surface) in the opposite side is formed with an encapsulant cutting trace 16 in a from of a recess.
  • the inventive semiconductor device 10 may be formed with an encapsulant cutting trace 16 in a form of a protrusion on one third surface 15c of the encapsulation part 15 and an encapsulant cutting trace 16 in a form of a recess on the other third surface 15c in the opposite side of the encapsulation part 15. If a positional error does not substantially exist, it is of course that the encapsulant cutting traces 16 are substantially flush with the third surfaces 15c of the encapsulation part 15. However, the encapsulant cutting traces 16 formed by these gate lock blocks 130 are sufficiently visually recognizable.
  • FlG. 44 is a perspective view showing a semiconductor device according to an embodiment of the present invention.
  • one third surface 13c of the semiconductor device 10 may be formed with an encapsulant cutting trace 16 in a form of a protrusion, and the other third surface 15c in the opposite side may be formed with an encapsulant cutting trace 16 in a form of a recess. Therefore, the inventive semiconductor device 10 may have encapsulant cutting traces 15c in the forms of a protrusion and a recess on the third surfaces 15c, which are the opposite lateral sides of the encapsulation part 15.
  • FlG. 45 is a perspective view showing a semiconductor device according to another embodiment of the present invention.
  • one third surface 13c of the semiconductor device 10 may be formed with an encapsulant cutting trace 16 in a form of a recess.
  • the other third surface 15c in the opposite side may be also formed with an encapsulant cutting trace 16 in a form of a recess.
  • both of the encapsulant cutting traces 16 may be formed in a shape of protrusion on the two opposite third surfaces 15c of the encapsulation part 15.
  • one encapsulant cutting trace 16 formed on one third surface 15c may be in a form of a protrusion and the other encapsulant cutting trace 16 formed on the other third surface 15c in the opposite side may be in a form of a recess.
  • both of the encapsulant cutting traces 16 formed on the opposite third surfaces 15c may be flush with the third surfaces 15c.
  • the encapsulant cutting traces 16 may be equal to or slightly smaller than corresponding third surfaces in length. However, the invention is not limited by the length of the encapsulant cutting trace 16.
  • FIG. 46 is a perspective view showing a semiconductor device according to another embodiment of the present invention.
  • a large-scale semiconductor device 10 may be formed with encapsulant cutting traces 16 on only one of third surfaces 15c. That is, because a large-scale semiconductor device 10 is not manufactured through a method, which forms plural encapsulation parts 15 on one lead frame strip, it is difficult to form an encapsulation part 15 in a through-gate type.
  • the inventive gate lock blocks 130 can be sufficiently employed. That is, by providing gate lock blocks 130 at the areas corresponding to the gates connected to a cavity 111, a finished semiconductor device may be formed with encapsulant cutting traces only at one side of the encapsulation part.
  • Such encapsulant cutting traces 16 may be projected, recessed or flush with the corresponding lateral surface of the encapsulation part 15.
  • no gate encapsulant part is formed at the areas corresponding to the gates of a mold or even if formed, such a gate encapsulant part is very thin, whereby it is also possible to reduce the quantity of encapsulant to be used.
  • cavities in a mold for manufacturing semiconductor devices are communicated with each other through through- gates, each of which extends between two adjacent cavities, rather than being communicated with each other through a single runner and gates, which extend from the single runner, as in the prior art, whereby the quantity of encapsulant to be used in manufacturing semiconductor devices can be substantially reduced.
  • the gate encapsulant parts which are formed in the through-gates of the mold and wasted after an encapsulating process, are formed from a small amount of encapsulant.
  • encapsulant is introduced into each of cavities through a straightly arranged through-gate rather than through a gate which substantially extends perpendicularly from a runner as in the prior art, whereby the swirling of the encapsulant can be suppressed. Therefore, voids are scarcely produced in encapsulation parts formed within the cavities. Furthermore, it is very seldom that the cavities are insufficiently filled with encapsulant.
  • the present invention provides gate lock blocks for opening through-gates during an encapsulating process and closing the through-gates after the encapsulating process is completed, whereby it is sufficient if lead frames (or circuit boards) are only trimmed by a punch during a trimming process. That is, it is not necessary to trim encapsulant or encapsulation parts along with lead frames with a punch. Therefore, the life span of such a punch can be increased. In addition, because no gate encapsulant part exists (even if existing, the thickness of such a gate encapsulant part is very thin as compared with those of the prior art), the fracture of encapsulation parts, which has been caused when cutting gate encapsulant parts in the prior art, is not caused.
  • the encapsulation parts of semiconductor devices are formed through a through-gate type or gate-block type method. Therefore, after the encapsulating process is completed, opposite lateral surfaces (or one lateral surface) of an encapsulation part are formed with encapsulant cutting traces, which are the traces of the inlet and outlet of the encapsulant are naturally formed during the encapsulation cutting process, which is performed after the encapsulating process is completed. Therefore, if encapsulant cutting traces as mentioned above are seen in a semiconductor device, it can be inferred that the semiconductor device is manufactured by using the inventive method.
  • a split block which enables encapsulant to easily flow between and over semiconductor devices during the encapsulating process and which allows the encapsulation parts for individual semiconductor devices to be smoothly separated from each other.
  • it is possible to form a single large cavity instead of plural cavities in a mold. If plural semiconductor dies are manufactured using such a single large cavity, it may be necessary to saw encapsulation parts and lead frames (or circuit boards) in unison in the sawing process.
  • the encapsulation parts are separated from each other by the split block in advance, any one of a sawing process using a sawing blade and a trimming process using a punch can be selected and employed.
  • substantially no impact is applied to the encapsulation parts while they are sawed or trimmed, except lead frames (or circuit boards), the fracture of encapsulation parts can be greatly reduced.

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Moulds For Moulding Plastics Or The Like (AREA)
  • Injection Moulding Of Plastics Or The Like (AREA)

Abstract

L'invention concerne un moule pour la fabrication de dispositifs semi-conducteurs et un semi-conducteur fabriqué à l'aide du moule. Le moule comprend: un premier moule comportant de multiples cavités présentant une profondeur prédéterminée, les multiples cavités étant placées de manière à former une ou plusieurs rangées et étant espacées l'une de l'autre dans chaque rangée, de sorte que les multiples dispositifs semi-conducteurs forment une ou plusieurs rangées, les multiples cavités de chaque rangée communiquant entre elles par l'intermédiaire de passages, qui sont moins profonds que les cavités; un deuxième moule entrant en contact étroit avec le premier moule permet l'écoulement séquentiel, par les passages, de la matière d'encapsulation dans toutes les cavités, de sorte que ladite matière entoure les dispositifs semi-conducteurs placés dans les cavités; et de multiples unités portes, installées à travers le deuxième moule dans les zones correspondant aux passages du premier moule. Les unités portes ouvrent les passages pendant le processus d'encapsulation, et les referment ou réduisent les espaces ouverts des passages lorsque le processus d'encapsulation est achevé.
PCT/KR2006/001937 2005-06-02 2006-05-24 Moule pour la fabrication de dispositifs semi-conducteurs et dispositif semi-conducteur fabrique a l'aide de celui-ci Ceased WO2006129926A1 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
KR1020050047428A KR100714884B1 (ko) 2005-06-02 2005-06-02 반도체 장치 제조용 금형
KR10-2005-0047428 2005-06-02
KR1020060022126A KR100640556B1 (ko) 2006-03-09 2006-03-09 반도체 장치
KR10-2006-0022126 2006-03-09
KR1020060039577A KR100767194B1 (ko) 2006-05-02 2006-05-02 반도체 장치
KR10-2006-0039577 2006-05-02

Publications (1)

Publication Number Publication Date
WO2006129926A1 true WO2006129926A1 (fr) 2006-12-07

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PCT/KR2006/001937 Ceased WO2006129926A1 (fr) 2005-06-02 2006-05-24 Moule pour la fabrication de dispositifs semi-conducteurs et dispositif semi-conducteur fabrique a l'aide de celui-ci

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JP (1) JP2006339649A (fr)
WO (1) WO2006129926A1 (fr)

Cited By (2)

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Publication number Priority date Publication date Assignee Title
US9941182B2 (en) 2013-06-21 2018-04-10 Denso Corporation Electronic device and method for manufacturing same
US20210242038A1 (en) * 2019-08-06 2021-08-05 Texas Instruments Incorporated Universal semiconductor package molds

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5341556B2 (ja) * 2008-09-30 2013-11-13 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置の製造方法
JP5873886B2 (ja) * 2014-03-25 2016-03-01 アピックヤマダ株式会社 樹脂成形体の製造方法、及び、ｌｅｄパッケージの製造方法
JP7360374B2 (ja) * 2020-11-04 2023-10-12 Ｔｏｗａ株式会社 樹脂成形装置及び樹脂成形品の製造方法

Citations (3)

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Publication number Priority date Publication date Assignee Title
JPS57203532A (en) * 1981-06-10 1982-12-13 Toshiba Chem Corp Mold for molding thermosetting resin
JPH08217313A (ja) * 1994-12-14 1996-08-27 Canon Inc 画像形成装置のカール修正装置
JP2000031180A (ja) * 1999-06-28 2000-01-28 Hitachi Ltd 半導体装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57203532A (en) * 1981-06-10 1982-12-13 Toshiba Chem Corp Mold for molding thermosetting resin
JPH08217313A (ja) * 1994-12-14 1996-08-27 Canon Inc 画像形成装置のカール修正装置
JP2000031180A (ja) * 1999-06-28 2000-01-28 Hitachi Ltd 半導体装置の製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9941182B2 (en) 2013-06-21 2018-04-10 Denso Corporation Electronic device and method for manufacturing same
US20210242038A1 (en) * 2019-08-06 2021-08-05 Texas Instruments Incorporated Universal semiconductor package molds
US11791170B2 (en) * 2019-08-06 2023-10-17 Texas Instruments Incorporated Universal semiconductor package molds

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