WO2007015258A1 - Microprocesseur equipe d'une unite de commande configurable - Google Patents

Microprocesseur equipe d'une unite de commande configurable Download PDF

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Publication number
WO2007015258A1
WO2007015258A1 PCT/IN2005/000261 IN2005000261W WO2007015258A1 WO 2007015258 A1 WO2007015258 A1 WO 2007015258A1 IN 2005000261 W IN2005000261 W IN 2005000261W WO 2007015258 A1 WO2007015258 A1 WO 2007015258A1
Authority
WO
WIPO (PCT)
Prior art keywords
component
instruction
microprocessor
control
cycle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IN2005/000261
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English (en)
Inventor
Kumar Bulusu Gopi
Desikan Murali
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to PCT/IN2005/000261 priority Critical patent/WO2007015258A1/fr
Publication of WO2007015258A1 publication Critical patent/WO2007015258A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter

Definitions

  • the present invention relates to the field of microprocessors and more specifically to configurable microprocessors. More particularly the present invention relates to a microprocessor with a configurable control unit .
  • a typical microprocessor includes data paths containing registers and one or more execution units and a control path to coordinate the program execution.
  • the control unit is responsible for fetching program instructions from memory, decoding
  • control unit of a microprocessor depends on the number of execution paths, number of instructions and the number of stages in execution of an instruction.
  • One way to design a control unit involves representing the control logic entirely though the interconnections between the various components of the logic
  • a control unit designed using such a method is known as a hardwired control unit.
  • the logic circuit is responsible for generating appropriate control signals for each processor cycle based on the input instruction and the current state. For each cycle one basic operation is performed as specified by the
  • a micro-programmed control unit stores the control signals as microinstructions in a memory area within the control unit. For each processor instruction, a sequence of microinstructions will be fetched from this memory and corresponding control signals will be activated to perform the required operations.
  • a micro-programmed control unit can represent more complex operations and can be modified by updating the micro-program memory with updated microinstructions. However, it is generally slower than a hardwired control unit.
  • microprocessor is developed. To overcome this limitation, the present invention
  • control unit which can be configured using the control information specified in the program instructions themselves.
  • the present invention relates to a microprocessor having a configurable control
  • the instructions of the processor according to the invention include control information associated with the operation code (opcode) and the operands. This control information is provided as clock cycle count and cycle type attributes.
  • instruction decoder of the processor reads the instruction and decodes it. The control
  • cycle type attribute could have one of the values "read”, "execute” or "write”. If cycle type, of the selected component is "read”, then the corresponding operand is read from memory or register. If the cycle type of the component is "write”, then the operand corresponding to the component is written to memory or register file. If the cycle type of the component is "execute”, then the operation specified by the
  • control unit decrements the cycle counts of all components of the current instruction. This process is repeated till the instruction has no component with cycle count zero, which means that the instruction execution is complete and the next instruction is fetched from memory.
  • FIG. 1 is a block diagram of a microprocessor with a configurable control unit implemented in accordance with an embodiment of the invention.
  • FIG. 2 is a block diagram of the configurable control unit implemented in accordance with an embodiment of the invention.
  • FIG. 3 is a diagram of the instruction format of a microprocessor implemented in accordance with an embodiment of the invention.
  • FIG. 4 is a flow diagram of a method describing the steps involved in the execution of instructions on a microprocessor implemented in accordance with an
  • FIG. 1 shows a particular embodiment of the microprocessor with configurable control unit according to the present invention.
  • the microprocessor 100 according to the described embodiment includes an instruction buffer 101 in which the instructions
  • an instruction decoder 102 which decodes the instruction
  • a configurable control unit 103 which controls instruction execution
  • one or more functional units 104 one or more functional units 104
  • a register file 105 for storing data
  • a memory interface 106 which interfaces with the system memory.
  • FIG. 2 shows the configurable control unit 103 in detail.
  • the control unit 103 contains a component selector 201, which selects a particular component (operand or operation code) of the decoded instruction for execution.
  • the control logic 202 is the control logic 202 .
  • control signals to read or write operands or to perform an operation. This is done based on the cycle type attribute specified for the component selected by the
  • FIG. 3 shows the format of instructions for the present microprocessor.
  • Each instructions includes an operation code (opcode) 200 which specifies the operation performed by the instruction, opcode control attributes 201 which is a set of values for cycle count and cycle type for the opcode and one or more operands 202 and operand
  • control attributes 203 which again is a list of values for cycle count and cycle type for the operand.
  • the cycle count is a numerical value, which specifies when a particular component of the instruction should be considered for execution. A component with cycle count of zero is considered first for execution.
  • the cycle type attribute of a component of an instruction can take one of three values -viz. read,
  • the read cycle type is used for input operands, the write cycle type for output operands and the execute cycle type for operations.
  • FIG. 3 only shows a high-level format of the instructions for the microprocessor according to the present invention. A person skilled in the art can implement the actual representation of the instructions or the present
  • microprocessor in many different ways.
  • FIG. 4 shows the steps of a method according to the preset invention for executing instructions of the microprocessor according to the invention.
  • the method starts at block 400 where an instruction is fetched from memory for execution and
  • the instruction is taken from the instruction buffer 101 and
  • the component selector 201 of the configurable control unit 103 selects the component 205 of the instruction with cycle count zero.
  • the cycle type associated with the instruction component 205 is
  • control logic 202 If it is found to be a read cycle, then at block 405, the control logic 202 generates read control signals 203 to read (fetch) the operand
  • control proceeds to block 410. If, at block 404, the control logic 202 finds that the
  • cycle type is not "read", then control goes to block 406 instead of 405.
  • control logic 202 checks if the cycle type of the instruction component 205 is execute. If it is, then control passes to block 407, where the control
  • control proceeds to block 410. If, at block 406, the control logic 202 finds that the cycle type is not "execute”, then control goes to block 408 instead of 407.
  • control logic 202 checks if the cycle type of the instruction
  • control goes to block 410.
  • control logic 202 decrements the cycle counts of all the components of the instruction by one and then control passes back to block 401 to select another component of the instruction for execution.
  • ADD is the operation code representing addition
  • Rl and R2 are the input operands
  • R3 is the output operand for holding the result of the addition.
  • the above instruction is expanded by attaching attributes to each component of the instruction. This can be represented
  • the instruction is fetched from memory and placed in instruction buffer 101. Then the instruction decoder 102 decodes it.
  • the component selector 201 of the control unit 103 obtains the decoded instruction and selects the component with cycle count zero. In the above case, the selected component will be the operand Rl.
  • the control logic 202 then checks the cycle type of this component and generates read
  • control signals 203 This causes the value to be read from register Rl in the register file 105. Then the control logic decrements the cycle counts of all the components of the instruction. At this stage, the attribute values for the instruction will be as shown below:

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

La présente invention concerne un microprocesseur équipé d'une unité de commande configurable qui peut être configurée de manière dynamique. Les informations concernant le moment où les opérandes doivent être lus, le moment où des opérations doivent être effectuées et le moment où des résultats doivent être inscrits sont indiquées dans les instructions du microprocesseur sous forme d'attributs de commande. L'unité de commande exécute ces instructions sur la base de ces attributs. La configuration et la conception du microprocesseur sont ainsi simplifiées.
PCT/IN2005/000261 2005-08-04 2005-08-04 Microprocesseur equipe d'une unite de commande configurable Ceased WO2007015258A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/IN2005/000261 WO2007015258A1 (fr) 2005-08-04 2005-08-04 Microprocesseur equipe d'une unite de commande configurable

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IN2005/000261 WO2007015258A1 (fr) 2005-08-04 2005-08-04 Microprocesseur equipe d'une unite de commande configurable

Publications (1)

Publication Number Publication Date
WO2007015258A1 true WO2007015258A1 (fr) 2007-02-08

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IN2005/000261 Ceased WO2007015258A1 (fr) 2005-08-04 2005-08-04 Microprocesseur equipe d'une unite de commande configurable

Country Status (1)

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WO (1) WO2007015258A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4633390A (en) * 1980-04-25 1986-12-30 Tokyo Shibaura Denki Kabushiki Kaisha Microprogram control system
US4714991A (en) * 1984-02-21 1987-12-22 International Computers Limited Microprogram control apparatus having variable mapping between microinstruction control bits and generated control signals
US6026490A (en) * 1997-08-01 2000-02-15 Motorola, Inc. Configurable cryptographic processing engine and method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4633390A (en) * 1980-04-25 1986-12-30 Tokyo Shibaura Denki Kabushiki Kaisha Microprogram control system
US4714991A (en) * 1984-02-21 1987-12-22 International Computers Limited Microprogram control apparatus having variable mapping between microinstruction control bits and generated control signals
US6026490A (en) * 1997-08-01 2000-02-15 Motorola, Inc. Configurable cryptographic processing engine and method

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