WO2007017394A2 - Procede et dispositif pour determiner un etat de demarrage pour systeme informatique comportant au moins deux unites d'execution, par prise en charge de l'etat de demarrage - Google Patents

Procede et dispositif pour determiner un etat de demarrage pour systeme informatique comportant au moins deux unites d'execution, par prise en charge de l'etat de demarrage Download PDF

Info

Publication number
WO2007017394A2
WO2007017394A2 PCT/EP2006/064721 EP2006064721W WO2007017394A2 WO 2007017394 A2 WO2007017394 A2 WO 2007017394A2 EP 2006064721 W EP2006064721 W EP 2006064721W WO 2007017394 A2 WO2007017394 A2 WO 2007017394A2
Authority
WO
WIPO (PCT)
Prior art keywords
execution unit
start state
mode
execution units
comparison
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2006/064721
Other languages
German (de)
English (en)
Other versions
WO2007017394A3 (fr
Inventor
Reinhard Weiberle
Bernd Mueller
Eberhard Boehl
Yorck Collani
Rainer Gmehlich
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of WO2007017394A2 publication Critical patent/WO2007017394A2/fr
Publication of WO2007017394A3 publication Critical patent/WO2007017394A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1658—Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1683—Temporal synchronisation or re-synchronisation of redundant processing components at instruction level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/845—Systems in which the redundancy can be transformed in increased performance

Definitions

  • the invention relates to a method and a device for switching between at least two operating modes of a microprocessor having at least two execution units for processing program segments according to the preambles of the independent claims.
  • Such processor units are also known as dual-core or multi-core architectures.
  • the different cores execute the same program segment redundantly and clock-synchronously, the results of the two cores are compared. An error is found in the comparison to Matching of the two results recognized In the following, this configuration is referred to as a comparison mode.
  • Dual-core or multi-core architectures are also used in other applications to increase performance, ie to increase performance. Both cores run different program segments, which can achieve a performance improvement compared to the comparison mode or a single core system. This configuration is called power mode or performance mode.
  • This system is also referred to as a symmetrical multiprocessor system (SMP) in a special form with the same cores.
  • SMP symmetrical multiprocessor system
  • SMP symmetric multiprocessor
  • the internal states (registers, pipeline, etc.) of the execution units must be adjusted before switching from the performance mode to the comparison mode. In the case of an execution unit with many registers, this can take up a relatively large amount of computing time and prolong a mode changeover from the performance mode to the comparison mode.
  • the usual method for aligning the states of the execution units is to set all registers in the execution units to zero or to mark their contents invalid.
  • the object of this invention is to shorten this transition from the performance mode to the comparison mode.
  • the embodiments described herein have the advantage over the prior art of enabling faster switching from the performance mode to the compare mode, since the registers of the execution units can be quickly initialized using the methods of the invention, depending on the mode in which they are involved
  • a method is described for determining a start state in a computer system having at least two execution units, switching between a performance mode and a comparison mode, and when switching from the performance mode to the compare mode, a first execution unit generates a start state for the compare mode in that the second execution unit takes over the generated start state of the first execution unit for generating the start state.
  • At least one memory or memory area assigned to the respective execution unit is advantageously assigned at least one predefinable value.
  • the generated start state of the first execution unit is copied into a memory or memory area, and the second execution unit takes over this generated start state from it.
  • the generated start state of the first execution unit is taken over by the second execution unit via a special communication channel.
  • a device for determining a start state in a computer system having at least two execution units is described, wherein
  • Switching means and comparing means are included and is switched between a performance mode and a comparison mode and when switching from the performance mode in the comparison mode, a first execution unit generates a start state for the comparison mode, characterized in that the device is configured such that a start state of the first Execution unit is provided so that the second execution unit for generating the start state takes over the generated start state of the first execution unit.
  • a memory or memory area assigned to the respective execution unit is contained and the apparatus is configured in such a way that it is assigned at least one predeterminable value in the start state.
  • a memory or memory area is included and the generated start state of the first execution unit is copied into this memory or memory area and the second execution unit takes over this generated start state from this.
  • the at least one memory or memory area is a register.
  • a special communication channel is included and the device is configured in such a way that the generated start state of the first execution unit is dependent on the second one
  • Figure 1 shows the general structure of a processor with two execution units and a comparison unit.
  • FIG. 2 shows a possible structure of an execution unit with two different register groups and the processing logic.
  • FIG. 3 shows a possible structure of an execution unit with two different register sets and the processing logic.
  • the register sets are in turn divided into two different groups.
  • FIG. 4 shows two execution units with their internal registers, a buffer and a connection between the execution units for transmitting the internal states.
  • FIG. 5 shows two execution units with their internal registers and a buffer for reading out the internal states for the start state of the comparison mode.
  • Figure 6 shows the structure of a register with user and control data.
  • FIG. 7 shows a multiprocessor with two execution units, as well as the internal one
  • FIG. 8 shows a multiprocessor system with two execution units, their internal registers and a special register
  • a processor a core, a CPU, as well as an FPU (Floating Point Unit), a DSP (Digital Signal Processor), a coprocessor or an ALU (Arithmetic Logical Unit) may be referred to as an execution unit.
  • FPU Floating Point Unit
  • DSP Digital Signal Processor
  • ALU Arimetic Logical Unit
  • FIG. 1 shows a processor system CLOOO which can switch between a comparison mode and a performance mode, consisting of two execution units ClOOa and ClOOb.
  • the execution units are identical.
  • Both execution units ClOOa and ClOOb each have an interface C 110a or C 11 Ob to the system bus, via which, for example, access to storage media such as e.g. RAM, ROM, Flash or peripheral devices.
  • storage media such as e.g. RAM, ROM, Flash or peripheral devices.
  • the output signals of the execution units C 100a, ClOOb are compared with each other via the unit C 120.
  • This comparison preferably takes place with exact clocking or with a fixed clock offset, this means that in each clock the output signals of the at least two execution units C100a, C100b are compared by the unit C120. If there is a difference between the compared signals, then an error signal is generated by the unit C 120.
  • the input signals of the execution units ClOOa and ClOOb can additionally be compared. If the processor system ClOOO is in the performance mode, the comparison unit C 120 is not active and no error signal is generated if there are differences in the output signals of the execution units.
  • the deactivation of the comparison unit can be realized in various ways:
  • a comparison by the unit C 120 is not performed.
  • the internal state of the two execution units C100a and C100b is identical to the beginning of the comparison mode, ie the time at which the comparator C120 is activated.
  • the state at the beginning of the comparison mode from the starting in the comparison mode, the calculations start as the start state.
  • the states in the execution units must be identical so that in the error-free case, at no time in the comparison mode, the signals compared by C 120 have differences. Different states of the execution units in the comparison mode will usually lead to a different output signal being generated.
  • Output signals would detect the comparator as an error, although the same input signals are present and no error to be detected in the processing has occurred.
  • FIG. 2 describes a possible implementation of the execution unit C100. It contains at least two different groups of registers ClOl and C 102 and an internal logic C 103. The group of registers ClOl can be marked as invalid. This means that the internal logic C 103 of the execution unit recognizes when accessing an invalid marked register of this group that the content for this
  • Register must be recalculated; for example by reloading from RAM, ROM, Flash or by recalculation. Registers from the other group C 102 always have valid content. The working registers of an execution unit belong, for example, to this group. If a change from the performance mode to the comparison mode takes place, these registers from ClO1 and C 102 must be identical in both execution units ClOO, as already mentioned.
  • This condition for the register group ClO1, CI 02 does not necessarily have to be valid from the moment of switching from the performance mode to the comparison mode, but not later than the first read access to two identical registers in the execution units ClOO after switching to the compare mode.
  • a common method is to assign a fixed value to all registers of group C 102 in good time before or after switching to comparison mode. Regardless of this, registers in the ClOl group are marked as invalid when switching to the compare mode. If an execution unit ClOO is constructed as in FIG. 3 according to ClOOc, this process can be accelerated by using two sets of registers ClOIa, C102a and ClOIb, C102b in each of the execution units.
  • FIG. 4 A further possibility of accelerating the switching over from the performance mode to the comparison mode is shown in FIG. It consists of copying the internal status C104d resp. C104e from an execution unit ClOOd, ClOOe to the other execution unit ClOOd or ClOOe.
  • C104d at ClOOd and C104e at ClOOe which is ready earlier in time, are initialized before switching to the values which are required in the comparison mode, then the internal state of a second, successive execution unit can be adjusted. by assuming the state of the first execution unit. If, for example, the execution unit ClOOd is ready earlier for a changeover than the execution unit ClOOe, then during the switchover the state C104d is copied to C104e.
  • This copying of the internal state can be done by directly using a connection C300 between the two execution units over which the internal state is copied.
  • the condition may be of a first, earlier than earlier unit are copied into a (fast-bound) cache C200, from which a second, temporally following execution unit takes over the state into the internal registers.
  • the initialization of the internal states for the compare mode is described by copying the register contents from a memory area with a fast connection. It is assumed that at the beginning of the performance mode, the internal state C104f, C 104g of the at least two execution units Cl00f, Cl00g are always set to exactly one defined value. This value is stored in a memory C400, which has the fastest possible connection to the execution units ClOOf, ClOOg and thus to the registers C104f, C104g. This memory is preferably non-volatile.
  • volatile memory is also possible if the initialization state for the performance mode stored in the memory is copied from a non-volatile memory during the initialization of the multiprocessor system, is received by an external data source or is generated by the multiprocessor system. To switch or when switching from the performance mode to the comparison mode, the memory is in memory
  • partial states are marked which do not have to be adjusted between the execution units when switching to the comparison mode. It is not always necessary to align all registers of the execution units when switching from the performance mode to the comparison mode. In order not to erroneously detect an error in comparison mode, only the registers of one execution unit need to be aligned with the registers of a second execution unit that are actually used in the compare mode. Especially in architectures that provide a large number of registers in the execution units, this is the case or can be considered in the software development as a constraint. The number of registers used in a comparison mode can be determined in any case. If all of them are used, it is not necessary to match all registers, only the ones used. Therefore, it is proposed to provide additional bits in each register.
  • bits can be encoded as to whether or not the contents of this register should be matched with the corresponding registers of the other execution units when switching from a performance mode to a compare mode.
  • a special register may exist whose content defines which The register of one execution unit must be matched with the corresponding registers of the other execution units. The approximation itself can be done independently of the markings via the known or presented here method.
  • FIG. 7 shows a processor system C300 with a plurality of execution units C310, C320 with their registers C311, C321.
  • Each register of C311, C321 consists of n bits (n> 1) with payload data (shown in Figure 6 C2010).
  • control bits In these m-bits is coded whether an adjustment takes place when changing to the comparison mode. In the simplest case, if the control bits consist of only one bit, for example, a value of zero means that an approximation does not have to take place and a value of one implies that an approximation must take place. The evaluation of these bits then takes place when switching from the performance to the comparison mode.
  • FIG. 8 shows another embodiment of the invention with a processor system C400 including execution units C410, C420 with their registers C411, C422.
  • the processor system C400 has a register C430.
  • the content of this register C430 defines which registers of C411, C421 of the execution units C410, C420 need to be adjusted when changing to the compare mode.
  • register C430 may be implemented such that for each potentially C411, C421 register to be matched, one bit in
  • a central register C430 is not provided as shown in FIG. 8, but a register is provided in each execution unit which performs the task of the register C430. This means that in this register is coded which of the registers of the execution unit must be adapted when switching from the performance mode in a comparison mode to the registers of at least one second execution unit. When switching from a performance mode to a comparison mode, however, it must then be ensured that the contents of these special registers are identical in all execution units to be synchronized.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Debugging And Monitoring (AREA)

Abstract

L'invention concerne un procédé permettant de déterminer un état de démarrage pour un système informatique comportant au moins deux unités d'exécution, selon lequel une commutation s'effectue entre un mode de performance et un mode de référence. Lors du passage du mode de performance au mode de référence, une première unité d'exécution produit un état de démarrage pour le mode de référence. Ledit procédé se caractérise en ce que la seconde unité d'exécution prend en charge l'état de démarrage produit par la première unité d'exécution, pour produire l'état de démarrage.
PCT/EP2006/064721 2005-08-08 2006-07-27 Procede et dispositif pour determiner un etat de demarrage pour systeme informatique comportant au moins deux unites d'execution, par prise en charge de l'etat de demarrage Ceased WO2007017394A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE200510037258 DE102005037258A1 (de) 2005-08-08 2005-08-08 Verfahren und Vorrichtung zur Festlegung eines Startzustandes bei einem Rechnersystem mit wenigstens zwei Ausführungseinheiten durch Übernehmen des Startzustandes
DE102005037258.9 2005-08-08

Publications (2)

Publication Number Publication Date
WO2007017394A2 true WO2007017394A2 (fr) 2007-02-15
WO2007017394A3 WO2007017394A3 (fr) 2007-04-26

Family

ID=37596207

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2006/064721 Ceased WO2007017394A2 (fr) 2005-08-08 2006-07-27 Procede et dispositif pour determiner un etat de demarrage pour systeme informatique comportant au moins deux unites d'execution, par prise en charge de l'etat de demarrage

Country Status (2)

Country Link
DE (1) DE102005037258A1 (fr)
WO (1) WO2007017394A2 (fr)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6615366B1 (en) * 1999-12-21 2003-09-02 Intel Corporation Microprocessor with dual execution core operable in high reliability mode
US7085959B2 (en) * 2002-07-03 2006-08-01 Hewlett-Packard Development Company, L.P. Method and apparatus for recovery from loss of lock step

Also Published As

Publication number Publication date
WO2007017394A3 (fr) 2007-04-26
DE102005037258A1 (de) 2007-02-15

Similar Documents

Publication Publication Date Title
DE69215538T2 (de) Verfahren zur verbesserung von partiellen streifenschreib-operationen einer speicherplattenanordnung
DE2428348C2 (de) Verfahren zur Weiterbenutzung eines fehlerhaften Datenspeichers und Einrichtung zur Durchführung dieses Verfahrens
DE69030931T2 (de) Mehrfachsequenzprozessorsystem
WO2007017386A1 (fr) Procede et dispositif pour commander un systeme informatique comprenant au moins deux unites d'execution et une unite de comparaison
WO2007057271A1 (fr) Dispositif et procédé d’élimination de défauts dans un système présentant au moins deux unités d’exécution avec registres
DE102009019961A1 (de) Vorrichtung, Systeme und Verfahren zum effizienten Verwenden von Hardware-Ressourcen für einen Softwaretest
DE68924883T2 (de) Mikroprozessor mit Befehlspipeline.
DE3814875C2 (fr)
DE102011011333B4 (de) Lesen in Peripheriegeräte und schreiben aus Peripheriegeräten mit zeitlich getrennter, redundanter Prozessorausführung
DE69029164T2 (de) Vorrichtung und Verfahren zum Ersetzen der Parität
DE102008024193A1 (de) System mit konfigurierbaren Funktionseinheiten und Verfahren
DE3786853T2 (de) Gerät zur Erkennung und Klassifizierung von Steuerwortfehlern.
DE102005037230A1 (de) Verfahren und Vorrichtung zur Überwachung von Funktionen eines Rechnersystems
EP1915686B1 (fr) Procede et dispositif pour fixer un etat de depart dans un systeme de calcul comprenant au moins deux unites d'execution par marquage de registres
EP1817662B1 (fr) Procede et dispositif de commutation de mode de fonctionnement d'un systeme multiprocesseur par l'intermediaire d'au moins un signal externe
WO2007017394A2 (fr) Procede et dispositif pour determiner un etat de demarrage pour systeme informatique comportant au moins deux unites d'execution, par prise en charge de l'etat de demarrage
EP1917590A1 (fr) Procede et dispositif pour determiner un etat de demarrage dans un systeme informatique comprenant au moins deux unites d'execution par commutation d'ensembles de registres
WO2007057270A1 (fr) Unite commandee par programme et procede d'utilisation
WO2007017372A1 (fr) Procede et dispositif pour piloter un systeme de calcul comprenant au moins deux unites d'execution
WO2007017363A1 (fr) Procede et dispositif de commutation dans un systeme de calcul comprenant au moins deux unites d'execution au moyen d'informations binaires dans un registre
DE102005037232A1 (de) Verfahren und Vorrichtung zur Analyse von Abläufen in einem Rechnersystem mit mehreren Ausführungseinheiten
DE60109644T2 (de) Vorrichtung und verfahren zur erkennung und korrektur von speicherfehlern in einer elektronischen vorrichtung
DE3750608T2 (de) Datenverarbeitungssystem mit einer Bedienungsrechnerhierarchie.
EP1915674B1 (fr) Procede et dispositif pour commander un systeme informatique comprenant au moins deux unites d'execution et au moins deux groupes d'etats internes
DE102010031017A1 (de) Verfahren zur Überwachung des Programmablaufs eines Prozessors

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase

Ref document number: 06778014

Country of ref document: EP

Kind code of ref document: A2