WO2007076063A2 - High mobility power metal-oxide semiconductor field-effect transistors - Google Patents

High mobility power metal-oxide semiconductor field-effect transistors Download PDF

Info

Publication number
WO2007076063A2
WO2007076063A2 PCT/US2006/049133 US2006049133W WO2007076063A2 WO 2007076063 A2 WO2007076063 A2 WO 2007076063A2 US 2006049133 W US2006049133 W US 2006049133W WO 2007076063 A2 WO2007076063 A2 WO 2007076063A2
Authority
WO
WIPO (PCT)
Prior art keywords
channel
plane
mosfet
trench
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2006/049133
Other languages
French (fr)
Other versions
WO2007076063A3 (en
Inventor
Deva Pattanayak
Kuo-In Chen
The-Tu Chau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vishay Siliconix Inc
Original Assignee
Vishay Siliconix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vishay Siliconix Inc filed Critical Vishay Siliconix Inc
Priority to CN200680052188.8A priority Critical patent/CN101336483B/en
Priority to KR1020117030811A priority patent/KR101261962B1/en
Priority to KR1020087017039A priority patent/KR101133510B1/en
Priority to JP2008547639A priority patent/JP2009521808A/en
Priority to EP06848908A priority patent/EP1966827A4/en
Publication of WO2007076063A2 publication Critical patent/WO2007076063A2/en
Publication of WO2007076063A3 publication Critical patent/WO2007076063A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/405—Orientations of crystalline planes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2926—Crystal orientations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3258—Crystal orientation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3466—Crystal orientation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts

Definitions

  • Embodiments of the present invention relate to the design and fabrication of semiconductors. More specifically, embodiments of the present invention relate to systems and methods for high mobility power metal-oxide semiconductor field effect transistors.
  • the on-state (or "on") resistance of a MOSFET (metal-oxide semiconductor field-effect transistor) device is an important figure of merit, especially for power devices. For example, when such a device is on, or conducting, a portion of the system power is lost due to resistance heating in the device. This leads to deleteriously decreased efficiency. Such resistance heating may also lead to heat dissipation problems, which in turn may lead to system overheating and/or decreased reliability. Consequently, devices with low on resistances are much desired.
  • the on resistance of a MOSFET (metal -oxide semiconductor field- effect transistor) device comprises mostly resistance of the channel, the drift layer and the substrate components. For low voltage MOSFETs 3 the channel resistance component provides a dominant contribution.
  • the channel resistance is inversely proportional to the mobility of the carriers in the channel.
  • the mobility of the carriers in the channel depends upon the crystal plane and the direction of current flow and this dependence is different for different types of carriers, e.g., electrons versus holes.
  • MOSFETs may be fabricated in crystalline Silicon. Geometry related to a crystal lattice is generally described in terms of the Miller index, which references the crystallographic axes of a crystal, e.g., a, b and c. As a crystal is periodic, there exist families of equivalent directions and planes. Herein, a plane, e.g., a surface of a wafer sliced from a crystal ingot, is described enclosed within parenthesis, e.g., (abc). This notation describes the (abc) plane and equivalent planes. Directions relative to the crystal lattice are described enclosed within brackets, e.g., [abc]. This notation describes the [abc] direction and equivalent directions.
  • (110) crystalline plane depends on the direction of current flow being maximum in the [110] direction (D. Colman et al., Journal of Applied Physics, pp. 1923-1931, 1968). Their experimental results are shown in the graph of Figure 1 (conventional art). From the graph of Figure 1, it is evident that compared to the conventional (100) orientation, the hole mobilities in the (110) crystalline plane are increased by more than a factor of two, depending upon the gate bias.
  • Plummer et al. have also reported (1980 IEDM, pp. 104-106) that a trench power MOSFET fabricated on (100) wafers with trench side walls parallel to the (1 10) crystalline planes do exhibit higher hole mobility at higher gate voltages than corresponding trench MOSFETs with trench walls parallel to the (110) plane but with the direction of current flow being also in the [100] direction.
  • High mobility P-channel power metal oxide semiconductor field effect transistors are disclosed.
  • a power MOSFET is fabricated such that the holes flow in an inversion/accumulation channel, which is along the (110) crystalline plane, and the current flow is in the [110] direction when a negative potential is applied to the gate with respect to the source.
  • the enhanced channel mobility of holes leads to a reduction of the channel portion of the on-state resistance, thereby advantageously reducing total "on" resistance of the device.
  • a power MOSFET structure includes a gate and a source.
  • the power MOSFET further includes an inversion/accumulation channel, wherein holes flow in said inversion/accumulation channel.
  • the channel is aligned along a (110) crystalline plane and the current flow is in a [110] direction when a negative potential is applied to said gate with respect to said source.
  • Figure 1 illustrates experimental measurements of hole mobility based on crystalline plane orientation.
  • Figure 2 illustrates a conventional wafer that is used to fabricate conventional P channel trench Power MOSFETs.
  • Figures 3, 4, 5, 6 and 7 illustrate formation of trenches in a variety of different trench rotations.
  • Figures 8A 9 8B, 8C and 8D illustrate (110) wafers with a variety of flats, in accordance with embodiments of the present invention.
  • Figure 9 illustrates etched trenches perpendicular to the flat of wafer, in accordance with embodiments of the present invention.
  • Figure 10 illustrates etched trenches that are both parallel and perpendicular to the flat of wafer, in accordance with embodiments of the present invention.
  • Figure 11 illustrates a schematic diagram of a trench MOSFET structure, in accordance with embodiments of the present invention.
  • Figure 12 illustrates a schematic diagram of a planar depletion-mode
  • MOSFET MOSFET
  • Figure 13 illustrates a schematic drawing of a high mobility P channel trench MOSFET device, in accordance with embodiments of the present invention.
  • FIG. 2 illustrates a conventional wafer 200 that may be used to fabricate conventional P channel trench Power MOSFETs.
  • Wafer 200 is described as a (001) wafer with a (001) flat.
  • Wafer 200 may also be described as having a flat in the ⁇ 010> direction.
  • the top surface of wafer 200 is a (100) plane. Tt is to be appreciated that the current flow direction in trench MOSFETs, where the current flow is from the top surface to the bottom surface of a wafer, e.g., wafer 200, will always be in the [100] direction, e.g., into the plane of the drawing, as illustrated in Figure 2.
  • Figures 3, 4, 5, 6 and 7 illustrate formation of trenches in a variety of different trench rotations.
  • Figure 3 illustrates a closed cell trench structure 300.
  • the vertical 310 and horizontal 320 trenches are on equivalent (100) planes.
  • Figure 4 illustrates a closed cell trench structure 400 formed with a 45 degree rotation.
  • the rotated trenches 410 and 420 are on equivalent (110) planes.
  • Figure 5 illustrates a stripe cell trench structure 500.
  • the vertical trenches 510 are on equivalent (100) planes.
  • Figure 6 illustrates a stripe cell trench structure 600 formed with a 45 degree rotation.
  • the rotated trenches 610 are on equivalent (110) planes.
  • Figure 7 illustrates a stripe cell trench structure 700 formed with a -45 degree rotation.
  • the rotated trenches 710 are on equivalent (110) planes.
  • Figures 8A, 8B 5 8C and 8D illustrate ( 110) wafers with a variety of flats, in accordance with embodiments of the present invention. It is to be appreciated that other flats are well suited to embodiments in accordance with the present invention.
  • Wafer 800 of Figure 8A is described as a (110) wafer with a (1 10) flat. A variety of crystalline orientations are illustrated, including [001], [111], and [1 10].
  • the top surface, e.g., as shown in Figure 8A 5 of wafer 800 is a (110) plane.
  • Wafer 810 of Figure 8B is described as a (110) wafer with a (111) flat.
  • the [111] crystalline orientation is illustrated.
  • the top surface, e.g., as shown in Figure 8B, of wafer 810 is a (110) plane.
  • Wafer 820 of Figure 8C is described as a (110) wafer with a (001) flat.
  • the [001] and [110] crystalline orientations are illustrated.
  • the top surface, e.g., as shown in Figure 8C, of wafer 820 is a (110) plane.
  • Wafer 830 of Figure 8D is described as a (1 10) wafer with a (112) flat.
  • the [1 12] crystalline orientation is illustrated.
  • the top surface, e.g., as shown in Figure 8D, of wafer 830 is a (110) plane.
  • MOSFET formed in wafer 800 may have hole current flow in the (110) plane and in the [110] direction.
  • the current flow from the top surface to the bottom surface may be in the [1 10] direction, e.g., into the plane of the drawing, as illustrated in Figure 8A.
  • a trench MOSFET formed in wafer 810 may have hole current flow in the (110) plane and in the [1 11] direction.
  • a trench MOSFET formed in wafer 820 may have hole current flow in the (110) plane and in the [001] direction.
  • a trench MOSFET formed in wafer 830 may have hole current flow in the (110) plane and in the [112] direction.
  • Figure 9 illustrates etched trenches 900 perpendicular to the flat of wafer 800 ( Figure 8A), in accordance with embodiments of the present invention. It is appreciated that trenches 900 are in (110) or equivalent planes. As the wafer surface is (110) plane, the direction of hole current flow is thus also in the [110] direction. It is appreciated that embodiments of the present invention are well suited to trenches formed perpendicular to other flat orientations, e.g., as illustrated in Figures 8B, 8C and/or 8D.
  • Figure 10 illustrates etched trenches 1000 that are both parallel and perpendicular to the flat of wafer 800 ( Figure 8A), in accordance with embodiments of the present invention. It is appreciated that trenches 1000 are in (110) or equivalent planes. As the wafer surface is (110) plane, the direction of hole current flow is thus also in the [110] direction. It is appreciated that embodiments of the present invention are well suited to trenches formed relative to other flat orientations, e.g., as illustrated in Figures 8B, 8C and/or 8D.
  • FIG 11 illustrates a schematic diagram of a trench MOSFET structure 1100, in accordance with embodiments of the present invention.
  • Trench MOSFET structure 1100 comprises a P+ source 1110, an N body 1130 and a P+ drain 1 120.
  • Trench MOSFET structure 1100 may be formed in and on wafer 800 ( Figure 8A), to provide a desirable orientation for both electron and hole flow currents.
  • the crystalline plane directions of trench MOSFET structure 1100 are illustrated in Figure 11. It is to be appreciated that current flow between the source 1110 and drain 1120 of trench MOSFET structure 1100 is in the [110] (or equivalent) direction. It is appreciated that embodiments of the present invention are well suited to trenches formed perpendicular to other flat orientations, e.g., as illustrated in Figures 8B, 8C and/or 8D.
  • Figure 12 illustrates a schematic diagram of a planar depletion-mode
  • Planar DMOSFET P channel structure 1200 comprises a P+ source 1210, an N body 1230 and a P+ drain 1220.
  • Planar DMOSFET P channel structure 1200 may be formed in and on wafer 800 ( Figure 8A), to provide a desirable orientation for both electron and hole flow currents.
  • the crystalline plane directions of planar DMOSFET P channel structure 1200 are illustrated in Figure 12. It is to be appreciated that current flow between the source 1210 and drain 1220 of planar DMOSFET P channel structure 1200 is in the [110] (or equivalent) direction. It is appreciated that embodiments of the present invention are well suited to channel alignment perpendicular to other flat orientations, e.g., as illustrated in Figures 8B, 8C and/or 8D.
  • oxide growth rates are different in different crystalline planes. For example, oxide generally grows faster in the [110] direction compared to in the [100] direction. The surface charge in the (1 10) plane is about twice that in the (100) plane. It is desirable to take these characteristics into account while designing for required threshold voltage of the high mobility MOSFETs.
  • FIG. 13 illustrates a schematic drawing of a high mobility P channel accumulation trench MOSFET 1300, in accordance with embodiments of the present invention.
  • Trench MOSFET 1300 comprises source metal 1310, an insulator 1320, P+ source regions 1330 and an N body 1340.
  • Trench MOSFET 1300 also comprises a polysilicon gate 1350, gate oxide 1390 and a P- drift region 1360.
  • Trench MOSFET 1300 further comprises a substrate 1370 and drain metallization 1380.
  • trench MOSFET 1300 is fabricated in a
  • trench MOSFET 1300 may be formed perpendicular to a (110) flat. It is appreciated that embodiments of the present invention are well suited to trenches formed perpendicular to other flat orientations, e.g., as illustrated in Figures 8B, 8C and/or 8D.
  • trench MOSFET 1300 inverts the channel
  • N body 1340 and accumulates charge in the lightly doped accumulation region (P- drift region 1360) forming a P+ accumulation layer near gate 1350.
  • P- drift region 1360 lightly doped accumulation region
  • the breakdown voltage is supported at the P N junction extending into the drift region.
  • the drift resistance consists of two parallel components: one is the accumulation region resistance and the other is the resistance of the drift region.
  • the accumulation resistance component is less than that of the drift region resistance.
  • the overall resistance of the drift region will be substantially reduced from the corresponding values for conventional accumulation power MOSFET devices due to the current flow being in a (110) plane and a [110] direction.
  • Embodiments in accordance with the present invention provide a system and method for a power MOSFET device with reduced on resistance. Embodiments in accordance with the present invention also provide for systems and methods for a P-Channel Trench Power MOSFET in which the holes are confined to the (110) plane and flow in the [110] direction. Further, embodiments in accordance with the present invention provide for systems and methods for power MOSFETs that are compatible and complementary with existing systems and methods of semiconductor design and manufacturing.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Thin Film Transistor (AREA)

Abstract

High mobility P-channel power metal oxide semiconductor field effect transistors. In accordance with an embodiment of the present invention, a power MOSFET is fabricated such that the holes flow in an inversion/accumulation channel, which is along the (110) crystalline plane, or equivalents, and the current flow is in the [110] direction, or equivalents, when a negative potential is applied to the gate with respect to the source. The enhanced channel mobility of holes leads to a reduction of the channel portion of the on-state resistance, thereby advantageously reducing total 'on' resistance of the device.

Description

HIGH MOBILITY POWER METAL-OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTORS
RELATED APPLICATION
[0001] This Application claims priority to United States Provisional
Application Serial No. 60/753,550, Attorney Docket VISH-8756.PRO, entitled "High Mobility P-Channel Trench Power Metal-Oxide Semiconductor Field Effect Transistors," filed December 22, 2005, to Pattanayak et al., which is hereby incorporated by reference herein in its entirety.
FIELD
[0002] Embodiments of the present invention relate to the design and fabrication of semiconductors. More specifically, embodiments of the present invention relate to systems and methods for high mobility power metal-oxide semiconductor field effect transistors.
BACKGROUND
[0003] The on-state (or "on") resistance of a MOSFET (metal-oxide semiconductor field-effect transistor) device is an important figure of merit, especially for power devices. For example, when such a device is on, or conducting, a portion of the system power is lost due to resistance heating in the device. This leads to deleteriously decreased efficiency. Such resistance heating may also lead to heat dissipation problems, which in turn may lead to system overheating and/or decreased reliability. Consequently, devices with low on resistances are much desired. [0004] The on resistance of a MOSFET (metal -oxide semiconductor field- effect transistor) device comprises mostly resistance of the channel, the drift layer and the substrate components. For low voltage MOSFETs3 the channel resistance component provides a dominant contribution. The channel resistance is inversely proportional to the mobility of the carriers in the channel. In Silicon, the mobility of the carriers in the channel depends upon the crystal plane and the direction of current flow and this dependence is different for different types of carriers, e.g., electrons versus holes.
[0005] MOSFETs may be fabricated in crystalline Silicon. Geometry related to a crystal lattice is generally described in terms of the Miller index, which references the crystallographic axes of a crystal, e.g., a, b and c. As a crystal is periodic, there exist families of equivalent directions and planes. Herein, a plane, e.g., a surface of a wafer sliced from a crystal ingot, is described enclosed within parenthesis, e.g., (abc). This notation describes the (abc) plane and equivalent planes. Directions relative to the crystal lattice are described enclosed within brackets, e.g., [abc]. This notation describes the [abc] direction and equivalent directions.
[0006] The mobility of electrons in Silicon is known to be the maximum in the
(100) crystalline plane and is weakly dependent on the direction of the current flow. In contrast, the mobility of holes is a strong function of both the orientation of the crystalline plane and the direction of the current flow. The mobility of the holes is maximum in the (110) crystalline plane and in the [110] direction.
[0007] It has been known for quite some time that the mobility of holes in the
(110) crystalline plane depends on the direction of current flow being maximum in the [110] direction (D. Colman et al., Journal of Applied Physics, pp. 1923-1931, 1968). Their experimental results are shown in the graph of Figure 1 (conventional art). From the graph of Figure 1, it is evident that compared to the conventional (100) orientation, the hole mobilities in the (110) crystalline plane are increased by more than a factor of two, depending upon the gate bias.
[0008] Plummer et al. have also reported (1980 IEDM, pp. 104-106) that a trench power MOSFET fabricated on (100) wafers with trench side walls parallel to the (1 10) crystalline planes do exhibit higher hole mobility at higher gate voltages than corresponding trench MOSFETs with trench walls parallel to the (110) plane but with the direction of current flow being also in the [100] direction.
[0009] More recently, various authors have reiterated that the hole mobility is highest in the (110) plane and in the [110] direction (H. Irie et al., IEDM, pp. 225-228, 2004 and references therein). A patent for a trench lateral device has also been granted to Wendell P. Noble et al. (US Patent # 6,580,154, issued June 17, 2003).
[0010] However, conventional P-channel trench MOSFET devices are fabricated such that the holes flow in an inversion channel which is along the (100) crystalline plane and the direction of the current flow is in the [100] direction.
[0011] Therefore there exists a need for a power MOSFET device with reduced on resistance. What is additionally needed is a system and method for a P- Channel Trench Power MOSFET in which the holes are confined to the (110) plane and flow in the [110] direction. A further need exists for systems and methods for power MOSFETs that are compatible and complementary with existing systems and methods of semiconductor design and manufacturing. Embodiments of the present invention provide these advantages. SUMMARY OF THE INVENTION
[0012] High mobility P-channel power metal oxide semiconductor field effect transistors are disclosed. In accordance with an embodiment of the present invention, a power MOSFET is fabricated such that the holes flow in an inversion/accumulation channel, which is along the (110) crystalline plane, and the current flow is in the [110] direction when a negative potential is applied to the gate with respect to the source. The enhanced channel mobility of holes leads to a reduction of the channel portion of the on-state resistance, thereby advantageously reducing total "on" resistance of the device.
[0013] In accordance with still another embodiment of the present invention, a power MOSFET structure includes a gate and a source. The power MOSFET further includes an inversion/accumulation channel, wherein holes flow in said inversion/accumulation channel. The channel is aligned along a (110) crystalline plane and the current flow is in a [110] direction when a negative potential is applied to said gate with respect to said source.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. Unless otherwise noted, the drawings are not drawn to scale.
[0015] Figure 1 illustrates experimental measurements of hole mobility based on crystalline plane orientation.
[0016] Figure 2 illustrates a conventional wafer that is used to fabricate conventional P channel trench Power MOSFETs.
[0017] Figures 3, 4, 5, 6 and 7 illustrate formation of trenches in a variety of different trench rotations.
[0018] Figures 8A9 8B, 8C and 8D illustrate (110) wafers with a variety of flats, in accordance with embodiments of the present invention.
[0019] Figure 9 illustrates etched trenches perpendicular to the flat of wafer, in accordance with embodiments of the present invention.
[0020] Figure 10 illustrates etched trenches that are both parallel and perpendicular to the flat of wafer, in accordance with embodiments of the present invention. [0021] Figure 11 illustrates a schematic diagram of a trench MOSFET structure, in accordance with embodiments of the present invention.
[0022] Figure 12 illustrates a schematic diagram of a planar depletion-mode
MOSFET (DMOSFET) P channel structure, in accordance with embodiments of the present invention.
[0023] Figure 13 illustrates a schematic drawing of a high mobility P channel trench MOSFET device, in accordance with embodiments of the present invention.
DETAILED DESCRIPTION
[0024] Reference will now be made in detail to various embodiments of the present invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with these embodiments, it is understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the invention, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be recognized by one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the invention.
[0025] Figure 2 illustrates a conventional wafer 200 that may be used to fabricate conventional P channel trench Power MOSFETs. Wafer 200 is described as a (001) wafer with a (001) flat. Wafer 200 may also be described as having a flat in the <010> direction. The top surface of wafer 200 is a (100) plane. Tt is to be appreciated that the current flow direction in trench MOSFETs, where the current flow is from the top surface to the bottom surface of a wafer, e.g., wafer 200, will always be in the [100] direction, e.g., into the plane of the drawing, as illustrated in Figure 2.
[0026] Figures 3, 4, 5, 6 and 7 illustrate formation of trenches in a variety of different trench rotations. Figure 3 illustrates a closed cell trench structure 300. The vertical 310 and horizontal 320 trenches are on equivalent (100) planes. [0027] Figure 4 illustrates a closed cell trench structure 400 formed with a 45 degree rotation. The rotated trenches 410 and 420 are on equivalent (110) planes.
[0028] Figure 5 illustrates a stripe cell trench structure 500. The vertical trenches 510 are on equivalent (100) planes.
[0029] Figure 6 illustrates a stripe cell trench structure 600 formed with a 45 degree rotation. The rotated trenches 610 are on equivalent (110) planes.
[0030] Figure 7 illustrates a stripe cell trench structure 700 formed with a -45 degree rotation. The rotated trenches 710 are on equivalent (110) planes.
[0031] Experimental examples of die comprising stripe cell trench structure
500 of Figure 5 and die comprising trench structure 600 formed with a 45 degree rotation of Figure 6 have been fabricated. Preliminary analysis shows that the overall resistance of the rotated trench structure 600 formed with a 45 degree rotation, e.g., when the current flow is in the (110) plane, is lower than the conventional art devices with trenches in the (100) planes.
[0032] However, it is to be appreciated that, although current flow may be aligned with a (110) plane of wafer 200, trench current flow is in the [100] direction, as described previously.
[0033 ] Figures 8A, 8B5 8C and 8D illustrate ( 110) wafers with a variety of flats, in accordance with embodiments of the present invention. It is to be appreciated that other flats are well suited to embodiments in accordance with the present invention. Wafer 800 of Figure 8A is described as a (110) wafer with a (1 10) flat. A variety of crystalline orientations are illustrated, including [001], [111], and [1 10]. The top surface, e.g., as shown in Figure 8A5 of wafer 800 is a (110) plane.
[0034] Wafer 810 of Figure 8B is described as a (110) wafer with a (111) flat.
The [111] crystalline orientation is illustrated. The top surface, e.g., as shown in Figure 8B, of wafer 810 is a (110) plane. Wafer 820 of Figure 8C is described as a (110) wafer with a (001) flat. The [001] and [110] crystalline orientations are illustrated. The top surface, e.g., as shown in Figure 8C, of wafer 820 is a (110) plane.
[0035] Wafer 830 of Figure 8D is described as a (1 10) wafer with a (112) flat.
The [1 12] crystalline orientation is illustrated. The top surface, e.g., as shown in Figure 8D, of wafer 830 is a (110) plane.
[0036] In accordance with embodiments of the present invention, a trench
MOSFET formed in wafer 800 (Figure 8A) may have hole current flow in the (110) plane and in the [110] direction. For example, the current flow from the top surface to the bottom surface may be in the [1 10] direction, e.g., into the plane of the drawing, as illustrated in Figure 8A.
[0037] In accordance with other embodiments of the present invention, a trench MOSFET formed in wafer 810 (Figure 8B) may have hole current flow in the (110) plane and in the [1 11] direction. [0038] In accordance with alternative embodiments of the present invention, a trench MOSFET formed in wafer 820 (Figure 8C) may have hole current flow in the (110) plane and in the [001] direction.
[0039] In accordance with still other embodiments of the present invention, a trench MOSFET formed in wafer 830 (Figure 8D) may have hole current flow in the (110) plane and in the [112] direction.
[0040] Figure 9 illustrates etched trenches 900 perpendicular to the flat of wafer 800 (Figure 8A), in accordance with embodiments of the present invention. It is appreciated that trenches 900 are in (110) or equivalent planes. As the wafer surface is (110) plane, the direction of hole current flow is thus also in the [110] direction. It is appreciated that embodiments of the present invention are well suited to trenches formed perpendicular to other flat orientations, e.g., as illustrated in Figures 8B, 8C and/or 8D.
[0041] Figure 10 illustrates etched trenches 1000 that are both parallel and perpendicular to the flat of wafer 800 (Figure 8A), in accordance with embodiments of the present invention. It is appreciated that trenches 1000 are in (110) or equivalent planes. As the wafer surface is (110) plane, the direction of hole current flow is thus also in the [110] direction. It is appreciated that embodiments of the present invention are well suited to trenches formed relative to other flat orientations, e.g., as illustrated in Figures 8B, 8C and/or 8D.
[0042] Figure 11 illustrates a schematic diagram of a trench MOSFET structure 1100, in accordance with embodiments of the present invention. Trench MOSFET structure 1100 comprises a P+ source 1110, an N body 1130 and a P+ drain 1 120. Trench MOSFET structure 1100 may be formed in and on wafer 800 (Figure 8A), to provide a desirable orientation for both electron and hole flow currents. The crystalline plane directions of trench MOSFET structure 1100 are illustrated in Figure 11. It is to be appreciated that current flow between the source 1110 and drain 1120 of trench MOSFET structure 1100 is in the [110] (or equivalent) direction. It is appreciated that embodiments of the present invention are well suited to trenches formed perpendicular to other flat orientations, e.g., as illustrated in Figures 8B, 8C and/or 8D.
[0043] Figure 12 illustrates a schematic diagram of a planar depletion-mode
MOSFET (DMOSFET) P channel structure 1200, in accordance with embodiments of the present invention. Planar DMOSFET P channel structure 1200 comprises a P+ source 1210, an N body 1230 and a P+ drain 1220. Planar DMOSFET P channel structure 1200 may be formed in and on wafer 800 (Figure 8A), to provide a desirable orientation for both electron and hole flow currents. The crystalline plane directions of planar DMOSFET P channel structure 1200 are illustrated in Figure 12. It is to be appreciated that current flow between the source 1210 and drain 1220 of planar DMOSFET P channel structure 1200 is in the [110] (or equivalent) direction. It is appreciated that embodiments of the present invention are well suited to channel alignment perpendicular to other flat orientations, e.g., as illustrated in Figures 8B, 8C and/or 8D.
[0044] It is appreciated that oxide growth rates are different in different crystalline planes. For example, oxide generally grows faster in the [110] direction compared to in the [100] direction. The surface charge in the (1 10) plane is about twice that in the (100) plane. It is desirable to take these characteristics into account while designing for required threshold voltage of the high mobility MOSFETs.
[0045] Figure 13 illustrates a schematic drawing of a high mobility P channel accumulation trench MOSFET 1300, in accordance with embodiments of the present invention. Trench MOSFET 1300 comprises source metal 1310, an insulator 1320, P+ source regions 1330 and an N body 1340. Trench MOSFET 1300 also comprises a polysilicon gate 1350, gate oxide 1390 and a P- drift region 1360. Trench MOSFET 1300 further comprises a substrate 1370 and drain metallization 1380.
[0046] It is to be appreciated that trench MOSFET 1300 is fabricated in a
[110] direction, as indicated in Figure 13. In accordance with embodiments of the present invention, trench MOSFET 1300 may be formed perpendicular to a (110) flat. It is appreciated that embodiments of the present invention are well suited to trenches formed perpendicular to other flat orientations, e.g., as illustrated in Figures 8B, 8C and/or 8D.
[0047] During current conduction, trench MOSFET 1300 inverts the channel
(N body 1340) and accumulates charge in the lightly doped accumulation region (P- drift region 1360) forming a P+ accumulation layer near gate 1350. Hence, current flows in an inversion layer within N body 1340 as well as within the accumulation layer formed next to gate 1350.
[0048] The breakdown voltage is supported at the P N junction extending into the drift region. However, unlike the conventional trench MOSFET, the drift resistance consists of two parallel components: one is the accumulation region resistance and the other is the resistance of the drift region. The accumulation resistance component is less than that of the drift region resistance. In accordance with embodiments of the present invention, the overall resistance of the drift region will be substantially reduced from the corresponding values for conventional accumulation power MOSFET devices due to the current flow being in a (110) plane and a [110] direction.
[0049] In this novel MOSFET design, by fabricating a MOSFET with the plane of the accumulation layer as (HO)5 and direction of accumulation layer as [110], the accumulation layer resistance will be greatly reduced, e.g., by a factor of about two.
[0050] Embodiments in accordance with the present invention provide a system and method for a power MOSFET device with reduced on resistance. Embodiments in accordance with the present invention also provide for systems and methods for a P-Channel Trench Power MOSFET in which the holes are confined to the (110) plane and flow in the [110] direction. Further, embodiments in accordance with the present invention provide for systems and methods for power MOSFETs that are compatible and complementary with existing systems and methods of semiconductor design and manufacturing.
[0051] Various embodiments of the invention, high mobility P-channel power metal oxide semiconductor field effect transistors, are thus described. While the present invention has been described in particular embodiments, it should be appreciated that the invention should not be construed as limited by such embodiments, but rather construed according to the below claims.

Claims

CLAIMSWhat is claimed is:
1. A vertical trench MOSFET wherein hole current is restricted to flow in a (110) plane and in a direction selected from the group comprising [110], [111], [112], [001] and their equivalents.
2. A vertical trench MOSFET of Claim 1 fabricated in a (110) wafer.
3. A vertical trench MOSFET of Claim 2 wherein said hole current is responsive to applying a negative voltage potential to a gate of said MOSFET device with respect to a source of said MOSFET.
4. A channel structure for a planar DMOSFET comprising: a P channel; a silicon wafer having a surface orientation in the [110] direction; a current flow in a (110) plane; and a current flow in a direction selected from the group comprising [110], [111], [112], [001] and their equivalents.
5. A power MOSFET structure comprising: a gate; a source; an inversion/accumulation channel; wherein holes flow in said inversion/accumulation channel; wherein said channel is aligned along a (110) crystalline plane; and wherein said flow is in a direction selected from the group comprising
[110], [111], [112], [001] and their equivalents when a negative potential is applied to said gate with respect to said source.
6. A method of fabricating a trench MOSFET, said method comprising: utilizing a silicon wafer having a surface orientation in a direction selected from the group comprising [110], [111], [112], [001] and their equivalents; and etching a trench in a (110) plane or equivalent plane.
7. A method of Claim 6 wherein said trench MOSFET comprises a current flow in the inversion channel which is in the (110) plane or equivalent planes and in the [110] direction when operated with a negative voltage potential applied to a gate of said MOSFET device with respect to its source.
PCT/US2006/049133 2005-12-22 2006-12-22 High mobility power metal-oxide semiconductor field-effect transistors Ceased WO2007076063A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN200680052188.8A CN101336483B (en) 2005-12-22 2006-12-22 High Mobility Power Metal Oxide Semiconductor Field Effect Transistors
KR1020117030811A KR101261962B1 (en) 2005-12-22 2006-12-22 High mobility power metal-oxide semiconductor field-effect transistors
KR1020087017039A KR101133510B1 (en) 2005-12-22 2006-12-22 High mobility power metal-oxide semiconductor field-effect transistors
JP2008547639A JP2009521808A (en) 2005-12-22 2006-12-22 High mobility power metal oxide semiconductor field effect transistor
EP06848908A EP1966827A4 (en) 2005-12-22 2006-12-22 METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS WITH HIGH MOBILITY PERFORMANCE

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US75355005P 2005-12-22 2005-12-22
US60/753,550 2005-12-22

Publications (2)

Publication Number Publication Date
WO2007076063A2 true WO2007076063A2 (en) 2007-07-05
WO2007076063A3 WO2007076063A3 (en) 2007-09-07

Family

ID=38218686

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/049133 Ceased WO2007076063A2 (en) 2005-12-22 2006-12-22 High mobility power metal-oxide semiconductor field-effect transistors

Country Status (7)

Country Link
US (2) US9425043B2 (en)
EP (1) EP1966827A4 (en)
JP (1) JP2009521808A (en)
KR (2) KR101133510B1 (en)
CN (2) CN104064475B (en)
TW (1) TWI489557B (en)
WO (1) WO2007076063A2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009038977A1 (en) * 2007-09-17 2009-03-26 Dsm Solutions, Inc. System and method for enabling higher hole mobility in a jfet
JP4989650B2 (en) * 2006-07-31 2012-08-01 日本ガス合成株式会社 Catalyst for producing liquefied petroleum gas, and method for producing liquefied petroleum gas using the catalyst

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7635637B2 (en) * 2005-07-25 2009-12-22 Fairchild Semiconductor Corporation Semiconductor structures formed on substrates and methods of manufacturing the same
US8409954B2 (en) 2006-03-21 2013-04-02 Vishay-Silconix Ultra-low drain-source resistance power MOSFET
US20090035911A1 (en) * 2007-07-30 2009-02-05 Willy Rachmady Method for forming a semiconductor device having abrupt ultra shallow epi-tip regions
US8101500B2 (en) * 2007-09-27 2012-01-24 Fairchild Semiconductor Corporation Semiconductor device with (110)-oriented silicon
US8039877B2 (en) * 2008-09-09 2011-10-18 Fairchild Semiconductor Corporation (110)-oriented p-channel trench MOSFET having high-K gate dielectric
US10026835B2 (en) 2009-10-28 2018-07-17 Vishay-Siliconix Field boosted metal-oxide-semiconductor field effect transistor
CN102130005A (en) * 2010-01-20 2011-07-20 上海华虹Nec电子有限公司 Preparation method of trench PMOS (positive-channel metal oxide semiconductor) enabling side wall of trench to be (110) surface
US8513798B2 (en) 2010-09-09 2013-08-20 Infineon Technologies Ag Power semiconductor chip package
US8461645B2 (en) 2011-03-16 2013-06-11 Infineon Technologies Austria Ag Power semiconductor device
US8816429B2 (en) 2011-07-07 2014-08-26 Fairchild Semiconductor Corporation Charge balance semiconductor devices with increased mobility structures
US9614043B2 (en) 2012-02-09 2017-04-04 Vishay-Siliconix MOSFET termination trench
US9842911B2 (en) 2012-05-30 2017-12-12 Vishay-Siliconix Adaptive charge balanced edge termination
US9887259B2 (en) 2014-06-23 2018-02-06 Vishay-Siliconix Modulated super junction power MOSFET devices
KR102098996B1 (en) 2014-08-19 2020-04-08 비쉐이-실리코닉스 Super-junction metal oxide semiconductor field effect transistor
US20230197732A1 (en) * 2021-12-22 2023-06-22 Intel Corporation Integrated group iii-nitrogen and silicon transistors on the same die

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6580154B2 (en) 1999-08-31 2003-06-17 Micron Technology, Inc. Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction
WO2004105116A1 (en) 2003-05-26 2004-12-02 Yazaki Corporation P-channel power mis field effect transistor and swiching circuit

Family Cites Families (80)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US615389A (en) * 1898-12-06 Wristlet
US671040A (en) * 1900-07-25 1901-04-02 John Thomas Wright Combined cultivator and planter.
US691961A (en) * 1900-10-31 1902-01-28 August G Nelson Alarm-bell.
US4131524A (en) * 1969-11-24 1978-12-26 U.S. Philips Corporation Manufacture of semiconductor devices
JPS58100441A (en) 1981-12-10 1983-06-15 Toshiba Corp Manufacture of semiconductor device
JPS58168258A (en) 1982-03-30 1983-10-04 Nippon Telegr & Teleph Corp <Ntt> Semiconductor integrated circuit device and manufacture thereof
JPS58197839A (en) 1982-05-14 1983-11-17 Toshiba Corp Manufacture of semiconductor device
JPS5935445A (en) 1982-08-24 1984-02-27 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor device
US4605919A (en) * 1982-10-04 1986-08-12 Becton, Dickinson And Company Piezoresistive transducer
JPS6122630A (en) 1984-07-10 1986-01-31 Sony Corp Manufacture of semiconductor device
US4835585A (en) 1984-11-26 1989-05-30 American Telephone And Telegraph Company, At&T Bell Laboratories Trench gate structures
JPS61256739A (en) 1985-05-10 1986-11-14 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPS6292361A (en) * 1985-10-17 1987-04-27 Toshiba Corp Complementary type semiconductor device
US4767722A (en) 1986-03-24 1988-08-30 Siliconix Incorporated Method for making planar vertical channel DMOS structures
JPS62298130A (en) 1986-06-18 1987-12-25 Matsushita Electric Ind Co Ltd Element isolation method
JPS63228710A (en) * 1987-03-18 1988-09-22 Toshiba Corp Semiconductor device
US4799990A (en) 1987-04-30 1989-01-24 Ibm Corporation Method of self-aligning a trench isolation structure to an implanted well region
JPH0810757B2 (en) 1987-05-25 1996-01-31 松下電子工業株式会社 Method for manufacturing semiconductor device
JPS6476755A (en) 1987-09-18 1989-03-22 Hitachi Ltd Semiconductor device
US4758531A (en) 1987-10-23 1988-07-19 International Business Machines Corporation Method of making defect free silicon islands using SEG
JPH0235736A (en) 1988-07-26 1990-02-06 Matsushita Electric Ind Co Ltd semiconductor equipment
EP0354449A3 (en) * 1988-08-08 1991-01-02 Seiko Epson Corporation Semiconductor single crystal substrate
JPH0258248A (en) 1988-08-23 1990-02-27 Seiko Epson Corp Manufacturing method of semiconductor device
US4939557A (en) * 1989-02-15 1990-07-03 Varian Associates, Inc. (110) GaAs microwave FET
JPH0344067A (en) 1989-07-11 1991-02-25 Nec Corp Laminating method of semiconductor substrate
US5182233A (en) * 1989-08-02 1993-01-26 Kabushiki Kaisha Toshiba Compound semiconductor pellet, and method for dicing compound semiconductor wafer
FR2668465B1 (en) 1990-10-30 1993-04-16 Inst Francais Du Petrole PROCESS FOR REMOVAL OF MERCURY OR ARSENIC IN A FLUID IN THE PRESENCE OF A MASS OF MERCURY AND / OR ARSENIC CAPTATION.
JP3131239B2 (en) * 1991-04-25 2001-01-31 キヤノン株式会社 Wiring for semiconductor circuit device and semiconductor circuit device
US5087586A (en) 1991-07-03 1992-02-11 Micron Technology, Inc. Process for creating fully-recessed field isolation regions by oxidizing a selectively-grown epitaxial silicon layer
US5366914A (en) * 1992-01-29 1994-11-22 Nec Corporation Vertical power MOSFET structure having reduced cell area
JPH07176745A (en) * 1993-12-17 1995-07-14 Semiconductor Energy Lab Co Ltd Semiconductor element
US5814858A (en) 1996-03-15 1998-09-29 Siliconix Incorporated Vertical power MOSFET having reduced sensitivity to variations in thickness of epitaxial layer
JPH09283440A (en) 1996-04-12 1997-10-31 Toshiba Corp Method for forming selective epitaxial film
JP3545590B2 (en) * 1997-03-14 2004-07-21 株式会社東芝 Semiconductor device
US6180966B1 (en) * 1997-03-25 2001-01-30 Hitachi, Ltd. Trench gate type semiconductor device with current sensing cell
JP3755228B2 (en) * 1997-04-14 2006-03-15 株式会社ニコン Charged particle beam exposure system
US6373100B1 (en) 1998-03-04 2002-04-16 Semiconductor Components Industries Llc Semiconductor device and method for fabricating the same
JPH11274485A (en) * 1998-03-25 1999-10-08 Nec Kansai Ltd Insulated gate semiconductor device and method of manufacturing the same
EP0996160A1 (en) 1998-10-12 2000-04-26 STMicroelectronics S.r.l. Contact structure for a semiconductor device
US7578923B2 (en) 1998-12-01 2009-08-25 Novellus Systems, Inc. Electropolishing system and process
US6413822B2 (en) 1999-04-22 2002-07-02 Advanced Analogic Technologies, Inc. Super-self-aligned fabrication process of trench-gate DMOS with overlying device layer
GB9917099D0 (en) 1999-07-22 1999-09-22 Koninkl Philips Electronics Nv Cellular trench-gate field-effect transistors
US6483171B1 (en) * 1999-08-13 2002-11-19 Micron Technology, Inc. Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same
US6475864B1 (en) * 1999-10-21 2002-11-05 Fuji Electric Co., Ltd. Method of manufacturing a super-junction semiconductor device with an conductivity type layer
JP4528460B2 (en) * 2000-06-30 2010-08-18 株式会社東芝 Semiconductor element
US6605843B1 (en) 2000-08-11 2003-08-12 Advanced Micro Devices, Inc. Fully depleted SOI device with tungsten damascene contacts and method of forming same
JP4764987B2 (en) * 2000-09-05 2011-09-07 富士電機株式会社 Super junction semiconductor device
US6710403B2 (en) * 2002-07-30 2004-03-23 Fairchild Semiconductor Corporation Dual trench power MOSFET
JP3531613B2 (en) * 2001-02-06 2004-05-31 株式会社デンソー Trench gate type semiconductor device and manufacturing method thereof
JP2002231945A (en) 2001-02-06 2002-08-16 Denso Corp Method for manufacturing semiconductor device
JP3534084B2 (en) 2001-04-18 2004-06-07 株式会社デンソー Semiconductor device and manufacturing method thereof
EP1267415A3 (en) * 2001-06-11 2009-04-15 Kabushiki Kaisha Toshiba Power semiconductor device having resurf layer
US6436791B1 (en) 2001-06-14 2002-08-20 Taiwan Semiconductor Manufacturing Company Method of manufacturing a very deep STI (shallow trench isolation)
US6764906B2 (en) 2001-07-03 2004-07-20 Siliconix Incorporated Method for making trench mosfet having implanted drain-drift region
JP2003115587A (en) * 2001-10-03 2003-04-18 Tadahiro Omi Semiconductor device formed on <110> oriented silicon surface and method of manufacturing the same
EP1302982A1 (en) 2001-10-12 2003-04-16 Infineon Technologies AG Method of producing a vertical field effect transistor device
US6753250B1 (en) 2002-06-12 2004-06-22 Novellus Systems, Inc. Method of fabricating low dielectric constant dielectric films
JP4055504B2 (en) 2002-07-23 2008-03-05 トヨタ自動車株式会社 Semiconductor device
WO2004012234A2 (en) 2002-07-30 2004-02-05 The Regents Of The University Of California Superlattice nanopatterning of wires and complex patterns
JP4158453B2 (en) * 2002-08-22 2008-10-01 株式会社デンソー Semiconductor device and manufacturing method thereof
JP2004146626A (en) * 2002-10-25 2004-05-20 Toshiba Corp Semiconductor device
KR100475025B1 (en) 2002-10-25 2005-03-10 주식회사 하이닉스반도체 Forming method for field oxide of semiconductor device
JP4695824B2 (en) * 2003-03-07 2011-06-08 富士電機ホールディングス株式会社 Manufacturing method of semiconductor wafer
US6844238B2 (en) 2003-03-26 2005-01-18 Taiwan Semiconductor Manufacturing Co., Ltd Multiple-gate transistors with improved gate control
EP1616348A1 (en) 2003-04-17 2006-01-18 X-FAB Semiconductor Foundries AG Monitoring the reduction in thickness as material is removed from a wafer composite and test structure for monitoring removal of material
US6987305B2 (en) 2003-08-04 2006-01-17 International Rectifier Corporation Integrated FET and schottky device
US7022578B2 (en) 2003-10-09 2006-04-04 Chartered Semiconductor Manufacturing Ltd. Heterojunction bipolar transistor using reverse emitter window
US6967112B2 (en) * 2003-12-23 2005-11-22 Sharp Laboratories Of America, Inc. Three-dimensional quantum dot structure for infrared photodetection
US7115920B2 (en) * 2004-04-12 2006-10-03 International Business Machines Corporation FinFET transistor and circuit
US7122412B2 (en) 2004-04-30 2006-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a necked FINFET device
EP1605498A1 (en) 2004-06-11 2005-12-14 S.O.I. Tec Silicon on Insulator Technologies S.A. A method of manufacturing a semiconductor wafer
US7329576B2 (en) 2004-09-02 2008-02-12 Micron Technology, Inc. Double-sided container capacitors using a sacrificial layer
JP2006120789A (en) * 2004-10-20 2006-05-11 Toshiba Corp Semiconductor device
US7371641B2 (en) 2004-10-29 2008-05-13 International Rectifier Corporation Method of making a trench MOSFET with deposited oxide
JP4841829B2 (en) * 2004-11-17 2011-12-21 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US20060108635A1 (en) * 2004-11-23 2006-05-25 Alpha Omega Semiconductor Limited Trenched MOSFETS with part of the device formed on a (110) crystal plane
US20100032857A1 (en) 2005-02-28 2010-02-11 Saint-Gobain Ceramics & Plastics, Inc. Ceramic components, coated structures and methods for making same
US9685524B2 (en) 2005-03-11 2017-06-20 Vishay-Siliconix Narrow semiconductor trench structure
US7868394B2 (en) 2005-08-09 2011-01-11 United Microelectronics Corp. Metal-oxide-semiconductor transistor and method of manufacturing the same
US8409954B2 (en) 2006-03-21 2013-04-02 Vishay-Silconix Ultra-low drain-source resistance power MOSFET

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6580154B2 (en) 1999-08-31 2003-06-17 Micron Technology, Inc. Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction
WO2004105116A1 (en) 2003-05-26 2004-12-02 Yazaki Corporation P-channel power mis field effect transistor and swiching circuit
EP1628337A1 (en) 2003-05-26 2006-02-22 Tadahiro Ohmi P-channel power mis field effect transistor and swiching circuit

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
D. COLMAN ET AL., JOURNAL OF APPLIED PHYSICS, 1968, pages 1923 - 1931
H. IRIE ET AL., IEDM, 2004, pages 225 - 228
NAKAMURA ET AL., THE JAPANESE JOURNAL OF APPLIED PHYSICS, vol. 43, no. 4B, April 2004 (2004-04-01), pages 1723,1728
PLUMMER ET AL., IEDM, 1980, pages 104 - 106
See also references of EP1966827A4

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4989650B2 (en) * 2006-07-31 2012-08-01 日本ガス合成株式会社 Catalyst for producing liquefied petroleum gas, and method for producing liquefied petroleum gas using the catalyst
WO2009038977A1 (en) * 2007-09-17 2009-03-26 Dsm Solutions, Inc. System and method for enabling higher hole mobility in a jfet

Also Published As

Publication number Publication date
EP1966827A2 (en) 2008-09-10
EP1966827A4 (en) 2009-08-05
TWI489557B (en) 2015-06-21
CN104064475A (en) 2014-09-24
KR20120026564A (en) 2012-03-19
WO2007076063A3 (en) 2007-09-07
KR101261962B1 (en) 2013-05-09
US20080220571A1 (en) 2008-09-11
CN104064475B (en) 2017-07-07
US20070262360A1 (en) 2007-11-15
JP2009521808A (en) 2009-06-04
KR101133510B1 (en) 2012-04-05
TW200746314A (en) 2007-12-16
CN101336483B (en) 2014-08-20
US9425043B2 (en) 2016-08-23
KR20080083151A (en) 2008-09-16
US9437424B2 (en) 2016-09-06
CN101336483A (en) 2008-12-31

Similar Documents

Publication Publication Date Title
US9437424B2 (en) High mobility power metal-oxide semiconductor field-effect transistors
TWI805991B (en) Metal-oxide-semiconductor field-effect transistor device
US9876103B2 (en) Semiconductor device and transistor cell having a diode region
JP5907940B2 (en) Semiconductor element
JP5529742B2 (en) Charge balance in MOSFET active and termination regions
CN102165594B (en) Power MOSFETs with strained channels in semiconductor heterostructures on metal substrates
US8492771B2 (en) Heterojunction semiconductor device and method
US20010030354A1 (en) MOS-type semiconductor device and method for making same
CN110828571A (en) Semiconductor device and method for manufacturing the same
US20040036113A1 (en) Silicon carbide n channel MOS semiconductor device and method for manufacturing the same
WO2022135862A1 (en) Silicon carbide power device and method for manufacturing the same
US7476932B2 (en) U-shape metal-oxide-semiconductor (UMOS) gate structure for high power MOS-based semiconductor devices
JP7486571B2 (en) Silicon carbide transistor devices
US20240282810A1 (en) Silicon carbide mosfet device and manufacturing method therefore
CN108257955B (en) Semiconductor device with a plurality of semiconductor chips
JP2008028263A (en) Semiconductor device
CN103872130B (en) Semiconductor devices and its manufacturing method
US12166082B2 (en) Silicon carbide semiconductor power transistor and method of manufacturing the same
CN116978927A (en) Wide band gap semiconductor device
US20240204056A1 (en) Silicon carbide semiconductor device
US20260082628A1 (en) Semiconductor device including a trench gate structure
US20250056869A1 (en) Wide band gap semiconductor device
US20250089343A1 (en) Power semiconductor device including silicon carbide (sic) semiconductor body
US20250089323A1 (en) Vertical power semiconductor device including silicon carbide (sic) semiconductor body
US20070126057A1 (en) Lateral DMOS device insensitive to oxide corner loss

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 2006848908

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2008547639

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 1020087017039

Country of ref document: KR

Ref document number: KR

WWE Wipo information: entry into national phase

Ref document number: 200680052188.8

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 06848908

Country of ref document: EP

Kind code of ref document: A2

WWE Wipo information: entry into national phase

Ref document number: 1020117030811

Country of ref document: KR