WO2007100940A2 - Circuit intégré avec mémoire et procédé de configuration d'une mémoire - Google Patents

Circuit intégré avec mémoire et procédé de configuration d'une mémoire Download PDF

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Publication number
WO2007100940A2
WO2007100940A2 PCT/US2007/060846 US2007060846W WO2007100940A2 WO 2007100940 A2 WO2007100940 A2 WO 2007100940A2 US 2007060846 W US2007060846 W US 2007060846W WO 2007100940 A2 WO2007100940 A2 WO 2007100940A2
Authority
WO
WIPO (PCT)
Prior art keywords
memory
multiplexer
opcode
integrated circuit
bus port
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2007/060846
Other languages
English (en)
Other versions
WO2007100940A3 (fr
Inventor
Douglas M. Shade
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Priority to EP07756395A priority Critical patent/EP1999594A4/fr
Publication of WO2007100940A2 publication Critical patent/WO2007100940A2/fr
Publication of WO2007100940A3 publication Critical patent/WO2007100940A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/262—Arrangements for next microinstruction selection
    • G06F9/268—Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30079—Pipeline control instructions, e.g. multicycle NOP
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching

Definitions

  • the present disclosures relate to integrated circuits, and more particularly, to an integrated circuit with memory and a method of configuring a memory.
  • Figure 1 is a block diagram view of an integrated circuit having memory according to one embodiment of the present disclosure
  • Figure 2 is a block diagram view of a portion of the integrated circuit of Figure 1 in greater detail, according to one embodiment of the present disclosure.
  • Figure 3 is a block diagram view of the memory array of Figure 2 in greater detail, according to one embodiment of the present disclosure.
  • the use of the same reference symbols in different drawings indicates similar or identical items. Skilled artisans will also appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.
  • An "opcode” can refer to the digital program command being operated on by a processor.
  • a "BRA PC+0" opcode can refer to an opcode that causes the processor to branch back to the same location it is currently at and, basically, it causes the processor to march in place.
  • a "hard coded” value can refer to an unchangeable data value such as a constant. Other interpretations may also be possible.
  • Figure 1 illustrates an integrated circuit (10) in which a processor (12) is coupled via a system bus (14) to a memory (16).
  • the memory (16) includes novel functionality according to the embodiments of the present disclosure, as discussed further herein.
  • FIG. 2 illustrates the details associated with region (18) of Figure 1.
  • the system bus (14) generally comprises Address (20) and Data (22) segments.
  • the address portion carries address information out from the processor to peripheral devices, e.g. memory (16).
  • the data portion comprises a bi-direction bus (though it is sometimes implemented as a unidirectional read data and write data pair) that carries data to and from the processor (12).
  • the memory (16) contains a memory array (24), associated control logic (26), and control signaling (28).
  • the memory (16) also contains a multiplexer (30) which selects between its first port (32) and its second port (34) and routes one of these two ports to its output (36) based on the multiplexer control input (38).
  • a hard-coded benign opcode specific to the processor (12) is assigned to the benign opcode input port (34).
  • the multiplexer control input (38) (a.k.a. "Busy” signal) is sourced by the memory control logic (26). Interface between the processor (12) and memory control logic is via the Address (40,20) and Data (42,22) components of the system bus (14).
  • FIG. 3 illustrates a typical application in which the memory (16) comprises a Flash type memory, in this case with four pages (44, 46, 48 and 50), any of which can be secured against erasure.
  • the fourth page of memory (50) is secured from erasure, and contains a "Boot Routine" (52).
  • This secured page of memory (50) contains a series of opcodes (i.e., processor instructions) that instructs the processor (12) to erase all of the unsecured Flash memory array (24), do nothing (i.e., the NOP instructions), and then continue on with the next meaningful instruction.
  • the next meaningful instruction may include, for example, a check to ensure that the unsecured pages (44, 46, 48) were successfully erased, or a series of instructions to write fresh data into one of these erased pages.
  • the processor (12) accepts an opcode that results from the assembly of an instruction such as BRA PC+0 (e.g., branch to the current program counter plus zero).
  • BRA PC+0 e.g., branch to the current program counter plus zero.
  • the processor (12) will be fetching the valid (but benign) substituted opcode and simply march in place.
  • the multiplexer (30) will revert back to its first port (32) and the processor will continue to fetch the opcodes contained in the "Boot Routine" (52), rather than the substituted benign opcode at (34).
  • the embodiments as discussed herein allow for the uninterrupted fetch and execution of opcodes from a memory (16), with no change in program (52) flow or suspension of processor (12) operation, even if the memory array (24) is not able to supply valid opcodes during certain functional states or conditions.
  • the Boot Routine (52) may be any program which instructs the memory (16) to execute a behavior that will cause it to become unavailable to provide valid opcodes for any length of time, including but not limited to: mass erase, page erase, writes, checksum calculations over an address range, or MBIST (Memory Built In Self Test) operations.
  • the memory (16) is not restricted to paged Flash.
  • the memory (16) may be of any type that may not be able to provide valid read access during certain operational states. These states may include: mass erase, page erase, writes, checksum calculations over an address range, or MBIST (Memory Built In Self Test) operations.
  • Flash memory whenever a Flash memory is busy (e.g. erasing, programming, self verifying, etc.) and is unable to present a valid opcode in response to a read command, it instead responds with a (hard coded) benign opcode such as BRA PC+0.
  • a boot (re -programming) program running from a protected segment of flash will occasionally "march in place” (i.e., fetch and execute BRA PC+0) while the flash memory is unable to respond to a read request with a real opcode.
  • an integrated circuit comprising a processor configured for fetching and executing opcodes, a system bus, and a memory coupled to the processor via the system bus.
  • the memory includes logic circuitry for detecting functional states of the memory and wherein the memory (a) supplies one or more programmed opcodes in response to detection of first functional states of the memory, and (b) supplies a hard coded opcode in response to detection of second functional states of the memory.
  • the memory comprises one or more of a Flash, RAM, MRAM, or other suitable memory.
  • the hard coded opcode is configured for enabling an uninterrupted fetch and execution of opcodes by the processor.
  • the uninterrupted fetch and execution of opcodes by the processor occurs with neither (i) a change in a program flow or (ii) a suspension of processor operation.
  • the integrated circuit includes a memory array, a multiplexer coupled to the memory array, and logic circuitry coupled to (a) the memory array and (b) the multiplexer.
  • the multiplexer includes (i) a first bus port coupled to the memory array for receiving programmed opcodes stored in the memory array, (ii) a second bus port for receiving the hard coded opcode, (iii) a control input for receiving a functional state signal from the logic circuitry, and (iv) a multiplexer system bus port. Responsive to the functional state signal on the control input having a first state representative of the first functional states, the multiplexer couples the first bus port to the multiplexer system bus port.
  • the multiplexer couples the second bus port to the multiplexer system bus port.
  • the hard coded opcode can be stored (i) internal to the memory or (ii) external to the memory.
  • the second functional states of the memory can represent one or more of erase, write, self-test, and check-sum, and wherein the first functional states of the memory can represent a functional state other than a second functional state.
  • the hard coded opcode comprises a benign opcode.
  • the benign opcode can include, for example, a branch instruction.
  • the processor further includes a program counter, and wherein the hard coded opcode comprises any opcode that results in the program counter of the processor remaining unchanged.
  • the opcode may include a branch instruction to a memory location given by a current program counter plus zero.
  • the memory includes a routine configured for placing the memory in a second functional state.
  • the routine can comprise one selected from the group consisting of a built-in self test, a check- sum routine, and a boot routine.
  • the routine may reside in a protected portion of the memory.
  • an integrated circuit comprises a memory configured for being coupled via a bus to a processor.
  • the processor is configured for fetching and executing opcodes.
  • the memory includes logic circuitry for detecting functional states of the memory and wherein the memory (a) supplies one or more programmed opcodes in response to detection of first functional states of the memory, and (b) supplies a hard coded opcode in response to detection of second functional states of the memory.
  • the hard coded opcode is configured for enabling uninterrupted fetch and execution of opcodes by the processor with either (i) no change in a program flow or (ii) no suspension of processor operation.
  • the memory includes a memory array and a multiplexer coupled to the memory array.
  • the logic circuitry is coupled to (a) the memory array and (b) the multiplexer.
  • the multiplexer includes (i) a first bus port coupled to the memory array for receiving programmed opcodes stored in the memory array, (ii) a second bus port for receiving the hard coded opcode, (iii) a control input for receiving a functional state signal from the logic circuitry, and (iv) a multiplexer system bus port. Responsive to the functional state signal on the control input having a first state representative of the first functional states, the multiplexer couples the first bus port to the multiplexer system bus port.
  • the multiplexer couples the second bus port to the multiplexer system bus port.
  • the hard coded opcode can be stored (i) internal to the memory or (ii) external to the memory.
  • a method of configuring a memory for being coupled via a bus to a processor wherein the processor is adapted for fetching and executing opcodes from the memory.
  • the method comprises detecting functional states of the memory with logic circuitry, supplying one or more programmed opcodes from the memory in response to detection of first functional states of the memory, and supplying a hard coded opcode from the memory in response to detection of second functional states of the memory.
  • the hard coded opcode is configured for enabling uninterrupted fetch and execution of opcodes by the processor with either (i) no change in a program flow or (ii) no suspension of processor operation.
  • configuring the memory further includes providing a memory array, coupling a multiplexer to the memory array, and coupling the logic circuitry to (a) the memory array and (b) the multiplexer.
  • the multiplexer includes (i) a first bus port coupled to the memory array for receiving programmed opcodes stored in the memory array, (ii) a second bus port for receiving the hard coded opcode, (iii) a control input for receiving a functional state signal from the logic circuitry, and (iv) a multiplexer system bus port. Responsive to the functional state signal on the control input having a first state representative of the first functional states, the multiplexer couples the first bus port to the multiplexer system bus port.
  • the multiplexer couples the second bus port to the multiplexer system bus port. Furthermore, configuring the memory also includes storing the hard coded opcode (i) internal to the memory or (ii) external to the memory.
  • the embodiments of the present disclosure advantageously circumvent the need for either a second physical block of program memory or a mechanism to stall the core while a Flash memory is busy.
  • the embodiments of the present disclosure further allow mission mode reprogramming of a single Flash block microcontroller.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)

Abstract

L'invention concerne un circuit intégré (10) qui comprend un processeur (12) configuré pour récupérer et exécuter des codes d'opération, un bus système (14), et une mémoire (16) couplée au processeur au moyen du bus système. La mémoire comprend un ensemble de circuits logiques (26) pour détecter les différents états fonctionnels de la mémoire. La mémoire: (a) fournit au moins un code d'opération programmé en réponse à la détection des premiers états fonctionnels de la mémoire, et (b) fournit un code d'opération incorporé au programme en réponse à la détection des seconds états fonctionnels de la mémoire.
PCT/US2007/060846 2006-02-28 2007-01-22 Circuit intégré avec mémoire et procédé de configuration d'une mémoire Ceased WO2007100940A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP07756395A EP1999594A4 (fr) 2006-02-28 2007-01-22 Circuit intégré avec mémoire et procédé de configuration d'une mémoire

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/364,104 US7441102B2 (en) 2006-02-28 2006-02-28 Integrated circuit with functional state configurable memory and method of configuring functional states of the integrated circuit memory
US11/364,104 2006-02-28

Publications (2)

Publication Number Publication Date
WO2007100940A2 true WO2007100940A2 (fr) 2007-09-07
WO2007100940A3 WO2007100940A3 (fr) 2008-04-10

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US (1) US7441102B2 (fr)
EP (1) EP1999594A4 (fr)
WO (1) WO2007100940A2 (fr)

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IL180020A (en) 2006-12-12 2013-03-24 Waterfall Security Solutions Ltd Encryption -and decryption-enabled interfaces
IL180748A (en) * 2007-01-16 2013-03-24 Waterfall Security Solutions Ltd Secure archive
US9817665B2 (en) * 2011-03-31 2017-11-14 Silicon Laboratories Inc. System and technique for retrieving an instruction from memory based on a determination of whether a processor will execute the instruction
KR101997079B1 (ko) 2012-07-26 2019-07-08 삼성전자주식회사 가변 저항 메모리를 포함하는 저장 장치 및 그것의 동작 방법
US9635037B2 (en) 2012-09-06 2017-04-25 Waterfall Security Solutions Ltd. Remote control of secure installations
US9419975B2 (en) 2013-04-22 2016-08-16 Waterfall Security Solutions Ltd. Bi-directional communication over a one-way link
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Also Published As

Publication number Publication date
EP1999594A4 (fr) 2009-08-05
EP1999594A2 (fr) 2008-12-10
WO2007100940A3 (fr) 2008-04-10
US20070204140A1 (en) 2007-08-30
US7441102B2 (en) 2008-10-21

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