WO2007108104A1 - Dispositif a semi-conducteurs et son procede de fabrication - Google Patents

Dispositif a semi-conducteurs et son procede de fabrication Download PDF

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Publication number
WO2007108104A1
WO2007108104A1 PCT/JP2006/305596 JP2006305596W WO2007108104A1 WO 2007108104 A1 WO2007108104 A1 WO 2007108104A1 JP 2006305596 W JP2006305596 W JP 2006305596W WO 2007108104 A1 WO2007108104 A1 WO 2007108104A1
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Prior art keywords
region
gate electrode
semiconductor substrate
conductive
channel stop
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Ceased
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English (en)
Japanese (ja)
Inventor
Sachie Tone
Yoshio Matsuzawa
Taiji Ema
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Fujitsu Ltd
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Definitions

  • the present invention relates to a semiconductor device that requires a high breakdown voltage and a method for manufacturing the same, and particularly to a semiconductor device having a transistor structure in which a drain has an offset structure.
  • a MOS transistor will be described as an example of a high breakdown voltage semiconductor element.
  • FIG. 22 and FIGS. 23A to 23D are schematic diagrams showing a conventional high voltage MOS transistor.
  • FIG. 22 is a plan view
  • FIG. 23A is a cross-sectional view along broken line I- ⁇ in FIG. 22
  • FIG. 23B is a cross-sectional view along broken line II— ⁇ ⁇ ⁇ in FIG. 22
  • FIG. 23C is a broken line in FIG. III—A cross-sectional view along ⁇
  • FIG. 23D is a cross-sectional view along the broken line IV—IV ′ in FIG.
  • an element isolation structure here, a field oxide film 102 is formed on a semiconductor substrate 100 by a LOCOS method to define a rectangular element region 103.
  • the well 101 is formed so as to include the element region 103.
  • a strip-like gate electrode 105 is patterned on the element region 103 through the gate insulating film 104 so as to cross the element region 103, and side insulating films are formed on both sides of the gate electrode 105.
  • 111 is formed, and on the surface layer of the element region 103 on both sides of the gate electrode 105, a pair of LDD regions 106 into which impurities are introduced at a low concentration are formed, and overlap with the LD D regions 106, respectively.
  • a source region 107 and a drain region 108 into which impurities are introduced at a higher concentration than these are formed.
  • the source region 107 and the source region 107 are formed in order to prevent charge outflow between the impurity regions with the adjacent semiconductor element through the field oxide film 102.
  • a stop region 109 is formed.
  • the drain region 108 is provided with an LD in order to ensure a high breakdown voltage of the MOS transistor.
  • the channel stop region 109 is also separated from the end of the LDD region 106 by a predetermined distance to ensure a high breakdown voltage.
  • Patent Document 1 Japanese Patent Laid-Open No. 6-216380
  • Patent Document 2 JP 2004-207499 A
  • the element region 103 is spaced apart from its end that is wider than the element region 103 by a certain distance. Then, the semiconductor substrate 100 is ion-implanted with the resist mask 110 covered. Therefore, as shown in FIGS. 23A and 23D, the region between the end of the element region 103 under the gate electrode 105 and the end of the resist mask 110 (removed after the channel stop region 109 is formed). Under 103a, the semiconductor substrate 100 through the field oxide film 102 is in a state where only the well 101 exists.
  • Patent Document 1 discloses a MOS transistor configuration in which a rectangular ring-shaped impurity region is formed in an element region so as to surround a source / drain region by introducing an impurity of an opposite conductivity type to the source / drain region. Yes.
  • the portion corresponding to the gate width of the gate electrode overlaps with the channel stop region, which results in deterioration of transistor characteristics.
  • the resist mask for forming the channel stop region is formed in a concave shape so as to expose a portion corresponding to the region 103a of the element region 103 in FIG. By introducing impurities using this resist mask, a channel stop region can be formed under the element isolation structure corresponding to the region 103a.
  • the hump shown in FIG. 24 is improved.
  • the element isolation structure is transmitted with a high acceleration energy so that the impurity concentration peak is located near the bottom. Need to be injected.
  • a region having a high impurity concentration is formed below the portion corresponding to the gate width of the gate electrode.
  • the presence of this high impurity concentration region causes a change in transistor characteristics.
  • the formation form of the region is unstable due to manufacturing variations, and there is a problem that the variation in transistor characteristics cannot be controlled.
  • the element isolation structure forming method is limited to the LO COS method, and there is an oxidation resistant film pattern when forming the field oxide film. It was necessary to form a channel stop region before performing.
  • the present invention has been made in view of the above-described problems, and suppresses deterioration in transistor characteristics regardless of the method of forming an element isolation structure and the position of the process, and relatively easily and reliably achieves a high breakdown voltage.
  • An object of the present invention is to provide a highly reliable semiconductor device that achieves the above and a manufacturing method thereof.
  • a semiconductor device of the present invention includes an element isolation structure that is formed in an element isolation region on the surface of a semiconductor substrate and demarcates the element region on the semiconductor substrate, and a gate that is formed across the element region.
  • An impurity region is overlapped, and at least one of the conductive regions includes the high impurity region in the low concentration region and the low concentration region.
  • the element isolation structure is formed so that the element region protrudes outward with a width narrower than the gate length at a portion below the gate electrode.
  • a surface conductive region formed by introducing an impurity of a conductivity type opposite to the conductive region is formed in a surface layer of the projecting portion.
  • a method for manufacturing a semiconductor device includes a step of forming an element isolation structure for defining an element region on the semiconductor substrate in an element isolation region on the surface of the semiconductor substrate, and a gate so as to cross the element region. Forming a pair of conductive regions by introducing impurities into the element regions on both sides of the gate electrode, and each of the conductive regions is divided into a low concentration region and a low concentration region, respectively. And a high impurity region having a higher impurity concentration is superimposed, and at least one of the conductive regions is formed in a state where the high impurity region is offset in the low concentration region by an end force of the low concentration region.
  • the element isolation structure has a portion below the gate electrode such that the element region has a protruding portion that is narrower than the gate length and protrudes outward in the portion below the gate electrode.
  • the surface conductive region is formed by introducing an impurity of a conductivity type opposite to the conductive region into the surface layer of the protruding portion.
  • FIG. 1 is a schematic plan view showing a configuration of a high breakdown voltage MOS transistor according to a first embodiment.
  • FIG. 2A is a schematic cross-sectional view taken along broken line ⁇ - ⁇ in FIG.
  • FIG. 2B is a schematic cross-sectional view taken along broken lines ⁇ — ⁇ in FIG.
  • FIG. 2C is a schematic cross-sectional view along the broken line ⁇ _ ⁇ in FIG.
  • FIG. 2D is a schematic cross-sectional view taken along broken line IV-IV ′ in FIG.
  • Fig. 2 ⁇ is a schematic cross-sectional view along the broken line VV 'in Fig. 1.
  • FIG. 3B is a schematic cross-sectional view showing the method of manufacturing the high voltage MOS transistor according to the first embodiment.
  • FIG. 3B is a schematic cross-sectional view showing the method of manufacturing the high voltage MOS transistor according to the first embodiment.
  • FIG. 3C is a schematic cross-sectional view showing the method of manufacturing the high voltage MOS transistor according to the first embodiment.
  • FIG. 3D is a schematic cross-sectional view showing the method of manufacturing the high voltage MOS transistor according to the first embodiment.
  • FIG. 4A is a schematic cross-sectional view showing a method for manufacturing the high voltage MOS transistor according to the first embodiment.
  • FIG. 4B is a schematic cross-sectional view showing the method of manufacturing the high breakdown voltage MOS transistor according to the first embodiment.
  • FIG. 4C is a schematic cross-sectional view showing the method of manufacturing the high voltage MOS transistor according to the first embodiment.
  • FIG. 5A is a schematic cross-sectional view showing a method for manufacturing the high voltage MOS transistor according to the first embodiment.
  • FIG. 5B-1 is a schematic cross-sectional view showing the method of manufacturing the high voltage MOS transistor according to the first embodiment.
  • FIG. 5B-2 is a schematic cross-sectional view showing the method of manufacturing the high voltage MOS transistor according to the first embodiment.
  • FIG. 6A is a schematic cross-sectional view showing a method of manufacturing the high voltage MOS transistor according to the first embodiment.
  • FIG. 6B is a schematic cross-sectional view showing the method of manufacturing the high breakdown voltage MOS transistor according to the first embodiment.
  • FIG. 6C is a schematic cross-sectional view showing the method of manufacturing the high voltage MOS transistor according to the first embodiment.
  • FIG. 7 is a schematic plan view showing the configuration of the high voltage MOS transistor according to the second embodiment.
  • FIG. 8A is a schematic cross-sectional view taken along broken line ⁇ - ⁇ in FIG.
  • FIG. 8B is a schematic cross-sectional view taken along broken lines ⁇ — ⁇ in FIG.
  • FIG. 8C is a schematic cross-sectional view taken along the broken line ⁇ _ ⁇ in FIG.
  • FIG. 8D is a schematic sectional view taken along broken line IV-IV ′ in FIG. 9A]
  • FIG. 9A is a schematic cross-sectional view showing a method of manufacturing a high voltage MOS transistor according to the second embodiment.
  • FIG. 9B is a schematic cross-sectional view showing the method of manufacturing the high breakdown voltage MOS transistor according to the second embodiment.
  • FIG. 9C is a schematic cross-sectional view showing a method for manufacturing the high voltage MOS transistor according to the second embodiment.
  • FIG. 10A is a schematic cross-sectional view showing a method for manufacturing a high voltage MOS transistor according to the second embodiment.
  • FIG. 10B-1 is a schematic cross-sectional view showing a method of manufacturing a high voltage MOS transistor according to the second embodiment.
  • FIG. 10B-2 is a schematic cross-sectional view showing a method of manufacturing a high voltage MOS transistor according to the second embodiment.
  • FIG. 11A is a schematic cross-sectional view showing a method for manufacturing a high voltage MOS transistor according to the second embodiment.
  • FIG. 11B is a schematic cross-sectional view showing the method of manufacturing the high breakdown voltage MOS transistor according to the second embodiment.
  • FIG. 11C is a schematic cross-sectional view showing the method of manufacturing the high voltage MOS transistor according to the second embodiment.
  • FIG. 12A is a schematic cross-sectional view showing a method for manufacturing a high voltage MOS transistor according to the second embodiment.
  • FIG. 12B is a schematic cross-sectional view showing a method for manufacturing the high voltage MOS transistor according to the second embodiment.
  • FIG. 12C is a schematic cross-sectional view showing the method for manufacturing the high voltage MOS transistor according to the second embodiment.
  • FIG. 13 is a schematic plan view showing the configuration of a high voltage MOS transistor according to the third embodiment.
  • FIG. 14A is a schematic cross-sectional view taken along broken line ⁇ ⁇ - ⁇ in FIG.
  • FIG. 14B is a schematic cross-sectional view taken along broken lines ⁇ — ⁇ in FIG.
  • FIG. 14C is a schematic cross-sectional view along broken line III— ⁇ in FIG.
  • FIG. 14D is a schematic sectional view taken along broken line IV-IV ′ in FIG.
  • FIG. 14E is a schematic cross-sectional view along the broken line VV ′ of FIG.
  • FIG. 15A is a schematic cross-sectional view showing a method for manufacturing a high voltage MOS transistor according to the third embodiment.
  • FIG. 15B is a schematic cross-sectional view showing a method for manufacturing a high voltage MOS transistor according to the third embodiment.
  • FIG. 15C is a schematic cross-sectional view showing the method of manufacturing the high voltage MOS transistor according to the third embodiment.
  • FIG. 15D is a schematic cross-sectional view showing the method of manufacturing the high breakdown voltage MOS transistor according to the third embodiment.
  • FIG. 16A-1 is a schematic cross-sectional view showing a method for manufacturing a high voltage MOS transistor according to the third embodiment.
  • FIG. 16A-2 is a schematic cross-sectional view showing a method for manufacturing a high voltage MOS transistor according to the third embodiment.
  • FIG. 16B-1 is a schematic cross-sectional view showing a method of manufacturing a high voltage MOS transistor according to the third embodiment.
  • FIG. 16B-2 is a schematic cross-sectional view showing a method for manufacturing a high voltage MOS transistor according to the third embodiment.
  • FIG. 17 is a schematic plan view showing the configuration of a high voltage MOS transistor according to the fourth embodiment.
  • FIG. 18A is a schematic cross-sectional view along broken line ⁇ - ⁇ in FIG.
  • FIG. 18B is a schematic sectional view taken along broken lines ⁇ ⁇ — ⁇ in FIG.
  • FIG. 18C is a schematic cross-sectional view along the broken line ⁇ _ ⁇ ⁇ ⁇ in FIG.
  • FIG. 18D is a schematic cross-sectional view taken along broken line IV-IV ′ in FIG.
  • FIG. 19 is a schematic plan view showing another example of the structure of the high voltage MOS transistor according to the fourth embodiment.
  • FIG. 20 is a schematic diagram showing a configuration of a high voltage MOS transistor according to the fifth embodiment. It is a top view.
  • FIG. 21A is a schematic cross-sectional view along broken line I ⁇ in FIG.
  • FIG. 21B is a schematic cross-sectional view along broken line II— ⁇ ⁇ ⁇ in FIG.
  • FIG. 22 is a schematic plan view showing a configuration of a high voltage MOS transistor according to a conventional embodiment.
  • FIG. 23A is a schematic cross-sectional view along the broken line ⁇ in FIG.
  • FIG. 23B is a schematic cross-sectional view taken along broken lines ⁇ — ⁇ ⁇ ⁇ in FIG.
  • FIG. 23C is a schematic cross-sectional view taken along broken lines ⁇ ⁇ ⁇ in FIG.
  • FIG. 23D is a schematic sectional view taken along broken line IV-IV ′ in FIG.
  • FIG. 24 is a characteristic diagram showing the relationship between the gate electrode and the drain current.
  • the inventor of the present invention has contrived the following main configuration as a result of intensive studies to suppress the deterioration of transistor characteristics regardless of the method of forming the element isolation structure and the process position. That is, the element isolation structure is formed in a concave shape in the portion under the gate electrode so that the element region has a protruding portion that is narrower than the gate length and protrudes outward in the portion under the gate electrode. Then, for example, an impurity having a conductivity type opposite to that of the conductive region to be the source / drain region is introduced into the surface layer of the protruding portion to form the surface conductive region.
  • a sufficient threshold voltage can be ensured by forming a surface conductive region at least in the protruding portion of the element region below the gate electrode.
  • the protrusion is formed narrower than the gate length, so it does not function as an active region although it is part of the device region. Therefore, even if a channel stop region is formed under the element isolation structure and the end of the channel stop region protrudes from the end of the element isolation structure, a channel stop region is formed below the portion corresponding to the gate width of the gate electrode. There is no stop region (the end of the channel stop region does not reach the portion corresponding to the gate width), and the portion corresponding to the gate width of the gate electrode and the end of the channel stop region are kept apart. Be drunk. Therefore, fluctuation deterioration of the transistor characteristics is suppressed, and stable and sufficient transistor characteristics can be obtained. [0023] Specific embodiments to which the present invention is applied
  • FIG. 1 and 2A to 2E are schematic diagrams showing the configuration of the high-breakdown-voltage MOS transistor according to the first embodiment.
  • FIG. 1 is a plan view
  • FIG. 2A is a cross-sectional view along broken line ⁇ in FIG. 1
  • FIG. 2B is a cross-sectional view along broken line ⁇ ⁇ — ⁇ ⁇ ⁇ in FIG. 1
  • FIG. 2C is a broken line in FIG. — Cross-sectional view along ⁇
  • Figure 2D is a cross-sectional view along IV-IV 'in Figure 1
  • Figure 2E is a broken line V in Figure 1.
  • an element isolation structure here STI, is formed on a silicon semiconductor substrate 1.
  • An STI element isolation structure 7 is formed by the Trench Isolation method, and an element region 10 is defined on the semiconductor substrate 1.
  • the well 21 is formed so as to include the element region 10.
  • a strip-shaped gate electrode 16 is patterned on the element region 10 via the gate insulating film 14 so as to cross the element region 10, and sidewall insulating films 18 are formed on both side surfaces of the gate electrode 16.
  • a pair of LDD regions 19 into which impurities are introduced at a low concentration are formed, so that they overlap with the LDD regions 19, respectively.
  • a source region 24 and a drain region 25 into which impurities are introduced at a high concentration are formed.
  • a channel stop region 23 is formed in which an impurity having a conductivity type opposite to that of the region 24 and the drain region 25 is introduced.
  • the drain region 25 is formed and offset so as to be offset from the end of the LDD region 19 by a predetermined distance in order to ensure the high breakdown voltage of the MOS transistor. This offset As a result, the channel stop region 23 is also separated from the end of the LDD region 19 by a predetermined distance.
  • the STI element isolation structure 7 has a portion under the gate electrode 16 such that the element region 10 has a pair of protrusions 10a protruding outward in the portion under the gate electrode 16. It is formed in a concave shape.
  • the protrusion 10a has a width W narrower than the gate length G of the gate electrode 16 and the expected width.
  • the length L is at least the distance d between the element region 10 and a resist mask 11 for forming a channel stop region 23 described later, and the pattern for forming the element region 10 and the formation of the gate electrode 16 are formed.
  • the dimension is set to allow for a margin, for example, 0 or more so as to satisfy the alignment accuracy with the pattern for use.
  • an impurity having a conductivity type opposite to that of the source region 24 and the drain region 25 is introduced into the surface layer of the protruding portion 10a to form a surface conductive region.
  • a channel dose region 22 is formed in the surface layer of the silicon element region 10 including the protruding portion 10a under the gate electrode 16 as the surface layer conductive region.
  • a sufficient threshold voltage can be secured by forming the channel dose region 22 in the well 21 below the gate electrode 16.
  • the protruding portion 10a is formed narrower than the gate length, it does not function as an active region although it is a part of the element region 10. Therefore, as shown in FIG. 2D, even if the end of the channel stop region 23 protrudes from the end of the STI element isolation structure 7 for the channel stop region 23 formed under the STI element isolation structure 7, the gate electrode The channel stop region 23 does not exist under the portion corresponding to the gate width G of 16 (the
  • the end of the channel stop region 23 does not reach the part corresponding to the gate width G),
  • the portion corresponding to the gate width G of the gate electrode 16 is separated from the end of the channel stop region 23.
  • FIGS. 3A to 6C are schematic cross-sectional views showing the method of manufacturing the high voltage MOS transistor according to this embodiment in the order of steps.
  • FIGS. 3A to 6C each figure except for FIG. 5B-2 is a cross-sectional view taken along the broken line II— ⁇ in FIG. 1, and FIG. 5B-2 is a cross section taken along the broken line IV—IV ′ in FIG. Corresponds to the figure.
  • an oxidation resistant material film 3 is formed on a silicon semiconductor substrate 1 with an insulating film 2 interposed therebetween.
  • an insulating film 2 having a thickness of about 30 nm is formed on the surface of the semiconductor substrate 1 by a thermal oxidation method, and then an oxidation resistant material, for example, silicon nitride is deposited by the CVD method, and the oxidation resistance of a thickness of about lOO nm is deposited.
  • a material film 3 is formed.
  • an isolation groove 4 is formed in the element isolation region.
  • the oxidation-resistant material film 3 and the insulating film 2 are patterned by lithography and dry etching so that the element isolation region is exposed so as to cover a portion to be the element region 10 of the semiconductor substrate 1.
  • the semiconductor substrate 1 is dry-etched to a depth of about 200 nm to 500 nm to obtain a semiconductor substrate
  • An isolation groove 4 is formed in the element isolation region 1.
  • the separation groove 4 has a gate electrode so that the element region 10 has a pair of projecting portions 10a projecting outward under the formation portion of the gate electrode 16 when viewed in plan as shown in FIG. It is formed in a concave shape under 16 formation sites.
  • the insulator 6 is deposited on the entire surface.
  • the inner wall surface of the separation groove 4 is wet-oxidized to form the insulating film 5 having a thickness of about 20 nm.
  • an insulator 6, here a silicon oxide film, is deposited to a thickness of about 300 nm to 800 nm by the CVD method on the entire surface of the semiconductor substrate 1 so as to receive the separation groove 4.
  • the STI element isolation structure 7 is formed.
  • the insulator 6 is CMP (Chemi cal Polishing and flattening by a mechanical polishing method. Then, the remaining oxidation-resistant material film 3 and insulating film 2 are removed, thereby forming the STI element isolation structure 7 that fills the isolation groove 4 with the insulator 6.
  • This STI element isolation structure 7 defines an element region 10 on the semiconductor substrate 1.
  • the STI element isolation structure 7 has a pair of protrusions 10a that protrude outwardly under the formation region of the gate electrode 16, It is formed in a concave shape under the formation site of the gate electrode 16. Thereafter, the insulating film 2 is formed again on the semiconductor substrate 1 by thermal oxidation.
  • impurities for forming wells are introduced into the semiconductor substrate 1.
  • a resist mask 8 is formed so as to expose a part of the element region 10 on the semiconductor substrate 1 and the surrounding STI element isolation structure 7. Then, using the resist mask 8, a P-type impurity, here boron (B + ), is ion-implanted into the semiconductor substrate 1 corresponding to the lower portion of the portion exposed from the resist mask 8.
  • the acceleration energy is 200 keV to 500 keV
  • the dose is 1 ⁇ 10 10 / cm 2 to 1 ⁇ 10 13 / cm 2 .
  • a P-type impurity region 9 is formed.
  • the resist mask 8 is removed by ashing or the like.
  • impurities for forming a channel stop region are introduced into the semiconductor substrate 1.
  • a resist mask 11 is formed so as to surround the element region 10 by being separated from the element region 10 by a predetermined distance on the entire surface of the element region 10 and on the STI element isolation structure 7.
  • the resist mask 11 exposes a ring-shaped portion on the STI element isolation structure 7.
  • a P-type impurity here, boron (B + ) is ion-implanted into the semiconductor substrate 1 corresponding to the lower portion of the portion exposed from the resist mask 11.
  • the calo-speed energy energy is 70 keV to 180 keV
  • the dose is 1 ⁇ 10 10 / cm 2 to 1 ⁇ 10 14 / cm 2 .
  • a P-type impurity region 12 is formed in a portion immediately below the STI element isolation structure 7 in the opening portion of the resist mask 11.
  • the resist mask 11 is removed by ashing or the like.
  • a channel dose region for forming a semiconductor substrate 1 is formed. Impurities are introduced.
  • a resist mask 26 is formed so as to expose the formation site of the gate electrode 16 in the element region 10. Then, using the resist mask 26, a P-type impurity, here boron (B + ), is ion-implanted into the surface layer (here near the surface) of the semiconductor substrate 1 corresponding to the lower part of the portion exposed from the resist mask 26. To do. As ion implantation conditions, the acceleration energy is 10 keV to 50 keV, and the dose is 1 ⁇ 10 10 / cm 2 to 1 ⁇ 10 13 / cm 2 . By this ion implantation, a P-type impurity region 13 is formed. The resist mask 26 is removed by ashing or the like.
  • the gate insulating film 14 and the gate electrode material film 15 are formed.
  • annealing is performed at 1100 ° C. to 1200 ° C. for about 0.5 to 9 hours to activate the P-type impurity regions 9, 12 and 13 implanted into the semiconductor substrate 1. To become sexual.
  • the well 21, the channel dose region 22 and the channel stop region 23 are formed.
  • the gate insulating film 14 is formed in the element region 10 to a film thickness of about 20 nm by thermal oxidation. Thereafter, a gate electrode material film 15, here a polycrystalline silicon film, is deposited to a thickness of about 300 nm by CVD.
  • the gate electrode 16 is patterned.
  • the gate electrode material film 15 is patterned into an electrode shape by lithography and dry etching to form the gate electrode 16.
  • the gate electrode 16 is formed in a pattern so that the channel dose region 22 exists in the lower portion and the protruding portion 10a of the element region is included in the lower portion.
  • a resist mask 27 that exposes part of the element region 10 and the STI element isolation structure 7 is formed, and the resist mask 27 is used to form N-type impurities on both sides of the gate electrode 16 in the element region 10.
  • phosphorus (P + ) is ion-implanted.
  • the conditions for the ion implantation are as follows: Caro-speed energy energy is 70 keV to 150 keV, and dose is 1 X 10 "/ (111 2 to 1 X 10 13 / cm 2 By this ion implantation, an N-type impurity region 17 is formed.
  • the resist mask 27 is removed by ashing or the like.
  • annealing is performed at 900 ° C. to 1000 ° C. for about 10 seconds to 20 seconds to activate phosphorus in the N-type impurity region 17.
  • a pair of LDD regions 19 is formed by this annealing process.
  • an insulator here a silicon oxide film (not shown) is deposited on the entire surface so as to cover the gate electrode 16 by a CVD method to a film thickness of about 500 nm. Then, the entire surface of the silicon oxide film is subjected to anisotropic dry etching (etchback), and the silicon oxide film is left only on both side surfaces of the gate electrode 16 to form a sidewall insulating film 18.
  • the source region 24 and the drain region 25 are formed.
  • a resist mask (not shown) that exposes only the surface of the element region 10 on one side (source formation region) of the gate electrode 16 is formed, and an N-type impurity, here arsenic, is formed using this resist mask.
  • (As + ) ions are implanted.
  • the ion implantation conditions are such that the acceleration energy is 70 keV to 120 keV and the dose is 1 X 10 15 / cm 2 to l X 10 16 / so that it is superimposed on the LDD region 19 at a higher impurity concentration than the L DD region 19. cm 2
  • a resist mask (not shown) that exposes only the surface of the element region 10 on the other side (drain formation region) of the gate electrode 16 is formed.
  • N-type impurities here arsenic (As + ) are ion-implanted.
  • the ion implantation conditions are such that the calo-velocity energy is 70 keV to 120 keV and the dose is 1 X 10 15 / cm to 1 X 10 / cm so that it is superimposed on the LDD region 19 at a higher impurity concentration than the LDD region 19.
  • annealing treatment is performed at 900 ° C to 1000 ° C for about 10 seconds to 20 seconds to activate the ion-implanted phosphorus.
  • a source region 24 and a drain region 25 are formed.
  • the drain region 25 is formed to be offset from the end of the LDD region 19 by a predetermined distance in order to ensure the high breakdown voltage of the MOS transistor.
  • interlayer insulation films, contact holes, gate electrodes 16, source regions 24, drain regions 25, wirings connected to the drain region 25, etc. are sequentially formed. Type MOS transistor is completed.
  • FIG. 7 and 8A to 8D are schematic views showing the configuration of the high voltage MOS transistor according to the second embodiment.
  • FIG. 7 is a plan view
  • FIG. 8A is a sectional view taken along the broken line ⁇ - ⁇ in FIG. 7
  • FIG. 8B is a sectional view taken along the broken line ⁇ — ⁇ in FIG. 7
  • FIG. 8D is a cross-sectional view taken along the broken line IV-IV ′ of FIG.
  • an element isolation structure here, a field oxide film 39 by a L OCOS (LOCal Oxidation of Silicon) method is formed on a silicon semiconductor substrate 31, and an element region 30 is defined on the semiconductor substrate 31. Is done.
  • the well 41 is formed so as to include the element region 30.
  • a strip-shaped gate electrode 47 is patterned on the element region 30 through the gate insulating film 45 so as to cross the element region 30, and sidewall insulating films 52 are formed on both side surfaces of the gate electrode 47.
  • a pair of LDD regions 51 into which impurities are introduced at a low concentration are formed, so that they overlap with the LDD regions 51, respectively.
  • a source region 53 and a drain region 54 into which impurities are introduced at a high concentration are formed.
  • a source region is formed in order to prevent charge outflow between the impurity regions with the adjacent MOS transistor via the field oxide film 39.
  • a channel stop region 42 into which impurities of the opposite conductivity type to 53 and drain region 54 are introduced is formed.
  • the drain region 54 is formed so as to be offset from the end of the LDD region 51 by a predetermined distance in order to ensure the high breakdown voltage of the MOS transistor. This offset As a result, the channel stop region 42 is also separated from the end of the LDD region 51 by a predetermined distance.
  • the field oxide film 39 is formed at a portion below the gate electrode 47 so that the element region 30 has a pair of protruding portions 30a protruding outward at the portion below the gate electrode 47. It is formed in a concave shape.
  • the protrusion 30a has a width W that is narrower than the gate length G of the gate electrode 47 and is expected.
  • the length L is at least a distance d between the element region 30 and a resist mask 36 for forming a channel stop region 42 described later, and the pattern for forming the element region 30 and the formation of the gate electrode 47 are formed.
  • the dimension is set to allow for a margin, for example, 0 or more so as to satisfy the alignment accuracy with the pattern for use.
  • an impurity having a conductivity type opposite to that of the source region 53 and the drain region 54 is introduced into the surface layer of the protrusion 30a to form a surface conductive region.
  • a channel dose region 48 is formed in the surface layer of the silicon element region 30 including the protruding portion 30a under the gate electrode 47 as the surface conductive region.
  • a sufficient threshold voltage can be secured by forming the channel dose region 48 in the wall 41 under the gate electrode 47.
  • the projecting portion 30a is formed narrower than the gate length, so it does not function as an active region although it is a part of the device region 30. Therefore, as shown in FIG. 8D, for the channel stop region 42 formed under the field oxide film 39, even if the end of the channel stop region 42 protrudes from the end of the field oxide film 39, the gate electrode 47 The channel stop region 42 does not exist under the portion corresponding to the gate width G of
  • the portion of the gate electrode 47 corresponding to the gate width G is separated from the end of the channel stop region 42.
  • FIG. 9A to FIG. 12C are schematic cross-sectional views showing the manufacturing method of the high voltage MOS transistor according to the present embodiment in the order of steps.
  • each figure except for FIG. 10B-2 is a sectional view taken along broken line II—— ⁇ in FIG. 7, and FIG. 10B-2 is a sectional view taken along broken line IV—IV ′ in FIG. Corresponds to the figure.
  • an oxidation resistant material film 33 is formed on a silicon semiconductor substrate 31 via an insulating film 32.
  • an insulating film 32 having a thickness of about 30 nm is formed on the surface of the semiconductor substrate 31 by a thermal oxidation method, and then an oxidation-resistant material, for example, silicon nitride is deposited by the CVD method to form an oxidation-resistant material film having a thickness of about lOOnm. 33 is formed.
  • an oxidation-resistant material for example, silicon nitride is deposited by the CVD method to form an oxidation-resistant material film having a thickness of about lOOnm. 33 is formed.
  • impurities for forming wells are introduced into the semiconductor substrate 31.
  • the oxidation-resistant material film 33 is patterned by lithography and dry etching so as to cover a portion to be the element region 30 of the semiconductor substrate 31.
  • a resist mask 34 is formed so as to expose part of the region where the element region 30 on the semiconductor substrate 31 and the peripheral field oxide film 39 are formed. Then, using the resist mask 34, a P-type impurity, here, passes through the oxidation-resistant material film 33 and the insulating film 32 and reaches the semiconductor substrate 1 corresponding to the lower part of the portion exposed from the resist mask 34. Then, boron (B + ) is ion-implanted. As ion implantation conditions, the acceleration energy is set to 200 keV to 500 keV, and the dose is set to 1 ⁇ 10 10 / cm 2 to 1 ⁇ 10 13 / cm 2 . By this ion implantation, a P-type impurity region 35 is formed. The resist mask 34 is removed by ashing or the like.
  • impurities for forming a channel stop region are introduced into the semiconductor substrate 31.
  • a resist mask 36 is formed on the formation site of the oxidation resistant material film 33 and the field oxide film 39 so as to surround the oxidation resistant material film 33 by being separated from the oxidation resistant material film 33 by a predetermined distance. To do.
  • the resist mask 36 exposes a ring-shaped portion on the site where the field oxide film 39 is formed.
  • P-type impurities this are introduced into the semiconductor substrate 31 corresponding to the lower part of the portion exposed from the resist mask 36.
  • boron (B + ) ions are implanted.
  • acceleration energy is set to 70 keV to 180 keV, and a dose amount is set to 1 X 10 10 / cm 2 to l X 10 "/ cm 2.
  • a dose amount is set to 1 X 10 10 / cm 2 to l X 10 "/ cm 2.
  • a well 41 and a channel dose region 42 are formed by annealing.
  • annealing is performed at 1000 to 1200 ° C. for about 0.5 to 9 hours to activate the P-type impurity regions 35 and 37 implanted into the semiconductor substrate 31.
  • a wall 41 and a channel stop region 42 are formed by this annealing process.
  • a field oxide film 39 is formed in the element isolation region.
  • the insulating film 32 and the semiconductor substrate 31 are field oxidized to form a field oxide film 39 in the element isolation region.
  • the device region 30 is defined on the semiconductor substrate 31 by the finered oxide film 39.
  • the finered oxide film 39 has a gate shape so that the element region 30 has a pair of projecting portions 30a projecting outward under the formation position of the gate electrode 47 when viewed in plan as shown in FIG.
  • the electrode 47 is formed in a concave shape under the formation site.
  • an insulating film 38 is formed on the semiconductor substrate 31 by a thermal oxidation method.
  • impurities for forming a channel dose region are introduced into the semiconductor substrate 31.
  • a resist mask 43 is formed so as to expose the formation site of the gate electrode 47 in the element region 30.
  • a P-type impurity here boron (B + )
  • B + a P-type impurity
  • the acceleration energy is 10 keV to 50 keV
  • the dose is 1 ⁇ 10 10 / cm 2 to 1 ⁇ 10 13 / cm 2 .
  • a P-type impurity region 44 is formed.
  • the resist mask 43 is removed by ashing or the like.
  • a gate insulating film 45 and a gate electrode material film 46 are formed.
  • the gate insulating film 45 is formed in the element region 30 to a thickness of about 20 nm by thermal oxidation.
  • the channel dose region 48 is formed by the annealing process when forming the gate insulating film.
  • a gate electrode material film 46 here a polycrystalline silicon film, is deposited to a thickness of about 300 nm by CVD.
  • the P-type impurity region 44 ion-implanted in the semiconductor substrate 31 is activated by annealing the gate for about 10 to 60 minutes with C.
  • a channel dose region 48 is formed by this annealing process.
  • the gate electrode 47 is patterned. Specifically, the gate electrode material film 46 is patterned into an electrode shape by lithography and dry etching to form the gate electrode 47.
  • the gate electrode 47 has a channel dose region 48 in the lower portion and is patterned so as to include the protruding portion 30a of the element region in the lower portion.
  • a resist mask 50 that exposes part of the element region 30 and the field oxide film 39 is formed, and the resist mask 50 is used to form an N-type impurity on both sides of the gate electrode 47 in the element region 30.
  • phosphorus (P + ) is ion-implanted.
  • the energy of the calo-velocity is 70 keV to 150 keV, and the dose is 1 X ⁇ ⁇ / ⁇ ⁇ ⁇ X 10 13 / cm 2 .
  • an N-type impurity region 49 is formed.
  • the resist mask 50 is removed by ashing or the like.
  • side wall insulating films 52 are formed on both side surfaces of the gate electrode 47.
  • annealing is performed at 900 ° C. to 1000 ° C. for about 10 seconds to 20 seconds, for example, to activate phosphorus in the N-type impurity region 49 as necessary.
  • annealing process a pair of LDD regions 51 are formed.
  • an insulator here a silicon oxide film (not shown) is deposited on the entire surface so as to cover the gate electrode 47 by a CVD method to a thickness of about 500 nm. Then, the entire surface of the silicon oxide film is subjected to anisotropic dry etching (etchback), and silicon oxide is formed only on both sides of the gate electrode 47. A sidewall insulating film 52 is formed by leaving the film.
  • a source region 53 and a drain region 54 are formed.
  • a resist mask (not shown) that exposes only the surface of the element region 30 on one side (source formation region) of the gate electrode 47 is formed, and this resist mask is used to form an N-type impurity, here arsenic.
  • (As + ) ions are implanted.
  • the ion implantation conditions are such that the acceleration energy is 70 keV to 120 keV and the dose is 1 X 10 15 / cm 2 to l X 10 16 / so that it is superimposed on the LDD region 51 at a higher impurity concentration than the L DD region 51.
  • a resist mask (not shown) that exposes only the surface of the element region 30 on the other side of the gate electrode 47 (drain formation region) is formed.
  • N-type impurities here arsenic (As + )
  • the ion implantation conditions are such that the calo-velocity energy is 70 keV to 120 keV and the dose is 1 X 10 15 so that it is superimposed on the LDD region 51 at a higher impurity concentration than the LDD region 51.
  • annealing treatment is performed at 900 ° C to 1000 ° C for about 10 seconds to 20 seconds to activate the ion-implanted phosphorus.
  • a source region 53 and a drain region 54 are formed.
  • the drain region 54 is formed to be offset from the end of the LDD region 51 by a predetermined distance in order to ensure the high breakdown voltage of the MOS transistor.
  • interlayer insulation films, contact holes, gate electrodes 47, wirings connected to the source region 53 and the drain region 54 are sequentially formed, and the high breakdown voltage N according to the present embodiment is formed.
  • Completed type MOS transistor is sequentially formed, and the high breakdown voltage N according to the present embodiment is formed.
  • FIG. 13 and FIGS. 14A to 14E are schematic diagrams showing the configuration of a high-breakdown-voltage MOS transistor according to the third embodiment. Note that the structure of the MOO transistor described in the second embodiment is used. The components corresponding to the component members are denoted by the same reference numerals.
  • FIG. 13 is a plan view
  • FIG. 14A is a cross-sectional view taken along the broken line ⁇ - ⁇ in FIG. 13
  • FIG. 14B is a cross-sectional view taken along the broken line ⁇ - ⁇ in FIG.
  • FIG. 14D is a cross-sectional view taken along the broken line IV-IV in FIG. 13
  • FIG. 14D is a cross-sectional view taken along the broken line V_V ′ in FIG.
  • an element isolation structure here, a field oxide film 39 by a L OCOS (LOCal Oxidation of Silicon) method is formed on a silicon semiconductor substrate 31, and an element region 30 is defined on the semiconductor substrate 31. Is done.
  • a wall 41 is formed on the surface layer of the semiconductor substrate 31 so as to include the element region 30.
  • a strip-shaped gate electrode 47 is patterned on the element region 30 through the gate insulating film 45 so as to cross the element region 30, and sidewall insulating films 52 are formed on both side surfaces of the gate electrode 47.
  • a pair of LDD regions 51 into which impurities are introduced at a low concentration are formed, so that they overlap with the LDD regions 51, respectively.
  • a source region 53 and a drain region 54 into which impurities are introduced at a high concentration are formed.
  • the source region 53 and A channel stop region 62 is formed in which impurities having a conductivity type opposite to that of the drain region 54 are introduced.
  • the drain region 54 is formed so as to be offset by a predetermined distance from the end of the LDD region 51 in order to ensure a high breakdown voltage of the MOS transistor.
  • the channel stop region 62 is also separated from the end of the LDD region 51 by a predetermined distance to ensure a high breakdown voltage.
  • the field oxide film 39 is formed at a portion below the gate electrode 47 so that the element region 30 has a pair of protruding portions 30a protruding outward at the portion below the gate electrode 47. It is formed in a concave shape.
  • the protrusion 30 a has a width W that is narrower than the gate length G of the gate electrode 47 and is
  • the length L is at least the element area.
  • the distance between the region 30 and a resist mask 36 for forming a channel stop region 42 described later is at least d, and the alignment accuracy between the pattern for forming the element region 30 and the pattern for forming the gate electrode 47 is satisfied.
  • the dimension is set to be more than 0.6 ⁇ .
  • an impurity having a conductivity type opposite to that of the source region 53 and the drain region 54 is introduced into the surface layer of the protrusion 30a to form a surface conductive region.
  • a channel dose region 48 is formed in the surface layer of the silicon element region 30 including the protruding portion 30a under the gate electrode 47 as the surface conductive region.
  • the channel dose region 48 in the wall 41 under the gate electrode 47 by forming the channel dose region 48 in the wall 41 under the gate electrode 47, a sufficient threshold voltage can be ensured.
  • the protrusion 30a is formed to be narrower than the gate length, so it does not function as an active region although it is a part of the element region 30.
  • the channel stop region 62 is formed below the field oxide film 39 so that the end 62a of the channel stop region 62 protrudes from the end of the field oxide film 39.
  • the stop region 62 does not exist (the end 62a of the channel stop region 62 does not reach the portion corresponding to the gate width G w), and the portion corresponding to the gate width G of the gate electrode 47
  • FIG. 15A to FIG. 16B-2 are schematic cross-sectional views showing the method of manufacturing the high voltage MOS transistor according to this embodiment in the order of steps.
  • each figure except FIGS. 16A-2 and 16B-2 is a cross-sectional view taken along the broken line ⁇ — ⁇ in FIG. 13, and FIGS. 16A-2 and 16B-2 are This corresponds to the cross-sectional view along the broken line IV_IV ′ in FIG.
  • an oxidation resistant material film 33 is formed on a silicon semiconductor substrate 31 via an insulating film 32.
  • an insulating film 32 having a thickness of about 30 nm is formed on the surface of the semiconductor substrate 31 by a thermal oxidation method.
  • an oxidation resistant material for example, silicon nitride is deposited by a CVD method to form an oxidation resistant material film 33 having a thickness of about lOOnm.
  • the oxidation-resistant material film 33 is patterned into the shape of the element region.
  • the oxidation-resistant material film 33 is patterned by lithography and dry etching so as to cover a portion that becomes the element region 30 of the semiconductor substrate 31.
  • a field oxide film 39 is formed in the element isolation region.
  • the insulating film 32 and the semiconductor substrate 31 are field oxidized to form a field oxide film 39 in the element isolation region.
  • the device region 30 is defined on the semiconductor substrate 31 by the finered oxide film 39.
  • the field oxide film 39 has a gate shape so that the element region 30 has a pair of projecting portions 30a projecting outward under the formation position of the gate electrode 47 when viewed in plan as shown in FIG.
  • the electrode 47 is formed in a concave shape under the formation site.
  • an insulating film 38 is formed on the semiconductor substrate 31 by a thermal oxidation method.
  • impurities for forming wells are introduced into the semiconductor substrate 31.
  • a resist mask 34 is formed so as to expose a part of the element region 30 on the semiconductor substrate 31 and the field oxide film 39 in the vicinity thereof. Then, the resist mask 34 is used to transmit the field oxide film 39 present in the opening of the resist mask 34 and reach the semiconductor substrate 1 corresponding to the lower portion of the portion exposed from the resist mask 34.
  • Impurities here boron (B + ) are ion-implanted.
  • the acceleration energy is 200 keV to 500 keV
  • the dose is 1 ⁇ 10 10 / cm 2 to 1 ⁇ 10 13 / cm 2 .
  • a P-type impurity region 35 is formed.
  • the resist mask 34 is removed by ashing or the like.
  • impurities for forming a channel stop region are introduced into the semiconductor substrate 31.
  • the device region 30 is separated from the element region 30 by a predetermined distance on the field oxide film 39.
  • a resist mask 36 is formed so as to surround the element region 30 excluding the element region protruding portion 30a.
  • the resist mask 36 exposes a ring-shaped portion on the field oxide film 39.
  • a P-type impurity here boron (B + )
  • B + boron
  • the acceleration energy is set to 100 keV to 240 keV
  • the dose is set to 1 ⁇ 10 10 Zcm 2 to 1 ⁇ 10 M / cm 2 .
  • a P-type impurity region 61 is formed immediately below the field oxide film 39 in alignment with the opening of the resist mask 36.
  • B is exposed from the opening of the resist mask 36 through the end force insulating film 38 of the element region 30 and is ion-implanted into the end portion.
  • + Is introduced deeper than the other part of the P-type impurity region 61.
  • the resist mask 36 is removed by ashing or the like.
  • an impurity for forming a channel dose region is introduced into the semiconductor substrate 31.
  • a resist mask 43 is formed so that the element region 30 is exposed. Then, using the resist mask 43, a P-type impurity, here boron (B + ), is ionized on the surface layer (here near the surface) of the semiconductor substrate 31 corresponding to the lower part of the portion exposed from the resist mask 43. inject.
  • the acceleration energy is 10 keV to 50 keV, and the dose is 1 ⁇ 10 lc> / cm 2 to l ⁇ 10 13 / cm 2 .
  • a P-type impurity region 44 is formed.
  • the resist mask 43 is removed by ashing or the like.
  • the various processes such as the formation of the sidewall insulating film 52, the source region 53, and the drain region 54, the high breakdown voltage N-type MOS transistor according to the present embodiment is completed.
  • This embodiment has substantially the same configuration as that of the second embodiment and is manufactured by substantially the same manufacturing method, but is different in that the form of the channel stop region is slightly different. This embodiment is a modification of the second embodiment.
  • FIGS. 17 and 18A to 18D are schematic views showing the configuration of a high voltage MOS transistor according to the fourth embodiment.
  • FIG. 17 is a plan view
  • FIG. 18A is a cross-sectional view taken along the broken line I—I ′ in FIG. 17
  • FIG. 18B is a cross-sectional view taken along the broken line ⁇ — ⁇ in FIG.
  • FIG. 18D is a cross-sectional view taken along the broken line IV—IV ′ of FIG. 17.
  • an element isolation structure here a field oxide film 39 formed by the LOCOS (LOCal Oxidation of Silicon) method is formed on a silicon semiconductor substrate 31, and an element region 30 is defined on the semiconductor substrate 31. Is done.
  • the well 41 is formed so as to include the element region 30.
  • a strip-shaped gate electrode 47 is patterned on the element region 30 via the gate insulating film 45 so as to cross the element region 30, and sidewall insulating films 52 are formed on both side surfaces of the gate electrode 47.
  • a pair of LDD regions 51 into which impurities are introduced at a low concentration are formed, so that they overlap with the LDD regions 51, respectively.
  • a source region 53 and a drain region 54 into which impurities are introduced at a high concentration are formed.
  • a source region is formed in order to prevent charge outflow between the impurity regions with the adjacent MOS transistor through the field oxide film 39.
  • a channelless top region 71 is formed in which impurities having the conductivity type opposite to that of the drain region 54 and the drain region 54 are introduced.
  • the drain region 54 is formed so as to be offset from the end of the LDD region 51 by a predetermined distance in order to ensure the high breakdown voltage of the MOS transistor. With this offset, the channel stop region 71 is also separated from the end of the LDD region 51 by a predetermined distance. High breakdown voltage is ensured.
  • the channel stop region 71 has a field on the almost right half (on the drain region 54 side) of FIG. 17 except for the formation position of the resist mask 36 as in FIG. 7 of the second embodiment.
  • An oxide film 39 is formed immediately below.
  • almost the left half (source region 53 side) of FIG. 17 is formed directly under the entire field oxide film 39. Therefore, in this case, as shown in FIG. 18A, a part of the channel stop region 71 is formed only on the source region 53 side of the portion surrounding the protruding portion 30a in the field oxide film 39. That is, in this embodiment, the channel stop region 71 is formed before the field oxide film 39 is formed, as in the second embodiment.
  • the oxidation-resistant material film 33 is patterned so as to be aligned with the formation region of the element region 30, so that the oxidation-resistant material film 33 is masked during channel stop ion implantation.
  • the intrusion of impurities into the formation region of the element region 30 is prevented.
  • the channel stop region is formed after the field oxide film 39 is formed
  • the channel stop region 71 when the channel stop region 71 is formed, the element region 30 is formed in an acid resistant region. Chemical film 33 does not exist. Accordingly, in this case, as shown in FIG. 19, a resist mask 72 is formed so as to include the element region 30 in the almost right half (drain region 54 side) of FIG. 17, and channel stop ion implantation is performed. It takes a thing.
  • the finered acid oxide film 39 is provided under the gate electrode 47 so that the element region 30 has a pair of protruding portions 30a protruding outward at the portion under the gate electrode 47.
  • the part is formed in a concave shape.
  • the protrusion 30a has a width W narrower than the gate length G of the gate electrode 47 and is
  • the length L is at least a distance d between the element region 30 and a resist mask 36 for forming a channel stop region 71 described later, and the pattern for forming the element region 30 and the formation of the gate electrode 47 are formed. Dimension with allowance, for example, 0. It is.
  • an impurity having a conductivity type opposite to that of the source region 53 and the drain region 54 is introduced into the surface layer of the protrusion 30a to form a surface conductive region.
  • a channel dose region 48 is formed in the surface layer of the silicon element region 30 including the protruding portion 30a under the gate electrode 47 as the surface conductive region.
  • the channel dose region 48 in the wall 41 under the gate electrode 47 by forming the channel dose region 48 in the wall 41 under the gate electrode 47, a sufficient threshold voltage can be ensured.
  • the projecting portion 30a is formed narrower than the gate length, so it does not function as an active region although it is a part of the device region 30. Therefore, as shown in FIG. 8D, for the channel stop region 71 formed under the field oxide film 39, even if the end of this channel stop region 71 protrudes from the end of the field oxide film 39, the gate electrode 47 The channel stop region 71 does not exist under the part corresponding to the gate width G of
  • the end of the channel stop region 72 does not reach the portion corresponding to the gate width G)
  • the portion corresponding to the gate width G of the gate electrode 47 and the end of the channel stop region 71 are separated from each other.
  • This embodiment has substantially the same configuration as that of the first embodiment and is manufactured by substantially the same manufacturing method, but differs in that the source region is also formed in an offset structure like the drain region. To do.
  • This embodiment is a modification of the first embodiment.
  • FIG. 20, FIG. 21A, and FIG. 21B are schematic diagrams showing the configuration of the high-breakdown-voltage MSO transistor according to the fifth embodiment.
  • FIG. 20 is a plan view
  • FIG. 21A is a cross-sectional view taken along broken line II in FIG. 20
  • FIG. 21B is a cross-sectional view taken along broken line ⁇ - ⁇ ⁇ ⁇ in FIG.
  • an element isolation structure here STI, is formed on the silicon semiconductor substrate 1.
  • An STI element isolation structure 7 is formed by the Trench Isolation method, and an element region 10 is defined on the semiconductor substrate 1.
  • a wall 21 is formed on the surface layer of the semiconductor substrate 1 so as to include the element region 10.
  • a strip-shaped gate electrode 16 is patterned on the element region 10 via the gate insulating film 14 so as to cross the element region 10, and the surface layer of the element region 10 on both sides of the gate electrode 16 is formed on the surface layer. Then, a pair of LDD regions 19 formed by introducing impurities at a low concentration is formed, and source / drain regions 25 formed by introducing impurities at a higher concentration than these are formed so as to overlap with the LDD regions 19 respectively. It has been done.
  • a channel stop region 23 is formed in which an impurity having a conductivity type opposite to that of the Z drain region 25 is introduced.
  • the source / drain region 25 is formed to be offset from the end of the LDD region 19 by a predetermined distance in order to ensure a high breakdown voltage of the MOS transistor.
  • the channel stop region 23 is also separated from the end of the LDD region 19 by a predetermined distance to ensure a high breakdown voltage.
  • the STI element isolation structure 7 has a portion below the gate electrode 16 such that the element region 10 has a pair of protruding portions 10a protruding outward at the portion below the gate electrode 16. It is formed in a concave shape.
  • the protrusion 10a has a width W narrower than the gate length G of the gate electrode 16 and the desired width.
  • the length L is at least the distance d between the element region 10 and a resist mask 11 for forming a channel stop region 23 described later, and the pattern for forming the element region 10 and the formation of the gate electrode 16 are formed.
  • the dimension is set to allow for a margin, for example, 0 or more so as to satisfy the alignment accuracy with the pattern for use.
  • the surface conductive region is formed by introducing the impurity.
  • a channel dose region 22 is formed on the surface layer of the silicon element region 10 including the protruding portion 10a under the gate electrode 16 as the surface conductive region.
  • a sufficient threshold voltage can be secured by forming the channel dose region 22 in the wall 21 under the gate electrode 16.
  • the protruding portion 10a is formed narrower than the gate length, it does not function as an active region although it is a part of the element region 10. Therefore, for the channel stop region 23 formed under the STI element isolation structure 7, even if the end of this channel stop region 23 protrudes from the end of the STI element isolation structure 7, the gate width G of the gate electrode 16 Equivalent to
  • the channel stop region 23 does not exist in the lower part of the region where the gate electrode 16 does not exist (the end of the channel stop region 23 does not reach the portion corresponding to the gate width G).
  • the portion corresponding to G and the end of the channel stop region 23 are kept apart.
  • the transistor characteristics are prevented from being deteriorated and stable and sufficient transistor characteristics can be obtained.
  • the reliability of the transistor isolation structure can be suppressed relatively easily and reliably with high reliability, regardless of the element isolation structure forming method and its process position.
  • a semiconductor device can be provided.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

La présente invention concerne une structure d'isolation (7) encastrée sous une électrode de grille (16) de sorte qu'une région d'élément (10) possède une paire de saillies (10a) dépassant vers l'extérieur depuis une partie placée sous l'électrode de grille (16). Sur la couche de surface de la saillie (10a), une région conductrice de couche de surface est formée par l'introduction d'impuretés ayant un type de conductivité opposé à celui d'une région source (24) et d'une région de drain (25), par exemple, une zone de sommeil de canal (22) est formée sur la couche de surface d'une région d'élément de silicium (10) comprenant la saillie (10a) sous l'électrode de grille (16). Avec cet agencement, la variation et la dégradation des caractéristiques du transistor sont supprimées, quel que soit le procédé de fabrication de la structure d'isolation et sa position de procédé et une tension de rupture élevée est obtenue de manière relativement simple et sûre.
PCT/JP2006/305596 2006-03-20 2006-03-20 Dispositif a semi-conducteurs et son procede de fabrication Ceased WO2007108104A1 (fr)

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Application Number Priority Date Filing Date Title
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62250671A (ja) * 1986-04-24 1987-10-31 Agency Of Ind Science & Technol 半導体装置
JPH0215672A (ja) * 1988-07-04 1990-01-19 Sony Corp 半導体装置
JPH1070272A (ja) * 1996-06-29 1998-03-10 Hyundai Electron Ind Co Ltd 半導体装置及びその製造方法
JP2001217414A (ja) * 2000-01-31 2001-08-10 Matsushita Electric Ind Co Ltd 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62250671A (ja) * 1986-04-24 1987-10-31 Agency Of Ind Science & Technol 半導体装置
JPH0215672A (ja) * 1988-07-04 1990-01-19 Sony Corp 半導体装置
JPH1070272A (ja) * 1996-06-29 1998-03-10 Hyundai Electron Ind Co Ltd 半導体装置及びその製造方法
JP2001217414A (ja) * 2000-01-31 2001-08-10 Matsushita Electric Ind Co Ltd 半導体装置

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