WO2007127202A1 - Boîtier sip moulé avec colonnes de soudure renforcées - Google Patents

Boîtier sip moulé avec colonnes de soudure renforcées Download PDF

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Publication number
WO2007127202A1
WO2007127202A1 PCT/US2007/009944 US2007009944W WO2007127202A1 WO 2007127202 A1 WO2007127202 A1 WO 2007127202A1 US 2007009944 W US2007009944 W US 2007009944W WO 2007127202 A1 WO2007127202 A1 WO 2007127202A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
electronic component
leadframe
recited
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2007/009944
Other languages
English (en)
Inventor
Chin-Tien Chiu
Hem Takiar
Hui Liu
Java Zhu
Jack Chang-Chien
Cheemen Yu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SanDisk Corp
Original Assignee
SanDisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/414,780 external-priority patent/US7435624B2/en
Priority claimed from US11/414,526 external-priority patent/US8878346B2/en
Application filed by SanDisk Corp filed Critical SanDisk Corp
Publication of WO2007127202A1 publication Critical patent/WO2007127202A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/303—Assembling printed circuits with electric components, e.g. with resistors with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0302—Properties and characteristics in general
    • H05K2201/0305—Solder used for other purposes than connections between PCB or components, e.g. for filling vias or for programmable patterns
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2036—Permanent spacer or stand-off in a printed circuit or printed circuit assembly
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/043—Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3465—Application of solder
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • Embodiments of the present invention relate to an integrated circuit, and a semiconductor die package formed therefrom, including solder columns for adding structural support to the package during fabrication.
  • Non-volatile semiconductor memory devices such as flash memory storage cards
  • flash memory storage cards are becoming widely used to meet the ever-growing demands on digital information storage and exchange.
  • Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including for example digital cameras, digital music players, video game consoles, PDAs and cellular telephones.
  • a leadframe which is a thin layer of metal on which one or more semiconductor die may be mounted.
  • the leadframe includes electrical leads for comm ⁇ nicating electrical signals from the one or more semiconductors to a printed circuit board or other external electrical devices.
  • Common leadframe-based packages include plastic small outlined packages (PSOP), thin small outlined packages (TSOP), and shrink small outline packages (SSOP).
  • PSOP plastic small outlined packages
  • TSOP thin small outlined packages
  • SSOP shrink small outline packages
  • Components in a conventional leadframe package are shown in Fig. 1. The illustrated components may be used for example in a TSOP package.
  • the package 20 includes a pair of semiconductor die 22 mounted on a leadframe 24.
  • the die 22 are wire bonded with wires 30 to electrical leads 26 and 28 of the leadframe.
  • electrical leads 26 may be angled so as to provide a down-set configuration. After the wire-bond process, semiconductor die 22, wire-bonds 30 and portions of leads 26 and 28 may be encapsulated in molding compound 30 in a known process to form the semiconductor die package 20.
  • TSOP package 20 may often be included as part of a system-i ⁇ - a-package (SiP) or multichip modules (MCM), where a plurality of die are mounted on a substrate such as a printed circuit board.
  • the substrate may in general include a rigid, dielectric base having a conductance pattern, generally of copper or copper alloy, etched on respective sides.
  • the TSOP package 20 may be surface mounted along with other electronic components to a substrate such as a printed circuit board 32 in a known surface mount process. Once electrical connections between the package 20, other electronic components and the substrate 32 are made, the assembly is then typically encased in a molding compound 34 in a transfer molding process (shown taking place in Fig. 2) to form a protected SiP semiconductor package.
  • the molding machine may output an injection force typically about 0.8 tons to drive the molding compound 34 into the mold cavity and around the surface mounted components.
  • a problem in conventional transfer molding processes is that the molding compound 34 travels more quickly over the top of surface mounted components, such as TSOP package 20, than into the space between the bottom surface of the component and the printed circuit board 32, as shown in Fig. 2.
  • the molding compound above the TSOP package 20 With the high pressure of the transfer molding process, the molding compound above the TSOP package 20 generates large forces down on the top of the package (indicated by arrows A).
  • the forces down on the top of package 20 may be on the order of about 1.2 kgf/mm 2 . As there is a void beneath the package during the molding process, these forces generate large stresses within the TSOP package 20.
  • Embodiments of the invention relate to an integrated circuit, and a semiconductor die package formed therefrom, including solder columns for adding structural support to the package during fabrication.
  • the solder columns may be applied to a substrate such as a printed circuit board in a variety of numbers and patterns to structurally support a leadframe-based package mounted to the substrate on top of the solder columns.
  • the solder columns may be applied as a solder paste or as solder balls in known solder application processes.
  • a leadframe-based semiconductor package may be surface mounted to the substrate in a known SMT or other mounting process.
  • the leadframe-based semiconductor package may for example be a TSOP semiconductor package, but other packages and electronic components are contemplated.
  • the substrate may then be heated to reflow and harden the solder in the solder columns and securely affix the leadframe-based semiconductor package to the substrate.
  • the height of the solder columns is provided so as to lie in contact with the bottom surface of the leadframe-based semiconductor package after the surface mount process.
  • the height of the solder columns when applied may be slightly larger than the space between the leadframe-based semiconductor package and the substrate, so that the package slightly compresses the columns when the package is surface mounted to the substrate. This ensures good contact between the package and solder columns, and good structural support by the solder columns.
  • the integrated circuit formed thereby may be encapsulated in a molding compound to form a finished SiP semiconductor package.
  • the solder columns serve to drastically reduce mechanical stresses within the leadframe-based semiconductor package.
  • the solder columns lie in contact with the bottom surface of the leadframe-based package, the solder columns provide an equal and opposite force to counteract the forces exerted on the leadframe-based semiconductor package by the molding compound during the encapsulation process.
  • FIGURE 1 is a cross-sectional side view of a conventional TSOP semiconductor package.
  • FIGURE 2 is a side view of a TSOP package mounted on a substrate during an encapsulation process.
  • FIGURE 3 is a flowchart for constructing an integrated circuit and semiconductor package according to the present invention.
  • FIGURE 4 is a cross-sectional side view of a substrate for use in accordance with the present invention.
  • FIGURE 5 is a cross-sectional side view of a substrate as in Fig.
  • FIGURE 6 is a cross-sectional side view of a substrate as in Fig.
  • FIGURE 7 is a top view of a substrate including solder columns according to an embodiment of the present invention.
  • FIGURE 8 is a flowchart illustrating the steps for completing fabrication of a semiconductor package according to embodiments of the present invention.
  • FIGURE 9 is a cross-sectional side view of a substrate as in Fig.
  • FIGURE 10 illustrates a completed semiconductor package including solder columns according to embodiments of the present invention.
  • Fig. 4 shows a substrate 100 on which an SiP semiconductor package may be formed.
  • Substrate 100 may be part of a substrate panel for batch processing a plurality of semiconductor packages. It is understood that the present invention is not limited to SiP semiconductor packages, and that the present invention may be used to fabricate a plurality of different semiconductor package configurations.
  • Substrate 100 may be a variety of different chip carrier mediums, including a PCB, a leadframe or a tape automated bonded (TAB) tape.
  • the substrate may be formed of a core 106, having a top conductive layer 108 formed on a top surface of the core 106, and a bottom conductive layer 110 formed on the bottom surface of the core.
  • the core 106 may be formed of various dielectric materials such as for example, polyimide laminates, epoxy resins including FR4 and FR5, bismaleimide triazine (BT), and the like.
  • core 106 may have a thickness of between 40 microns ( ⁇ m) to 200 ⁇ m, although the thickness of the core may vary outside of that range in alternative embodiments.
  • the core 106 may be ceramic or organic in alternative embodiments.
  • the conductive layers 108 and 110 may be formed of copper or copper alloys, plated copper or plated copper alloys, Alloy 42 (42Fe/58Ni), copper plated steel, or other metals and materials known for use on substrates.
  • the layers 108 and 110 may have a thickness of about 10 ⁇ m to 24 ⁇ m, although the thickness of the layers 108 and 110 may vary outside of that range in alternative embodiments.
  • the substrate 100 may be fabricated by initially drilling through-holes, or vias, through the substrate in step 180, and plating the holes in step 182 to allow electrical communication between the conductive layers 108 and 110.
  • the layers 108 and 110 may next be cleaned in step 184, and then etched with a conductance pattern to form a network of electrical traces in the layers 108 and 110 for signal and voltage (power/ground) communication.
  • One process for forming the conductance pattern on the substrate 100 includes the step 186 of applying a photoresist film over the surfaces of layers 108 and 110.
  • a pattern mask containing the outline of the electrical conductance pattern(s) may then be placed over the photoresist film in step 188.
  • the photoresist film is exposed (step 190) and developed (step 192) to remove the photoresist from areas on the conductive layers that are to be etched.
  • the exposed areas are next etched away using an etchant such as ferric chloride in step 194 to define the conductance patterns on the core.
  • the photoresist is removed in step 196.
  • Other known methods for forming the conductance pattern on substrate 100 are contemplated.
  • the top and bottom conductive layers 108, 110 may be laminated with a solder mask 112 in a step 198 to provide the structure shown in Fig.4.
  • the solder mask 112 may be developed to expose areas 116, 118 and 120 on the conductance pattern as shown in Fig. 5.
  • Areas 116 may form solder pads to which electronic components such as a TSOP semiconductor package may be surface mounted as explained hereinafter.
  • Areas 118 may form contact fingers for establishing electrical connection between the finished SiP semiconductor package and an external host device.
  • areas 120 may be for receiving solder columns in accordance with embodiments of the present invention as explained hereinafter.
  • the areas 120 may be approximately 300 ⁇ m square, though it is understood that the areas 120 may be larger or smaller than that in alternative embodiments of the present invention. There may be many more areas 116, 118 and 120 than are shown in the figures.
  • the areas 116, 118 and 120 may be plated with a layer of resistive metal in step 202 in a known electroplating process.
  • the areas 116, 118 and 120 of the conductance pattern may be plated with a metal film, such as for example gold, though other metals, including tin, tin-lead and nickel may be plated onto the conductance pattern(s) in alternative embodiments.
  • the plated areas 116 may form solder pads 126 and the plated areas 118 may form contact fingers 128 as shown in Fig. 6.
  • solder columns 130 may be applied to plated areas 120 as shown in Fig. 6. After surface mounting of a leadframe-based semiconductor package as explained hereinafter, the solder columns will provide structural support to the leadframe-based package to reduce mechanical stresses on the leadframe-based package during the subsequent encapsulation process.
  • the solder mask 112 was removed in the areas 120 to provide a metallic surface to which the solder columns 130 may adhere. However, it is understood that no electrical connection in fact need be established between the conductance pattern formed in the conductive layer 108 and the solder columns 130.
  • Solder may be applied to areas 120 as a paste in a known solder printing process.
  • solder paste applied in 'a solder printing process
  • solder columns may be formed of solder balls of known construction and applied in a solder ball placement process.
  • other structurally rigid materials may be used instead of solder paste or solder balls support the leadframe-based package during the encapsulation process.
  • Such structurally rigid materials may be structurally rigid when applied to substrate 100, or may become structurally rigid after a heating or curing process.
  • solder columns may be provided at positions so as to be relatively evenly distributed with respect to the bottom surface of a leadframe-based semiconductor package mounted thereover as explained hereinafter.
  • solder columns 130 there are five such solder columns 130 positioned in a crisscross pattern.
  • the solder columns may be arranged in a variety of other patterns on substrate 100 in alternative embodiments of the present invention.
  • Fig. 8 is a flowchart showing the steps for the continued fabrication of a semiconductor package according to the present invention.
  • a leadframe-based semiconductor package 140 (Fig. 9) may be surface mounted to substrate 100 by soldering leads of the package 140 to solder pads 126 in a known SMT or other mounting process.
  • Leadframe-based semiconductor package 140 may be any of a variety of lead frame-based semiconductor packages including for example a TSOP package as described in the background of. the invention.
  • Leadframe-based package 140 may include one or more semiconductor die which may for example be flash memory chips (NOR/NAND), SRAM or DDT, and/or a controller chip such as an ASIC.
  • leadframe-based semiconductor package 140 is not critical to the present invention and other semiconductor chip packages are contemplated.
  • other electronic components may be surface mounted to substrate 100 in step 180 in embodiments of the present invention.
  • the solder columns 130 may be applied at the same time as solder is applied to solder pads 126 to surface mount package 140. In altemative embodiments, the solder columns 130 may be applied before or after the solder applied to solder pads 126.
  • the substrate is heated to reflow and harden the solder in the solder columns and securely affix the surface mounted components at the solder pads. It is understood that the solder columns may be reflowed in a different heating process than that for securing the surface mounted components to the substrate 100.
  • the height of solder columns 130 is provided so as to lie in contact with the bottom surface of leadframe-based semiconductor package 140 after the surface mount process.
  • the height of the bottom surface of leadframe-based semiconductor package 140 above the substrate may be between 50 and 150 ⁇ m, though it is understood that the space between package 140 and substrate 100 may be smaller or larger than that in alternative embodiments.
  • the height of the solder columns 130 when applied may be slightly larger than the space between the leadframe-based semiconductor package 140 and the board, so that the package 140 slightly compresses the columns 130 when the package 140 is surface mounted to substrate 100. This ensures good contact between the package 140 and solder columns, and good structural support by the solder columns.
  • the columns 130 may be the same height as the space between the package 140 and substrate 100, or that the solder columns 130 may be slightly shorter than the space between the package 140 and substrate 100, in alternative embodiments.
  • the solder columns may have a diameter (in a plane generally parallel to surface of substrate 100) of approximately 150 ⁇ m, though it is understood that the diameter of columns 130 may be smaller or larger than that in alternative embodiments.
  • the plated areas 120 which receive solder columns 130 may be electrically coupled to other electrical terminals (such as solder pads 116) on substrate 100, or the areas 120 may be electrically isolated from other electrical terminals. In further embodiments of the present invention, the plated areas 120 receiving solder columns 130 may be electrically connected to the ground.
  • the mounted leadframe-based semiconductor package 140 and any other electronic components may define an integrated circuit on the substrate 100.
  • the integrated circuit may be encapsulated in a molding compound 144 in a step 210 (Fig. 8) to form a finished SiP semiconductor package 150.
  • the solder columns 130 serve to drastically reduce mechanical stresses within leadframe-based semiconductor package 140 as a result of molding compound 144 flowing more quickly over the top of leadframe-based semiconductor package 140 than beneath package 140.
  • solder columns 130 effectively reduce mechanical stresses and prevent cracking of the semiconductor die within leadframe-based package 140 which cracking may ordinarily occur during the encapsulation process in conventional SiP packages.
  • the present invention has been described above with respect to providing support to surface mounted semiconductor packages, it is understood that the present invention may be used to provide support for other electronic components surface mounted on substrate 100.
  • the solder columns may be provided beneath a variety of surface mounted electronic components to provide support to the electronic components during the encapsulation process.
  • solder columns are shown in the figures, it is understood that fewer than five and many more than five solder columns may be provided in alternative embodiments of the present invention.
  • leadframe-based semiconductor package 140 is a conventional 44 pin TSOP package
  • solder or other structural material may be applied beneath package 150 in geometries such as a ring, square, rectangle, etc. to accomplish the support and stress reduction properties of the present invention.
  • SiP package 150 may be used in any of a variety of applications, including for example as a flash memory card such as an SD-USB flash memory device manufactured by SanDisk Corporation of Sunnyvale, California. Other flash memory devices are contemplated, such as for example an SD Card, a Compact Flash, a Smart Media, a Mini SD Card, an MMC, an xD Card, a Transflash or a Memory Stick. It is understood that SiP package 150 may be used in a variety of other semiconductor device applications.
  • a flash memory card such as an SD-USB flash memory device manufactured by SanDisk Corporation of Sunnyvale, California.
  • Other flash memory devices are contemplated, such as for example an SD Card, a Compact Flash, a Smart Media, a Mini SD Card, an MMC, an xD Card, a Transflash or a Memory Stick. It is understood that SiP package 150 may be used in a variety of other semiconductor device applications.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

L'invention concerne un circuit intégré et un boîtier de puce à semiconducteur formé sur celui-ci, qui comprend des colonnes de soudure destinées à ajouter un support structurel au boîtier pendant le processus de fabrication.
PCT/US2007/009944 2006-04-28 2007-04-25 Boîtier sip moulé avec colonnes de soudure renforcées Ceased WO2007127202A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/414,780 US7435624B2 (en) 2006-04-28 2006-04-28 Method of reducing mechanical stress on a semiconductor die during fabrication
US11/414,526 US8878346B2 (en) 2006-04-28 2006-04-28 Molded SiP package with reinforced solder columns
US11/414,526 2006-04-28
US11/414,780 2006-04-28

Publications (1)

Publication Number Publication Date
WO2007127202A1 true WO2007127202A1 (fr) 2007-11-08

Family

ID=38542110

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/009944 Ceased WO2007127202A1 (fr) 2006-04-28 2007-04-25 Boîtier sip moulé avec colonnes de soudure renforcées

Country Status (2)

Country Link
TW (1) TWI404174B (fr)
WO (1) WO2007127202A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6012746A (ja) * 1983-07-01 1985-01-23 Mitsubishi Electric Corp 電子部品の実装方法
US4814944A (en) * 1985-08-14 1989-03-21 Omron Tateisi Electronics Co. Mounting structure for surface mounted type component with projection extending down from lower surface thereof and method of mounting a surface mounted type component on a printed circuit board
US20020079577A1 (en) * 1999-12-03 2002-06-27 Ho Tony H. Advanced electronic package
US20030168739A1 (en) * 2000-08-03 2003-09-11 Chien-Ping Huang Array structure of solder balls able to control collapse
WO2005074337A1 (fr) * 2004-01-30 2005-08-11 Robert Bosch Gmbh Composant electronique pour element support

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5258697A (en) * 1991-10-23 1993-11-02 Varelux Motor Corp. Efficient permanent magnet electric motor
US6072239A (en) * 1995-11-08 2000-06-06 Fujitsu Limited Device having resin package with projections
US5744383A (en) * 1995-11-17 1998-04-28 Altera Corporation Integrated circuit package fabrication method
JP3839178B2 (ja) * 1999-01-29 2006-11-01 株式会社ルネサステクノロジ 半導体装置
TWI251315B (en) * 2003-03-31 2006-03-11 Nec Schott Components Corp Thin metal package and manufacturing method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6012746A (ja) * 1983-07-01 1985-01-23 Mitsubishi Electric Corp 電子部品の実装方法
US4814944A (en) * 1985-08-14 1989-03-21 Omron Tateisi Electronics Co. Mounting structure for surface mounted type component with projection extending down from lower surface thereof and method of mounting a surface mounted type component on a printed circuit board
US20020079577A1 (en) * 1999-12-03 2002-06-27 Ho Tony H. Advanced electronic package
US20030168739A1 (en) * 2000-08-03 2003-09-11 Chien-Ping Huang Array structure of solder balls able to control collapse
WO2005074337A1 (fr) * 2004-01-30 2005-08-11 Robert Bosch Gmbh Composant electronique pour element support

Also Published As

Publication number Publication date
TWI404174B (zh) 2013-08-01
TW200812017A (en) 2008-03-01

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