WO2007146665A3 - Système de distribution d'énergie pour circuits intégrés - Google Patents

Système de distribution d'énergie pour circuits intégrés Download PDF

Info

Publication number
WO2007146665A3
WO2007146665A3 PCT/US2007/070401 US2007070401W WO2007146665A3 WO 2007146665 A3 WO2007146665 A3 WO 2007146665A3 US 2007070401 W US2007070401 W US 2007070401W WO 2007146665 A3 WO2007146665 A3 WO 2007146665A3
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuits
distribution system
power distribution
bypass
cavity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2007/070401
Other languages
English (en)
Other versions
WO2007146665A2 (fr
Inventor
Steve Weir
Scott Mcmorrow
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Teraspeed Consulting Group LLC
Original Assignee
Teraspeed Consulting Group LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/757,261 external-priority patent/US7886431B2/en
Priority claimed from US11/757,269 external-priority patent/US20070279882A1/en
Priority claimed from US11/757,265 external-priority patent/US7773390B2/en
Application filed by Teraspeed Consulting Group LLC filed Critical Teraspeed Consulting Group LLC
Publication of WO2007146665A2 publication Critical patent/WO2007146665A2/fr
Publication of WO2007146665A3 publication Critical patent/WO2007146665A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0231Capacitors or dielectric substances
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection
    • H03K19/00346Modifications for eliminating interference or parasitic voltages or currents
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/141One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00Electrical arrangements for controlling or matching impedance
    • H10W44/20Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/04Assemblies of printed circuits
    • H05K2201/049PCB for one component, e.g. for mounting onto mother PCB
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/0929Conductive planes
    • H05K2201/09309Core having two or more power planes; Capacitive laminate of two power planes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227Other objects, e.g. metallic pieces
    • H05K2201/10378Interposers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10734Ball grid array [BGA]; Bump grid array
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Electromagnetism (AREA)
  • Filters And Equalizers (AREA)
  • Distribution Board (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

Le système de distribution d'énergie pour circuits intégrés selon l'invention comprend des procédés d'atténuation de la résonance entre un réseau de condensateurs de dérivation et une cavité d'énergie/de terre de la carte de circuit imprimé qui (a) ne nécessite pas de quantités excessives de composants de dérivation/atténuation ou (b) ne nécessite pas de capacités de cavité plane élevée ou en variante peut assurer une Q inférieure à 1,4 à la transition depuis le réseau de dérivation vers le recouvrement d'impédance de la cavité plane.
PCT/US2007/070401 2006-06-06 2007-06-05 Système de distribution d'énergie pour circuits intégrés Ceased WO2007146665A2 (fr)

Applications Claiming Priority (12)

Application Number Priority Date Filing Date Title
US80408906P 2006-06-06 2006-06-06
US60/804,089 2006-06-06
US88714807P 2007-01-29 2007-01-29
US60/887,148 2007-01-29
US88714907P 2007-01-30 2007-01-30
US60/887,149 2007-01-30
US11/757,261 2007-06-01
US11/757,261 US7886431B2 (en) 2006-06-06 2007-06-01 Power distribution system for integrated circuits
US11/757,265 2007-06-01
US11/757,269 2007-06-01
US11/757,269 US20070279882A1 (en) 2006-06-06 2007-06-01 Power distribution system for integrated circuits
US11/757,265 US7773390B2 (en) 2006-06-06 2007-06-01 Power distribution system for integrated circuits

Publications (2)

Publication Number Publication Date
WO2007146665A2 WO2007146665A2 (fr) 2007-12-21
WO2007146665A3 true WO2007146665A3 (fr) 2008-12-04

Family

ID=38832653

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/070401 Ceased WO2007146665A2 (fr) 2006-06-06 2007-06-05 Système de distribution d'énergie pour circuits intégrés

Country Status (2)

Country Link
TW (1) TW200826753A (fr)
WO (1) WO2007146665A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9241400B2 (en) 2013-08-23 2016-01-19 Seagate Technology Llc Windowed reference planes for embedded conductors
TWI842654B (zh) * 2023-12-01 2024-05-11 亞福儲能股份有限公司 用於複合電力系統的控制器以及電能管理方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3414832A (en) * 1964-12-04 1968-12-03 Westinghouse Electric Corp Acoustically resonant device
US4096362A (en) * 1977-06-20 1978-06-20 Bell Telephone Laboratories, Incorporated Automatic cable balancing network
US6588005B1 (en) * 1998-12-11 2003-07-01 Hitachi, Ltd. Method of manufacturing semiconductor integrated circuit device
US6608259B1 (en) * 1999-11-26 2003-08-19 Nokia Mobile Phones Limited Ground plane for a semiconductor chip
US20050280146A1 (en) * 2004-06-17 2005-12-22 Cornelius William P Interposer containing bypass capacitors for reducing voltage noise in an IC device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3414832A (en) * 1964-12-04 1968-12-03 Westinghouse Electric Corp Acoustically resonant device
US4096362A (en) * 1977-06-20 1978-06-20 Bell Telephone Laboratories, Incorporated Automatic cable balancing network
US6588005B1 (en) * 1998-12-11 2003-07-01 Hitachi, Ltd. Method of manufacturing semiconductor integrated circuit device
US6608259B1 (en) * 1999-11-26 2003-08-19 Nokia Mobile Phones Limited Ground plane for a semiconductor chip
US20050280146A1 (en) * 2004-06-17 2005-12-22 Cornelius William P Interposer containing bypass capacitors for reducing voltage noise in an IC device

Also Published As

Publication number Publication date
TW200826753A (en) 2008-06-16
WO2007146665A2 (fr) 2007-12-21

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