WO2008022901A3 - Procede de fabrication collective de modules electroniques 3d - Google Patents

Procede de fabrication collective de modules electroniques 3d Download PDF

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Publication number
WO2008022901A3
WO2008022901A3 PCT/EP2007/058090 EP2007058090W WO2008022901A3 WO 2008022901 A3 WO2008022901 A3 WO 2008022901A3 EP 2007058090 W EP2007058090 W EP 2007058090W WO 2008022901 A3 WO2008022901 A3 WO 2008022901A3
Authority
WO
WIPO (PCT)
Prior art keywords
stage
components
wafers
modules
valid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2007/058090
Other languages
English (en)
Other versions
WO2008022901A2 (fr
Inventor
Christian Val
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
3D Plus SA
Original Assignee
3D Plus SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 3D Plus SA filed Critical 3D Plus SA
Priority to KR1020097003376A priority Critical patent/KR101424298B1/ko
Priority to US12/438,179 priority patent/US7951649B2/en
Priority to EP07788221.5A priority patent/EP2054929B1/fr
Priority to JP2009525001A priority patent/JP5433899B2/ja
Publication of WO2008022901A2 publication Critical patent/WO2008022901A2/fr
Publication of WO2008022901A3 publication Critical patent/WO2008022901A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/273—Interconnections for measuring or testing, e.g. probe pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7402—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7422—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/743—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7434—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/744—Details of chemical or physical process used for separating the auxiliary support from a device or a wafer
    • H10P72/7442—Separation by peeling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/834—Interconnections on sidewalls of chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/856—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49004—Electrical device making including measuring or testing of device or component part

Landscapes

  • Micromachines (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention concerne Ia fabrication collective de n modules 3D. Elle comprend une étape de fabrication d'un lot de n tranches i sur une même plaque, d'épaisseur es comprenant du silicium, recouverte sur une face de plots de test (20) puis d'une couche isolante (4) d'épaisseur e, formant le substrat isolant et munie d'au moins un composant électronique (11 ) connecté aux plots de test (20) à travers ladite couche isolante, les composants étant séparés les uns des autres par des premières rainures (30) d'une largeur L1, les plots de connexion des composants (2) étant connectés à des pistes (3) qui affleurent au niveau des rainures (30), B1) une étape de dépôt d'un support adhésif (40) sur la face côté composants, C1 ) une étape de retrait de la plaque de silicium (10) de manière à faire apparaître les plots de test (20), D1 ) une étape de test électrique des composants de la plaque par les plots de test (20), et de marquage des composants valides (11 '), E1 ) une étape de report sur un film adhésif (41) des tranches (50) comportant chacune un composant valide (11 '), les tranches étant séparées par des deuxièmes rainures (31) au niveau desquelles affleurent les pistes de connexion (3) des composants valides (11 '). Cette étape répétée K fois, est suivie d'une étape d'empilement des K plaques, de formation de trous métallisés dans l'épaisseur de l'empilement et destinés à la connexion des tranches entre elles, puis de découpe de l'empilement pour obtenir les n modules 3D.
PCT/EP2007/058090 2006-08-22 2007-08-03 Procede de fabrication collective de modules electroniques 3d Ceased WO2008022901A2 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020097003376A KR101424298B1 (ko) 2006-08-22 2007-08-03 전자 3ｄ 모듈들의 일괄적 제조를 위한 프로세스
US12/438,179 US7951649B2 (en) 2006-08-22 2007-08-03 Process for the collective fabrication of 3D electronic modules
EP07788221.5A EP2054929B1 (fr) 2006-08-22 2007-08-03 Procede de fabrication collective de modules electroniques 3d
JP2009525001A JP5433899B2 (ja) 2006-08-22 2007-08-03 ３次元電子モジュールの集合的製作方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0607442 2006-08-22
FR0607442A FR2905198B1 (fr) 2006-08-22 2006-08-22 Procede de fabrication collective de modules electroniques 3d

Publications (2)

Publication Number Publication Date
WO2008022901A2 WO2008022901A2 (fr) 2008-02-28
WO2008022901A3 true WO2008022901A3 (fr) 2008-06-19

Family

ID=37888100

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2007/058090 Ceased WO2008022901A2 (fr) 2006-08-22 2007-08-03 Procede de fabrication collective de modules electroniques 3d

Country Status (7)

Country Link
US (1) US7951649B2 (fr)
EP (1) EP2054929B1 (fr)
JP (1) JP5433899B2 (fr)
KR (1) KR101424298B1 (fr)
FR (1) FR2905198B1 (fr)
TW (1) TWI392054B (fr)
WO (1) WO2008022901A2 (fr)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2923081B1 (fr) * 2007-10-26 2009-12-11 3D Plus Procede d'interconnexion verticale de modules electroniques 3d par des vias.
FR2940521B1 (fr) 2008-12-19 2011-11-11 3D Plus Procede de fabrication collective de modules electroniques pour montage en surface
FR2943176B1 (fr) 2009-03-10 2011-08-05 3D Plus Procede de positionnement des puces lors de la fabrication d'une plaque reconstituee
CN102023236A (zh) * 2009-09-11 2011-04-20 中芯国际集成电路制造(上海)有限公司 测试结构及测试方法
US8012802B2 (en) * 2010-02-04 2011-09-06 Headway Technologies, Inc. Method of manufacturing layered chip package
US9064977B2 (en) 2012-08-22 2015-06-23 Freescale Semiconductor Inc. Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
US9190390B2 (en) 2012-08-22 2015-11-17 Freescale Semiconductor Inc. Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
US9093457B2 (en) 2012-08-22 2015-07-28 Freescale Semiconductor Inc. Stacked microelectronic packages having patterned sidewall conductors and methods for the fabrication thereof
US8518741B1 (en) 2012-11-07 2013-08-27 International Business Machines Corporation Wafer-to-wafer process for manufacturing a stacked structure
US9299670B2 (en) 2013-03-14 2016-03-29 Freescale Semiconductor, Inc. Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
US9524950B2 (en) 2013-05-31 2016-12-20 Freescale Semiconductor, Inc. Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
PL3957459T3 (pl) * 2013-09-27 2025-11-03 Tactotek Oy Sposób wytwarzania struktury elektromechanicznej i układ do realizacji tego sposobu
US9036363B2 (en) 2013-09-30 2015-05-19 Freescale Semiconductor, Inc. Devices and stacked microelectronic packages with parallel conductors and intra-conductor isolator structures and methods of their fabrication
US9025340B2 (en) 2013-09-30 2015-05-05 Freescale Semiconductor, Inc. Devices and stacked microelectronic packages with in-trench package surface conductors and methods of their fabrication
US9305911B2 (en) 2013-12-05 2016-04-05 Freescale Semiconductor, Inc. Devices and stacked microelectronic packages with package surface conductors and adjacent trenches and methods of their fabrication
US9263420B2 (en) 2013-12-05 2016-02-16 Freescale Semiconductor, Inc. Devices and stacked microelectronic packages with package surface conductors and methods of their fabrication
CN113893094B (zh) 2014-03-06 2023-07-21 宝洁公司 三维基底
US10388607B2 (en) 2014-12-17 2019-08-20 Nxp Usa, Inc. Microelectronic devices with multi-layer package surface conductors and methods of their fabrication
US9871019B2 (en) 2015-07-17 2018-01-16 Invensas Corporation Flipped die stack assemblies with leadframe interconnects
US9825002B2 (en) 2015-07-17 2017-11-21 Invensas Corporation Flipped die stack
US9490195B1 (en) 2015-07-17 2016-11-08 Invensas Corporation Wafer-level flipped die stacks with leadframes or metal foil interconnects
US9508691B1 (en) 2015-12-16 2016-11-29 Invensas Corporation Flipped die stacks with multiple rows of leadframe interconnects
FR3048123B1 (fr) 2016-02-19 2018-11-16 3D Plus Procede d'interconnexion chip on chip miniaturisee d'un module electronique 3d
US10566310B2 (en) 2016-04-11 2020-02-18 Invensas Corporation Microelectronic packages having stacked die and wire bond interconnects
US9595511B1 (en) 2016-05-12 2017-03-14 Invensas Corporation Microelectronic packages and assemblies with improved flyby signaling operation
FR3053158B1 (fr) * 2016-06-22 2018-11-16 3D Plus Procede de fabrication collective de modules electroniques 3d configures pour fonctionner a plus d'1 ghz
US9728524B1 (en) 2016-06-30 2017-08-08 Invensas Corporation Enhanced density assembly having microelectronic packages mounted at substantial angle to board
IT201800001092A1 (it) 2018-01-16 2019-07-16 St Microelectronics Srl Sensore di pressione piezoresistivo microelettromeccanico con capacita' di auto-diagnosi e relativo procedimento di fabbricazione
JP7258906B2 (ja) * 2018-03-15 2023-04-17 アプライド マテリアルズ インコーポレイテッド 半導体素子パッケージ製造プロセスための平坦化
RU2705727C1 (ru) * 2018-12-28 2019-11-11 федеральное государственное бюджетное научное учреждение "Научно-производственный комплекс "Технологический центр" Способы изготовления трехмерных электронных модулей, трехмерные электронные модули
RU2745338C1 (ru) * 2020-08-05 2021-03-24 Общество с ограниченной ответственностью "Маппер" Способ соединения кремниевых пластин микроэлектромеханических систем с изоляционным слоем диоксида кремния между ними
CN113793811B (zh) * 2021-11-16 2022-02-15 湖北三维半导体集成创新中心有限责任公司 芯片堆叠结构的连接方法
US12016131B2 (en) * 2021-12-30 2024-06-18 X Display Company Technology Limited Transfer printing high-precision devices

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1041620A2 (fr) * 1999-04-02 2000-10-04 Interuniversitair Microelektronica Centrum Vzw Methode de transfere de les substrats ultra-minces et application dans la fabrication d'un dispositif de multi-couches minces
JP2001210782A (ja) * 2000-01-27 2001-08-03 Seiko Epson Corp 半導体チップ、マルチチップパッケージ、および半導体装置と、並びに、それを用いた電子機器
JP2001332685A (ja) * 2000-05-24 2001-11-30 Matsushita Electric Ind Co Ltd 半導体装置の製造方法

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2403688A1 (fr) * 1977-09-16 1979-04-13 Thomson Csf Dispositif attenuateur reglable
FR2456388A1 (fr) * 1979-05-10 1980-12-05 Thomson Brandt Microboitier de circuit electronique, et circuit hybride comportant un tel microboitier
FR2485262A1 (fr) * 1980-06-19 1981-12-24 Thomson Csf Boitier d'encapsulation resistant a de fortes pressions externes
FR2485796A1 (fr) * 1980-06-24 1981-12-31 Thomson Csf Resistance electrique chauffante et tete d'imprimante thermique comportant de telles resistances chauffantes
FR2525815B1 (fr) * 1982-04-27 1985-08-30 Inf Milit Spatiale Aeronaut Substrat composite a haute conduction thermique et application aux boitiers de dispositifs semi-conducteurs
FR2527039A1 (fr) * 1982-05-14 1983-11-18 Inf Milit Spatiale Aeronaut Dispositif de protection d'un dispositif electronique contre les tensions engendrees par un champ electromagnetique
FR2538618B1 (fr) * 1982-12-28 1986-03-07 Inf Milit Spatiale Aeronaut Boitier pour composant electronique comportant un element fixant l'humidite
FR2547113B1 (fr) * 1983-06-03 1986-11-07 Inf Milit Spatiale Aeronaut Boitier d'encapsulation de composant electronique, durci vis-a-vis des radiations
FR2550009B1 (fr) * 1983-07-29 1986-01-24 Inf Milit Spatiale Aeronaut Boitier de composant electronique muni d'un condensateur
US5237204A (en) * 1984-05-25 1993-08-17 Compagnie D'informatique Militaire Spatiale Et Aeronautique Electric potential distribution device and an electronic component case incorporating such a device
FR2591801B1 (fr) * 1985-12-17 1988-10-14 Inf Milit Spatiale Aeronaut Boitier d'encapsulation d'un circuit electronique
FR2614134B1 (fr) * 1987-04-17 1990-01-26 Cimsa Sintra Procede de connexion d'un composant electronique pour son test et son montage, et dispositif de mise en oeuvre de ce procede
FR2666190B1 (fr) * 1990-08-24 1996-07-12 Thomson Csf Procede et dispositif d'encapsulation hermetique de composants electroniques.
US5847448A (en) * 1990-12-11 1998-12-08 Thomson-Csf Method and device for interconnecting integrated circuits in three dimensions
FR2674680B1 (fr) * 1991-03-26 1993-12-03 Thomson Csf Procede de realisation de connexions coaxiales pour composant electronique, et boitier de composant comportant de telles connexions.
FR2688629A1 (fr) * 1992-03-10 1993-09-17 Thomson Csf Procede et dispositif d'encapsulation en trois dimensions de pastilles semi-conductrices.
FR2688630B1 (fr) * 1992-03-13 2001-08-10 Thomson Csf Procede et dispositif d'interconnexion en trois dimensions de boitiers de composants electroniques.
FR2691836B1 (fr) * 1992-05-27 1997-04-30 Ela Medical Sa Procede de fabrication d'un dispositif a semi-conducteurs comportant au moins une puce et dispositif correspondant.
DK0660967T3 (da) * 1992-09-14 2001-08-13 Shellcase Ltd Fremgangsmåde til fremstilling af integrerede kredsløbsanordninger
FR2696871B1 (fr) * 1992-10-13 1994-11-18 Thomson Csf Procédé d'interconnexion 3D de boîtiers de composants électroniques, et composants 3D en résultant.
FR2709020B1 (fr) * 1993-08-13 1995-09-08 Thomson Csf Procédé d'interconnexion de pastilles semi-conductrices en trois dimensions, et composant en résultant.
FR2719967B1 (fr) * 1994-05-10 1996-06-07 Thomson Csf Interconnexion en trois dimensions de boîtiers de composants électroniques utilisant des circuits imprimés.
JP2000252411A (ja) 1999-03-03 2000-09-14 Mitsui High Tec Inc スタックド半導体装置及びその製造方法
FR2802706B1 (fr) * 1999-12-15 2002-03-01 3D Plus Sa Procede et dispositif d'interconnexion en trois dimensions de composants electroniques
FR2805082B1 (fr) * 2000-02-11 2003-01-31 3D Plus Sa Procede d'interconnexion en trois dimensions et dispositif electronique obtenu par ce procede
FR2812453B1 (fr) * 2000-07-25 2004-08-20 3D Plus Sa Procede de blindage et/ou de decouplage repartis pour un dispositif electronique a interconnexion en trois dimensions , dispositif ainsi obtenu et procede d'obtention de celui- ci
JP4361670B2 (ja) * 2000-08-02 2009-11-11 富士通マイクロエレクトロニクス株式会社 半導体素子積層体、半導体素子積層体の製造方法、及び半導体装置
FR2832136B1 (fr) * 2001-11-09 2005-02-18 3D Plus Sa Dispositif d'encapsulation hermetique de composant devant etre protege de toute contrainte
FR2857157B1 (fr) * 2003-07-01 2005-09-23 3D Plus Sa Procede d'interconnexion de composants actif et passif et composant heterogene a faible epaisseur en resultant
FR2875672B1 (fr) * 2004-09-21 2007-05-11 3D Plus Sa Sa Dispositif electronique avec repartiteur de chaleur integre
FR2884049B1 (fr) * 2005-04-01 2007-06-22 3D Plus Sa Sa Module electronique de faible epaisseur comprenant un empilement de boitiers electroniques a billes de connexion
FR2894070B1 (fr) * 2005-11-30 2008-04-11 3D Plus Sa Sa Module electronique 3d
FR2895568B1 (fr) * 2005-12-23 2008-02-08 3D Plus Sa Sa Procede de fabrication collective de modules electroniques 3d

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1041620A2 (fr) * 1999-04-02 2000-10-04 Interuniversitair Microelektronica Centrum Vzw Methode de transfere de les substrats ultra-minces et application dans la fabrication d'un dispositif de multi-couches minces
JP2001210782A (ja) * 2000-01-27 2001-08-03 Seiko Epson Corp 半導体チップ、マルチチップパッケージ、および半導体装置と、並びに、それを用いた電子機器
JP2001332685A (ja) * 2000-05-24 2001-11-30 Matsushita Electric Ind Co Ltd 半導体装置の製造方法

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WO2008022901A2 (fr) 2008-02-28
EP2054929B1 (fr) 2016-03-16
FR2905198B1 (fr) 2008-10-17
TW200826229A (en) 2008-06-16
US20090209052A1 (en) 2009-08-20
KR101424298B1 (ko) 2014-08-01
KR20090048597A (ko) 2009-05-14
US7951649B2 (en) 2011-05-31
JP2010502006A (ja) 2010-01-21
FR2905198A1 (fr) 2008-02-29
TWI392054B (zh) 2013-04-01
JP5433899B2 (ja) 2014-03-05
EP2054929A2 (fr) 2009-05-06

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