WO2008155678A1 - Détection de séquences de données défectueuses - Google Patents

Détection de séquences de données défectueuses Download PDF

Info

Publication number
WO2008155678A1
WO2008155678A1 PCT/IB2008/051919 IB2008051919W WO2008155678A1 WO 2008155678 A1 WO2008155678 A1 WO 2008155678A1 IB 2008051919 W IB2008051919 W IB 2008051919W WO 2008155678 A1 WO2008155678 A1 WO 2008155678A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
bits
sequence
defective
storage medium
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2008/051919
Other languages
English (en)
Inventor
Sönke OSTERTUN
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of WO2008155678A1 publication Critical patent/WO2008155678A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/40—Response verification devices using compression techniques
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0411—Online error correction

Definitions

  • the invention relates to a method for detecting a defective data sequence on a storage medium, wherein the data sequence contains a plurality of bits, including data bits and redundancy bits, and further relates to a method for testing a storage medium.
  • the invention furthermore relates to a device for detecting a defective data sequence on a storage medium.
  • error correction mechanisms are frequently used to enhance their efficiency and/or their lifetimes, which mechanisms require, in addition to the data bits, additional physical bits per stored data sequence, so-called redundancy bits or test bits. This has the result that a physical bit length of the data sequence exceeds the logical bit length of the data sequence.
  • EP 0 989 681 Bl is a system for detecting and correcting errors in a data block.
  • the data block contains data bits and check bits. Pairs of bits of the data block are transferred by several accesses to the stored data block on a multiplicity of data paths of a data bus and a so-called syndrome vector is generated from the transmitted data, with the aid of which single bit errors and double bit errors in the data block are detected.
  • an error correction mechanism is generally deactivated, in particular to detect system errors.
  • read-out of the storage medium without error correction is only possible via a data bus having the logical bit length by additionally reading out the redundancy bits in a second access.
  • the double read-out of the storage medium required when testing the storage medium means additional expenditure and costs, inter alia, valuable test time.
  • the read-out of data sequences from the storage medium should take place in as few steps as possible.
  • the object is achieved according to the invention by a method having the features of claim 1 as well as a corresponding device.
  • a data sequence comprising a plurality of bits containing nd data bits and nr redundancy bit is taken as the basis, wherein nd is the number of data bits and nr is the number of redundancy bits.
  • the method provides that the read-out of data sequences from a storage medium for the purpose of testing is reduced in each case from two to one read access without loss of test coverage.
  • a data sequence i.e.
  • Typical data patterns are fully set data sequences (1 1 1 %), completely unset data sequences (0 0 0 %) and so-called chequer-board patterns (1 0 1%), (0 1 0 7) in which every other bit is set. If the amount of data patterns occurring during tests is known, bit positions behaving similarly to these data patterns are clustered into groups. A data sequence is then compared with all the data patterns to be expected by the design of the circuitry, and the bit positions are grouped together which should always be identical for all expectation values.
  • At least one test sequence comprising a maximum of nd bits is formed depending on the data sequence and the relevant data pattern so that a read-out and transfer from the storage medium is possible by means of a data bus which is designed for the bit length nd.
  • a data bus which is designed for the bit length nd.
  • the classification of a single data sequence into one of the three states "data sequence correct”, “data sequence correctable” and “data sequence defective” can be made simply, this also provides a basis for evaluating the storage medium on which several data sequences are stored.
  • the number of data sequences on the storage medium which are classified as “correct”, “correctable” or “defective” are determined separately in each case and compared with predefined criteria.
  • Such criteria can be, for example, a maximum permissible number of "defective” data sequences or a maximum permissible fraction of "defective" data sequences in the total number of stored data sequences.
  • Corresponding criteria can also be compiled for "correctable" data sequences which are optionally applied more tolerantly with regard to the number or the fraction of "correctable” data sequences since a "correctable” data sequence only means a single-bit error whilst a “defective" data sequence means at least a two-bit error.
  • the method described and a corresponding device for carrying out the method can be applied according to its principle for the correction of defective error sequences on storage media as well as for the detection and correction of defective data sequences transferred by a transfer medium.
  • testing of the storage medium should be replaced by testing of the transfer medium, wherein the evaluation of the transfer medium is made by analogy with the storage medium as defective or non- defective on the basis of the number of correct and/or correctable and/or defective data sequences and by reference to predefined criteria.
  • An evaluation "defective storage medium" can be caused, for example, by a defective component of the storage medium but also by a defective line or a defective connection.
  • defective transfer medium can, for example, be based on defective components of the transfer medium, noise, or interference voltages within the transfer system being considered.
  • Fig. 4 shows a schematic circuit arrangement for the example of a storage module.
  • Table 1 shows four data patterns I to IV in the form (dl5..d ⁇ r4 .. r ⁇ ) as well as an allocation V to two bit groups a, b.
  • the coding allows all single-bit errors to be corrected.
  • bit positions designated with a in line V of Table 1 are “unset” for data pattern I, "inverse chequer-board” for data pattern IV, all at 0, and “set” for data pattern II, and “chequer-board”, at 1 for data pattern III.
  • the bit positions designated with b in line V are “unset” for data pattern I, “chequer-board” for data pattern III, all at
  • Table 2 presents a calculation of the four status signals all Ia, allOa, all Ib and allOb by means of multiple AND gates and multiple NOR gates for the various data patterns expected during testing.
  • Multiple AND gates are to be understood here in the sense of “multiple set gates” and multiple NOR gates in the sense of “multiple unset gates”.
  • Completely correct data sequences (dl5 ..d ⁇ r4 ..r ⁇ ) can thus be assigned for the test patterns one-to-one to the results indicated in the right-hand four columns in Table 2 for all four signals allla, allOa, alllb and allOb.
  • either one bit group x or several bit groups x can be affected by an error so that the signals alllx and allOx remain at 0. If several bit groups x are affected, at least two bit positions must be defective and the data sequence (dl5 ..d ⁇ r4 ..r ⁇ ) is considered to be incorrectably wrong, hereinafter also designated as defective. If only one bit group x is affected, this can either comprise a single-bit error or several defective bit positions are also located here in bit group x.
  • bit group x it is important that only one bit group x is affected so that in this case, only the bits of the affected bit group x must be transferred to the data bus. Since a bit group requires half the physical bit length of the data sequence (dl5 ..d ⁇ r4 ..r ⁇ ) at most, usually one read-out on the data bus parallel to the status bits allxy is possible. This can be achieved most simply by executing a bitwise
  • Table 1 and 2 shows seven data sequences I, VI, VII, VIII, IX and X in the form (dl5 ..d ⁇ r4 ..r ⁇ ) which are classified by reference to a test sequence from an XOR operation.
  • the two status bits allOa and allOb are given in the third and fourth columns of Table 3 as well as 11 bits for allOa and 10 bits plus 1 bit directly for allOb from the XOR operation.
  • a total of 15 bits are thus required, which can be delivered simultaneously via a data bus designed for data sequences of 16 bit length.
  • a particular advantage with this solution is that only a few standard gates, in the example two multiple AND gates and two multiple NOR gates, are required to determine the allxy signals and thus scarcely any design area is required on a memory.
  • the final classification of a data sequence (dl5 ..d ⁇ r4 ..r ⁇ ) thus takes place in two steps: firstly, the allxy information, i.e. the status bits, are checked and then, if necessary, the number of defective bits in the test sequence of a corresponding bitwise XOR operation is determined.
  • the data sequence VIII has a two-bit error in bit group a.
  • the result of the XOR operation contains two set bits, the data sequence is therefore incorrectably defective.
  • the data sequence IX has a two-bit error in bit groups a and b.
  • allOa O
  • Figure 4 shows the method forming the basis of the invention for the example of a memory (1).
  • the data bits (6) and redundancy bits (7) are transferred via an internal data bus (6, 7) of word width nd + nr both to the error correction unit (2) and also to the unit for test pattern evaluation (3).
  • a control line (8) and a multiplexer (4) in normal operation the corrected data (10) or in test operation the result of the test pattern evaluation (11) can be delivered to the external data bus (9) of word width nd.
  • the write path is not shown in this scheme.
  • the present invention thus describes a compaction, to be achieved by means of a few standard gates, of a physically stored data sequence on a storage medium having an error correction mechanism to at most the logical bit length of the data sequence, which allows a classification for the data patterns required during testing as to whether the data sequence is correct, correctable or incorrectably false, i.e. defective, and thereby makes it possible to achieve faster testing of a storage medium since only one read access per data sequence is required.
  • EEPROM Electrically Erasable Programmable Read-Only Memory
  • flash memory in which error correction mechanisms such as, for example, Hamming coding, are used, can be tested more rapidly with the method described here as long as the number of data patterns to be expected allows a suitable bit group formation and the data bus width is sufficiently large.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

L'invention concerne un procédé pour détecter une séquence de données défectueuse sur un support de stockage, la séquence de données contenant une pluralité de bits, incluant des bits de données et des bits de redondance, et concerne en outre un procédé pour tester un support de stockage. L'invention concerne en outre un dispositif pour détecter une séquence de données défectueuse sur un support de stockage. Pour réduire les deux accès généralement nécessaires à un support de stockage pour lire une séquence de données, à savoir une fois pour lire les bits de données et une fois pour lire les bits de redondance de la séquence de données, à un seul accès, il est proposé selon l'invention que le nombre total (nd + nr) de bits dans une séquence de données, comprenant nd bits de données et nr bits de redondance, puisse être réduit à la largeur d'un bus de données qui est identique à nd ou inférieur à nd de sorte que si la valeur d'espérance des données est connue, chaque erreur d'un seul bit peut être localisée et chaque erreur de plusieurs bits peut être détectée et distinguée des erreurs d'un seul bit. Un avantage de l'invention est que la lecture de séquences de données à partir d'un support de stockage dans le but de test est ainsi réduite de respectivement deux à un seul accès de lecture sans perte de couverture du test.
PCT/IB2008/051919 2007-06-20 2008-05-15 Détection de séquences de données défectueuses Ceased WO2008155678A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP07110667.8 2007-06-20
EP07110667 2007-06-20

Publications (1)

Publication Number Publication Date
WO2008155678A1 true WO2008155678A1 (fr) 2008-12-24

Family

ID=39930464

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2008/051919 Ceased WO2008155678A1 (fr) 2007-06-20 2008-05-15 Détection de séquences de données défectueuses

Country Status (1)

Country Link
WO (1) WO2008155678A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5959914A (en) * 1998-03-27 1999-09-28 Lsi Logic Corporation Memory controller with error correction memory test application
EP1069503A2 (fr) * 1999-07-12 2001-01-17 Matsushita Electronics Corporation Dispositif de mémoire à semiconducteurs disposant d'un circuit de code de correction d'erreur et méthode de test de la mémoire
US20050182997A1 (en) * 2004-02-13 2005-08-18 Keiichi Kushida Semiconductor device with memory and method for memory test

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5959914A (en) * 1998-03-27 1999-09-28 Lsi Logic Corporation Memory controller with error correction memory test application
EP1069503A2 (fr) * 1999-07-12 2001-01-17 Matsushita Electronics Corporation Dispositif de mémoire à semiconducteurs disposant d'un circuit de code de correction d'erreur et méthode de test de la mémoire
US20050182997A1 (en) * 2004-02-13 2005-08-18 Keiichi Kushida Semiconductor device with memory and method for memory test

Similar Documents

Publication Publication Date Title
CN110111834B (zh) 半导体存储器装置及其修复方法
US7779334B2 (en) Memory having an ECC system
US8286055B2 (en) Nonvolatile memory device and method of operating the same
JP3842238B2 (ja) メモリ・システム及びこれのテスト方法
US20060265636A1 (en) Optimized testing of on-chip error correction circuit
US8572444B2 (en) Memory apparatus and testing method thereof
US6259637B1 (en) Method and apparatus for built-in self-repair of memory storage arrays
US20030206470A1 (en) Self-repair of embedded memory arrays
US9104588B2 (en) Circuits, apparatuses, and methods for address scrambling
CN108877870A (zh) 用于修复操作的修复电路以及包括修复电路的存储器件
US10552261B2 (en) Semiconductor device and memory module
US4912710A (en) Self-checking random access memory
JP4504558B2 (ja) 半導体集積メモリ
US8402327B2 (en) Memory system with error correction and method of operation
US20070047347A1 (en) Semiconductor memory devices and a method thereof
US8321726B2 (en) Repairing memory arrays
US6366508B1 (en) Integrated circuit memory having column redundancy with no timing penalty
US7464309B2 (en) Method and apparatus for testing semiconductor memory device and related testing methods
US9312028B2 (en) Method for detecting permanent faults of an address decoder of an electronic memory device
US6560731B2 (en) Method for checking the functioning of memory cells of an integrated semiconductor memory
CN116072195B (zh) 存储器
WO2008155678A1 (fr) Détection de séquences de données défectueuses
CN101937722B (zh) 存储器装置及其相关测试方法
Lu et al. Integration of hard repair techniques with ECC for enhancing fabrication yield and reliability of embedded memories
Lu et al. Highly Efficient Built-In Self-Repair Techniques for NAND Flash Memory with Fine-Grained Redundancies

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08751211

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08751211

Country of ref document: EP

Kind code of ref document: A1