WO2009006284A2 - Dé semi-conducteur doté d'une couche de redistribution - Google Patents

Dé semi-conducteur doté d'une couche de redistribution Download PDF

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Publication number
WO2009006284A2
WO2009006284A2 PCT/US2008/068542 US2008068542W WO2009006284A2 WO 2009006284 A2 WO2009006284 A2 WO 2009006284A2 US 2008068542 W US2008068542 W US 2008068542W WO 2009006284 A2 WO2009006284 A2 WO 2009006284A2
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor die
die
recited
adhesive layer
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2008/068542
Other languages
English (en)
Other versions
WO2009006284A3 (fr
Inventor
Chien-Ko Liao
Chin-Tien Chiu
Jack Chang Chien
Cheemen Yu
Hem Takiar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SanDisk Corp
Original Assignee
SanDisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/769,937 external-priority patent/US7763980B2/en
Priority claimed from US11/769,927 external-priority patent/US7772047B2/en
Application filed by SanDisk Corp filed Critical SanDisk Corp
Priority to EP08796037.3A priority Critical patent/EP2179442A4/fr
Priority to CN2008800224541A priority patent/CN101765911B/zh
Publication of WO2009006284A2 publication Critical patent/WO2009006284A2/fr
Publication of WO2009006284A3 publication Critical patent/WO2009006284A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7402—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7432—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01204—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • Embodiments of the present invention relate to a redistribution layer for a semiconductor device and methods of forming same.
  • Non-volatile semiconductor memory devices such as flash memory storage cards
  • flash memory storage cards are becoming widely used to meet the ever-growing demands on digital information storage and exchange.
  • Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including for example digital cameras, digital music players, video game consoles, PDAs and cellular telephones.
  • flash memory storage cards may in general be fabricated as system-in-a-package (SiP) or multichip modules (MCM), where a plurality of die are mounted and interconnected on a small footprint substrate.
  • the substrate may in general include a rigid, dielectric base having a conductive layer etched on one or both sides. Electrical connections are formed between the die and the conductive layer(s), and the conductive layer(s) provide an electric lead structure for connection of the die to a host device. Once electrical connections between the die and substrate are made, the assembly is then typically encased in a molding compound to provide a protective package.
  • FIG. 1 A top view of a conventional semiconductor package 20 (without molding compound) is shown in Fig. 1.
  • Typical packages include a plurality of semiconductor die, such as die 22 and 24, affixed to a substrate 26.
  • a plurality of die bond pads 28 may be formed on the semiconductor die 22, 24 during the die fabrication process.
  • a plurality of contact pads 30 may be formed on the substrate 26.
  • Die 22 may be affixed to the substrate 26, and then die 24 may be mounted on die 22. Both die are then electrically coupled to the substrate by affixing wire bonds 32 between respective die bond pad 28 and contact pad 30 pairs.
  • traces 38 and bond pads 40 are formed on the top surface of the die.
  • the traces 38 and bond pads 28a may be covered with an insulator, leaving only the newly formed die bond pads 40 exposed.
  • the traces 38 connect the existing die bond pads 28a with the newly formed die bond pads 40 to effectively relocate the die bond pads to an edge of the die having a pin-out connection to the substrate.
  • Additional contact pads 30 may be formed on the substrate to allow electrical connection between the substrate and the bond pads 28a.
  • the additional contact pads 30 may be formed in-line with the remaining contact pads 30 as shown in prior art Fig. 1. Alternatively, where there is available space, the additional contact pads 30 may be staggered with the remaining contact pads as shown in prior art Fig. 2. [0007] Current photolithography and other methods for forming a redistribution layer on semiconductor die are cumbersome, adding large numbers of process steps and expense to the fabrication process. There is therefore a need for a streamlined process for forming a redistribution layer.
  • Embodiments of the present invention relate to a semiconductor device having a redistribution layer and methods of forming same.
  • a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer.
  • the tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape.
  • the film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material.
  • the tape assembly is applied to the surface of the wafer so that the adhesive layer of the film assembly lies in contact with the surface of the wafer.
  • the adhesive is a b-stage adhesive which adheres to the wafer, but which is pliable and can be removed.
  • focused heat such as for example from a laser
  • the laser is programmed to focus its energy at the interface between the adhesive layer and the surface of the semiconductor wafer.
  • the adhesive layer is heated and cured to the surface of the semiconductor wafer so as to be permanently affixed to the semiconductor wafer along the path traced by the laser where heat is applied.
  • the path of the laser is computer-controlled so as to trace out, on each semiconductor die, the pattern of the redistribution layer to be defined on each semiconductor die.
  • the adhesive layer of the tape assembly may be fused to the surface of each semiconductor die along a thin and sharply defined path.
  • the adhesive layer on either side of the paths defined by the focused heat remains in the b-stage, or otherwise uncured, and may be peeled away from the surface of the wafer while those areas which have been fused remain on the wafer surface. Accordingly, as the tape assembly is pulled away from the wafer, the heated areas of the film assembly tear away from the areas of film assembly which are not heated, and the heated areas of film assembly are left behind on the surfaces of each semiconductor die to define a redistribution layer pattern on each semiconductor die.
  • Figure 1 is a top view of a conventional semiconductor package including a semiconductor die having a redistribution layer to redistribute die bond pads from a first edge to a second edge of the die.
  • Figure 2 is a top view of a conventional semiconductor package including a die having a redistribution layer as in Fig. 1 with an alternative substrate contact pad arrangement.
  • Figure 3 is a perspective view of a semiconductor wafer covered by a tape assembly from a roll of tape according to embodiments of the present invention.
  • Figure 4 is a side view of a tape assembly being placed over semiconductor die of a semiconductor wafer according to embodiments of the present invention.
  • Figure 5 is a side view of a film assembly including an adhesive layer and conductive material according to embodiments of the present invention.
  • Figure 6 is a side view of a tape assembly affixed to semiconductor die of a semiconductor wafer and further including a laser tracing a redistribution pattern into the surface of the tape assembly.
  • Figure 7 is a top view of a semiconductor die with the tape assembly positioned thereon and the redistribution layer pattern lased into the tape assembly.
  • Figure 8 is a side view of the tape assembly being removed from a semiconductor wafer, leaving behind the redistribution layer pattern traced by the laser.
  • Figure 9 shows a plurality of semiconductor die singulated from the wafer.
  • Figure 10 is a top view of a singulated die including a redistribution layer formed according to embodiments of the present invention.
  • Figure 11 is a side view of an alternative method of separating the semiconductor die from the new tape assembly.
  • Figure 12 is a cross-sectional side view of a semiconductor package including a semiconductor die having a redistribution layer formed according to embodiments of the present invention.
  • FIG. 3 there is shown a top view of a semiconductor wafer 100 including a plurality of semiconductor die 102 (only some of which are numbered in Fig. 3).
  • Each semiconductor die 102 on wafer 100 has been processed to include an integrated circuit as is known in the art capable of performing a specified electronic function. All of semiconductor die 102 on wafer 100 may have the same integrated circuit, though it is contemplated that different die may have different integrated circuits in alternative embodiments. As is known in the art, the respective integrated circuits may be tested during wafer fabrication to identify defective or bad die.
  • each of the die 102 Upon completion of wafer fabrication testing, normally each of the die 102 would be singulated into individual die and thereafter assembled into a semiconductor package. However, according to an embodiment of the present invention, each semiconductor die may have a redistribution layer formed thereon as explained below.
  • Fig. 3 further shows a roll 104 including a tape assembly 106 for forming the redistribution layer on the respective die 102 of wafer 100.
  • the tape assembly 106 may have a width sufficient to be applied over the entire surface of wafer 100 as shown in Fig. 3. It is alternatively contemplated that tape assembly 106 has a width sufficient to cover only a single row of semiconductor die 102 on wafer 100 or two or more rows of semiconductor die 102.
  • tape assembly 106 includes a polyimide tape 108, referred to as a backgrind tape as is known in the art, to which is affixed a film assembly 110.
  • film assembly 110 includes an adhesive layer 116 on which is deposited a conductive material 114.
  • Adhesive material 116 may be any of a variety of known electrically insulating adhesive films, such as for example those available from Nitto Denko Corp. of Japan, Abel Stick Co., California or Henkel Corporation, California.
  • Adhesive material 116 may for example be a curable b-stage adhesive which is sticky and pliable prior to being applied to wafer 100 and prior to being cured.
  • Conductive material 114 may be a variety of electrical conductors, such as for example aluminum, titanium, or alloys thereof. Conductive material 114 may be applied to the surface of adhesive layer 116 by a variety of known methods including for example sputtering, plating, screen printing, photolithographic processes, or a variety of other deposition processes. Such processes allow conductive material 114 to be applied with a very small thickness, such as for example between 1 and 5 microns, and more particularly between 1 and 3 microns. It is understood that the thickness of the conductive material 114 on adhesive layer 116 may be less than 1 micron and greater than 5 microns in alternative embodiments of the present invention.
  • tape assembly 110 is applied to backgrind tape 108 to form tape assembly 106.
  • Tape 108 may also have an adhesive surface for adhering the conductive material 114 of the film assembly 110 to the backgrind tape 108.
  • tape assembly 106 is applied onto semiconductor wafer 100 so that the adhesive layer 116 of tape assembly 106 is applied to the surfaces of the semiconductor die 102 on wafer 100.
  • the adhesive layer 116 is sticky and adheres to the surface of wafer 100.
  • the adhesive layer 116 is not yet cured and, in this stage, the adhesive layer 116 may be pulled away from the surface of wafer 100.
  • the backgrind tape 108 may be thinned in a backgrind process to thin the tape assembly 106.
  • the backgrind process may be omitted in alternative embodiments.
  • this focused heat is applied to the interface between tape assembly 106 and the wafer 100 (and in particular, the interface between adhesive layer 116 and the surface of wafer 100).
  • this focused heat may be applied by one of a variety of lasers 120, including for example CO2 lasers, UV lasers, YBO4 lasers, argon lasers, etc.
  • lasers are manufactured for example by Rofin-Sinar Technologies of Hamburg, Germany.
  • the laser is programmed to focus its energy at the interface between adhesive layer 116 and the surface of the semiconductor wafer 100.
  • the adhesive layer 116 is heated and cured to the surface of the semiconductor wafer so as to be permanently affixed to the semiconductor wafer along the path traced by the laser where heat is applied.
  • the path of the laser is computer-controlled so as to trace out, on each semiconductor die 102, the pattern of the redistribution layer to be defined on each semiconductor die 102. For example, as shown in Fig. 7, it may be desirable to redistribute a first pair of die bond pads 124 along the top edge of semiconductor die 102 to a pair of die bond pads 126 along an adjacent edge of semiconductor die 102. Accordingly, laser 120 will trace out the redistribution layer pattern including paths 130 and 132 on tape assembly 106 as shown in dash lines in Fig. 7.
  • paths 130 and 132 are by way of example only, and a wide variety of redistribution layer patterns may be traced out by laser 120 to redistribute die bond pads from a first location on each of the semiconductor die 102 to a second location on each of the semiconductor die 102. While a single laser 120 is shown in Fig. 6, it is understood that a plurality of lasers 120 may be used to simultaneously trace out the redistribution layer pattern on a plurality of semiconductor die.
  • the adhesive layer 116 of tape assembly 106 may be fused to the surface of each semiconductor die 102 along a thin and sharply defined path.
  • the adhesive layer 116 on either side of the paths defined by the focused heat remains in the b-stage, or otherwise uncured, and may be peeled away from the surface of the wafer 100 as shown in Fig. 8, while those areas which have been fused remain on the wafer surface.
  • Figs. 9 and 10 after the uncured portions of tape assembly 106 are removed from the semiconductor wafer 100, the wafer 100 is singulated into individual semiconductor die 102, each of which includes the redistribution layer pattern 136 as defined by the heat source.
  • Fig. 10 is a top view of a singulated semiconductor die 102 including a redistribution layer pattern 136 for redistributing die bond pads 124 at the top of the die to die bond pads 126 along the adjacent edge of the die.
  • the adhesive layer 116 on the surface of the semiconductor die is an electrical insulator.
  • a variety of processes are known for electrically coupling the conductive material of redistribution layer pattern 136 to die bond pads 124 and 126. After the pattern is electrically coupled to die bond pads 124 and 126, a passivation layer may be formed on the surface of semiconductor die 102 as is known to cover the exposed redistribution layer pattern 136 and, optionally, die bond pads 124. Die bond pads 126 remain exposed.
  • Fig. 11 illustrates an alternative method for forming a redistribution layer on die 102.
  • Tape assembly 106 is applied to wafer 100, and a heat source such as a laser traces out the redistribution layer pattern 136 on each of the semiconductor die 102, as described above.
  • the semiconductor wafer 100 is flipped over and is supported by the tape assembly 106 on a wafer chuck or the like.
  • the die 102 are singulated while still in contact with tape assembly 106.
  • a robotic device 140 such as a pick and place robot, grips the back side of each semiconductor die 102 and pulls the respective die 102 away from tape assembly 106.
  • those areas of the film assembly 110 which have been heated and fused to the surface of the respective semiconductor die 102 tear away from the backgrind tape 108 and remain with the semiconductor die 102 when robotic device 140 pulls the singulated die 102 away from tape assembly 106.
  • the unheated portions of the film assembly 110 remain on tape assembly 106, on the wafer chuck.
  • one or more die bond pads may be redistributed from any first location to any second location on a semiconductor die 102 by a redistribution layer across the die formed at the wafer level.
  • the die 102 may be mounted on a substrate 160.
  • the die 102 may be the only die mounted on a substrate 160, or the die 102 may be mounted on substrate 160 along with one or more additional die 162 and passive components 164 as shown in Fig. 12.
  • the die bond pads on die 102, and any other die may be wire bonded to contact pads on substrate 160 using wire bonds 166 in a known wire bond process.
  • the die and substrate together may function as a flash memory device 170, where die 102 may be a controller such as an ASIC or a flash memory die.
  • the die 102 may be other than a controller or flash memory die in alternative embodiments, and the die and substrate together may be other than a flash memory device in alternative embodiments.
  • contact fingers 168 may further be provided on substrate 160 for exchanging signals between the device 170 and a host device within which the device 170 is inserted.
  • the individual semiconductor packages may be encased within the molding compound 168 to form a finished semiconductor die package 170.
  • Molding compound 168 may be a known epoxy such as for example available from Sumitomo Corp. and Nitto Denko Corp., both having headquarters in Japan.
  • the package 170 shown in Fig. 12 may be a finished portable memory card. Alternatively, the package 170 may be enclosed within a lid to form the completed portable memory card.

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

La présente invention a trait à un dispositif à semi-conducteur doté d'une couche de redistribution et à ses procédés de formation. Après la fabrication d'un dé semi-conducteur sur une tranche, un assemblage de bande est appliqué sur une surface de la tranche, en contact avec les surfaces de chaque dé semi-conducteur sur la tranche. L'assemblage de bande inclut une bande d'affûtage arrière en tant que couche de base et un assemblage de film collé à la bande d'affûtage arrière. L'assemblage de film inclut à son tour un film adhésif sur lequel est déposée une couche mince de matériau conducteur. Le motif de la couche de redistribution est tracé dans l'assemblage de bande, à l'aide par exemple d'un laser. Par la suite, les parties non chauffées de l'assemblage de bande peuvent être supprimées, ce qui laisse le motif de la couche de redistribution chauffé sur chaque dé semi-conducteur.
PCT/US2008/068542 2007-06-28 2008-06-27 Dé semi-conducteur doté d'une couche de redistribution Ceased WO2009006284A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP08796037.3A EP2179442A4 (fr) 2007-06-28 2008-06-27 Dé semi-conducteur doté d'une couche de redistribution
CN2008800224541A CN101765911B (zh) 2007-06-28 2008-06-27 具有重新分布层的半导体芯片

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/769,937 2007-06-28
US11/769,937 US7763980B2 (en) 2007-06-28 2007-06-28 Semiconductor die having a distribution layer
US11/769,927 2007-06-28
US11/769,927 US7772047B2 (en) 2007-06-28 2007-06-28 Method of fabricating a semiconductor die having a redistribution layer

Publications (2)

Publication Number Publication Date
WO2009006284A2 true WO2009006284A2 (fr) 2009-01-08
WO2009006284A3 WO2009006284A3 (fr) 2009-04-09

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/068542 Ceased WO2009006284A2 (fr) 2007-06-28 2008-06-27 Dé semi-conducteur doté d'une couche de redistribution

Country Status (5)

Country Link
EP (1) EP2179442A4 (fr)
KR (1) KR101475467B1 (fr)
CN (1) CN101765911B (fr)
TW (1) TWI371807B (fr)
WO (1) WO2009006284A2 (fr)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015127486A1 (fr) * 2014-02-28 2015-09-03 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Procédé de fabrication d'un circuit imprimé à puce de capteur incorporée ainsi que circuit imprimé
WO2015138359A1 (fr) * 2014-03-10 2015-09-17 Deca Technologies Inc. Dispositif semi-conducteur et procédé comprenant des couches de redistribution épaissies
US9177926B2 (en) 2011-12-30 2015-11-03 Deca Technologies Inc Semiconductor device and method comprising thickened redistribution layers
US9576919B2 (en) 2011-12-30 2017-02-21 Deca Technologies Inc. Semiconductor device and method comprising redistribution layers
US9613830B2 (en) 2011-12-30 2017-04-04 Deca Technologies Inc. Fully molded peripheral package on package device
US9831170B2 (en) 2011-12-30 2017-11-28 Deca Technologies, Inc. Fully molded miniaturized semiconductor module
US9887103B2 (en) 2010-02-16 2018-02-06 Deca Technologies, Inc. Semiconductor device and method of adaptive patterning for panelized packaging
US10050004B2 (en) 2015-11-20 2018-08-14 Deca Technologies Inc. Fully molded peripheral package on package device
US10157803B2 (en) 2016-09-19 2018-12-18 Deca Technologies Inc. Semiconductor device and method of unit specific progressive alignment
US10373870B2 (en) 2010-02-16 2019-08-06 Deca Technologies Inc. Semiconductor device and method of packaging
US10573601B2 (en) 2016-09-19 2020-02-25 Deca Technologies Inc. Semiconductor device and method of unit specific progressive alignment
US10672624B2 (en) 2011-12-30 2020-06-02 Deca Technologies Inc. Method of making fully molded peripheral package on package device
US11056453B2 (en) 2019-06-18 2021-07-06 Deca Technologies Usa, Inc. Stackable fully molded semiconductor structure with vertical interconnects
US12438065B2 (en) 2021-07-01 2025-10-07 Deca Technologies Usa, Inc. Fully molded semiconductor structure with through silicon via (TSV) vertical interconnects

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106469657B (zh) * 2015-08-14 2020-03-31 晟碟半导体（上海）有限公司 具有间隔体层的半导体装置、其形成方法和间隔体层带

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN87107692A (zh) * 1986-11-13 1988-05-25 Mt化学公司 半导体器件的制造方法
US6011314A (en) * 1999-02-01 2000-01-04 Hewlett-Packard Company Redistribution layer and under bump material structure for converting periphery conductive pads to an array of solder bumps
US6036809A (en) * 1999-02-16 2000-03-14 International Business Machines Corporation Process for releasing a thin-film structure from a substrate
JP2001323228A (ja) * 2000-05-15 2001-11-22 Nitto Denko Corp 加熱剥離型粘着シート
JP2002076576A (ja) * 2000-08-23 2002-03-15 Nec Corp 配線パターン形成方法およびその方法に用いられる原版
US6847105B2 (en) * 2001-09-21 2005-01-25 Micron Technology, Inc. Bumping technology in stacked die configurations
US6965160B2 (en) * 2002-08-15 2005-11-15 Micron Technology, Inc. Semiconductor dice packages employing at least one redistribution layer
US20040191955A1 (en) * 2002-11-15 2004-09-30 Rajeev Joshi Wafer-level chip scale package and method for fabricating and using the same
JP2005085799A (ja) * 2003-09-04 2005-03-31 Seiko Epson Corp 成膜方法、配線パターンの形成方法、半導体装置の製造方法、電気光学装置、及び電子機器
US7410825B2 (en) * 2005-09-15 2008-08-12 Eastman Kodak Company Metal and electronically conductive polymer transfer

Cited By (16)

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US9887103B2 (en) 2010-02-16 2018-02-06 Deca Technologies, Inc. Semiconductor device and method of adaptive patterning for panelized packaging
US10373870B2 (en) 2010-02-16 2019-08-06 Deca Technologies Inc. Semiconductor device and method of packaging
US10672624B2 (en) 2011-12-30 2020-06-02 Deca Technologies Inc. Method of making fully molded peripheral package on package device
US10373902B2 (en) 2011-12-30 2019-08-06 Deca Technologies Inc. Fully molded miniaturized semiconductor module
US9613830B2 (en) 2011-12-30 2017-04-04 Deca Technologies Inc. Fully molded peripheral package on package device
US9831170B2 (en) 2011-12-30 2017-11-28 Deca Technologies, Inc. Fully molded miniaturized semiconductor module
US9177926B2 (en) 2011-12-30 2015-11-03 Deca Technologies Inc Semiconductor device and method comprising thickened redistribution layers
US9576919B2 (en) 2011-12-30 2017-02-21 Deca Technologies Inc. Semiconductor device and method comprising redistribution layers
WO2015127486A1 (fr) * 2014-02-28 2015-09-03 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Procédé de fabrication d'un circuit imprimé à puce de capteur incorporée ainsi que circuit imprimé
WO2015138359A1 (fr) * 2014-03-10 2015-09-17 Deca Technologies Inc. Dispositif semi-conducteur et procédé comprenant des couches de redistribution épaissies
US10050004B2 (en) 2015-11-20 2018-08-14 Deca Technologies Inc. Fully molded peripheral package on package device
US10157803B2 (en) 2016-09-19 2018-12-18 Deca Technologies Inc. Semiconductor device and method of unit specific progressive alignment
US10573601B2 (en) 2016-09-19 2020-02-25 Deca Technologies Inc. Semiconductor device and method of unit specific progressive alignment
US11056453B2 (en) 2019-06-18 2021-07-06 Deca Technologies Usa, Inc. Stackable fully molded semiconductor structure with vertical interconnects
US12261140B2 (en) 2019-06-18 2025-03-25 Deca Technologies Usa, Inc. Stackable fully molded semiconductor structure with vertical interconnects
US12438065B2 (en) 2021-07-01 2025-10-07 Deca Technologies Usa, Inc. Fully molded semiconductor structure with through silicon via (TSV) vertical interconnects

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CN101765911B (zh) 2012-06-27
KR20100034756A (ko) 2010-04-01
WO2009006284A3 (fr) 2009-04-09
TWI371807B (en) 2012-09-01
EP2179442A2 (fr) 2010-04-28
CN101765911A (zh) 2010-06-30
TW200910474A (en) 2009-03-01
KR101475467B1 (ko) 2014-12-22
EP2179442A4 (fr) 2013-08-07

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