WO2009038169A1 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
WO2009038169A1
WO2009038169A1 PCT/JP2008/066971 JP2008066971W WO2009038169A1 WO 2009038169 A1 WO2009038169 A1 WO 2009038169A1 JP 2008066971 W JP2008066971 W JP 2008066971W WO 2009038169 A1 WO2009038169 A1 WO 2009038169A1
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WIPO (PCT)
Prior art keywords
semiconductor device
semiconductor package
circuit board
region
flexible circuit
Prior art date
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Ceased
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PCT/JP2008/066971
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English (en)
French (fr)
Inventor
Takao Yamazaki
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NEC Corp
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NEC Corp
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Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to US12/515,437 priority Critical patent/US7928556B2/en
Priority to JP2009533196A priority patent/JP4450113B2/ja
Priority to KR1020097010192A priority patent/KR101174056B1/ko
Priority to EP08831960A priority patent/EP2192613A4/en
Priority to CN2008800011422A priority patent/CN101569008B/zh
Publication of WO2009038169A1 publication Critical patent/WO2009038169A1/ja
Anticipated expiration legal-status Critical
Priority to US13/024,910 priority patent/US8093709B2/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of flexible or folded printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H—ELECTRICITY
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    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
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    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/688—Flexible insulating substrates
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/05—Flexible printed circuits [FPCs]
    • H05K2201/056—Folded around rigid support or component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10515—Stacked components
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
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    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07202—Connecting or disconnecting of bump connectors using auxiliary members
    • H10W72/07204—Connecting or disconnecting of bump connectors using auxiliary members using temporary auxiliary members, e.g. sacrificial coatings
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    • H10W72/07221—Aligning
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • H10W72/07338—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy hardening the adhesive by curing, e.g. thermosetting
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • H10W72/07339—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy hardening the adhesive by cooling, e.g. thermoplastics
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
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    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
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    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
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    • H10W72/874—On different surfaces
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    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
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    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

　品質保証された（検査済みの）、市販のチップサイズパッケージを積層可能な低コストな半導体装置であり、且つコプラナリティの値が小さく実装信頼性に優れた半導体装置を提供する。可撓性回路基板が半導体パッケージの側面の少なくとも一部と接着され、且つ半導体パッケージのはんだボール搭載面側に位置する可撓性回路基板が、半導体パッケージの外端部よりも内側の領域であって、且つ半導体パッケージに搭載された最外部のはんだボールよりも外側である領域で折り曲げられていることを特徴とする半導体装置及びその製造方法である。
PCT/JP2008/066971 2007-09-19 2008-09-19 半導体装置及びその製造方法 Ceased WO2009038169A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
US12/515,437 US7928556B2 (en) 2007-09-19 2008-09-19 Semiconductor device and manufacturing method thereof
JP2009533196A JP4450113B2 (ja) 2007-09-19 2008-09-19 半導体装置及びその製造方法
KR1020097010192A KR101174056B1 (ko) 2007-09-19 2008-09-19 반도체 장치 및 그 제조 방법
EP08831960A EP2192613A4 (en) 2007-09-19 2008-09-19 SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD THEREFOR
CN2008800011422A CN101569008B (zh) 2007-09-19 2008-09-19 半导体装置及其制造方法
US13/024,910 US8093709B2 (en) 2007-09-19 2011-02-10 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-242396 2007-09-19
JP2007242396 2007-09-19

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/024,910 Continuation US8093709B2 (en) 2007-09-19 2011-02-10 Semiconductor device and manufacturing method thereof

Publications (1)

Publication Number Publication Date
WO2009038169A1 true WO2009038169A1 (ja) 2009-03-26

Family

ID=40467978

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/066971 Ceased WO2009038169A1 (ja) 2007-09-19 2008-09-19 半導体装置及びその製造方法

Country Status (6)

Country Link
US (3) US7928556B2 (ja)
EP (1) EP2192613A4 (ja)
JP (1) JP4450113B2 (ja)
KR (1) KR101174056B1 (ja)
CN (1) CN101569008B (ja)
WO (1) WO2009038169A1 (ja)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011065544A1 (ja) * 2009-11-27 2011-06-03 日本電気株式会社 半導体装置、３次元実装型半導体装置、半導体モジュール、電子機器、及びその製造方法
JP2011171411A (ja) * 2010-02-17 2011-09-01 Nec Tohoku Ltd 半導体装置の製造方法
US20120074589A1 (en) * 2010-09-27 2012-03-29 Xilinx, Inc. Corner structure for ic die
JP2014011385A (ja) * 2012-07-02 2014-01-20 Nec Access Technica Ltd 電子デバイス、電子機器、および電子デバイスの製造方法
JP2017011274A (ja) * 2015-06-25 2017-01-12 スリーディー プラス ボールグリッドアレイパッケージの積層を含む３次元電子モジュール
CN112713131A (zh) * 2019-10-27 2021-04-27 台湾积体电路制造股份有限公司 半导体器件、包含半导体器件的电子器件以及其制造方法

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009006757B3 (de) * 2009-01-30 2010-08-19 Continental Automotive Gmbh Lötstopplack-Beschichtung für starrbiegsame Leiterplatten
US9299648B2 (en) * 2009-03-04 2016-03-29 Stats Chippac Ltd. Integrated circuit packaging system with patterned substrate and method of manufacture thereof
KR101372233B1 (ko) 2009-10-09 2014-03-11 한국전자통신연구원 미세 유체 소자 및 이를 이용한 유체 흐름 제어 방법
CN102117789B (zh) * 2010-01-04 2013-12-04 三星半导体(中国)研究开发有限公司 半导体芯片封装结构及封装方法
US8217507B1 (en) * 2010-01-22 2012-07-10 Amkor Technology, Inc. Edge mount semiconductor package
TWI440412B (zh) * 2011-12-28 2014-06-01 巨擘科技股份有限公司 超薄多層基板之封裝方法
CN103681458B (zh) * 2012-09-03 2016-06-01 华进半导体封装先导技术研发中心有限公司 一种制作嵌入式超薄芯片的三维柔性堆叠封装结构的方法
CN103117252B (zh) * 2013-02-25 2015-08-05 华进半导体封装先导技术研发中心有限公司 一种对二维封装柔性基板进行三维折叠封装的方法
CN103400814B (zh) * 2013-08-03 2016-02-03 华进半导体封装先导技术研发中心有限公司 一种柔性基板封装结构及其封灌方法
US9282649B2 (en) * 2013-10-08 2016-03-08 Cisco Technology, Inc. Stand-off block
US9196586B2 (en) 2014-02-13 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package including an embedded surface mount device and method of forming the same
CN105810654A (zh) * 2014-12-30 2016-07-27 展讯通信（上海）有限公司 一种引线框架型封装体
US11201096B2 (en) * 2019-07-09 2021-12-14 Texas Instruments Incorporated Packaged device with die wrapped by a substrate
CN112885727B (zh) * 2021-01-19 2022-04-29 广西桂芯半导体科技有限公司 一种芯片集成电路封装及其制造方法
US12154860B2 (en) * 2021-06-16 2024-11-26 SanDisk Technologies, Inc. Method of forming a semiconductor device including vertical contact fingers
CN114420574B (zh) * 2022-03-31 2022-06-21 威海嘉瑞光电科技股份有限公司 一种柔性封装构件及其形成方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0922976A (ja) * 1995-07-05 1997-01-21 Shinko Electric Ind Co Ltd 半導体装置
US5805422A (en) 1994-09-21 1998-09-08 Nec Corporation Semiconductor package with flexible board and method of fabricating the same
US20010054762A1 (en) 2000-05-23 2001-12-27 Nec Corporation Semiconductor device and method of fabricating the same
US6576992B1 (en) 2001-10-26 2003-06-10 Staktek Group L.P. Chip scale stacking system and method
JP2004146751A (ja) * 2002-08-30 2004-05-20 Nec Corp 半導体装置及びその製造方法、回路基板、電子機器並びに半導体装置の製造装置
US20050161793A1 (en) 2002-12-17 2005-07-28 Takao Ohno Semiconductor device and stacked semiconductor device that can increase flexibility in designing a stacked semiconductor device
US20060049495A1 (en) 2002-11-20 2006-03-09 Nec Corporation Semiconductor package and laminated semiconductor package

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08335663A (ja) * 1995-06-08 1996-12-17 Sony Corp 半導体装置及び半導体装置の製造方法
JP3552422B2 (ja) 1996-10-04 2004-08-11 株式会社デンソー ボールグリッドアレイ半導体装置及びその実装方法
JP2002076263A (ja) 2000-08-31 2002-03-15 Hitachi Ltd 半導体装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5805422A (en) 1994-09-21 1998-09-08 Nec Corporation Semiconductor package with flexible board and method of fabricating the same
JPH0922976A (ja) * 1995-07-05 1997-01-21 Shinko Electric Ind Co Ltd 半導体装置
US20010054762A1 (en) 2000-05-23 2001-12-27 Nec Corporation Semiconductor device and method of fabricating the same
US6576992B1 (en) 2001-10-26 2003-06-10 Staktek Group L.P. Chip scale stacking system and method
JP2004146751A (ja) * 2002-08-30 2004-05-20 Nec Corp 半導体装置及びその製造方法、回路基板、電子機器並びに半導体装置の製造装置
US20060055053A1 (en) 2002-08-30 2006-03-16 Nec Corporation Semiconductor device and method for manufacturing the same, circuit board, electronic apparatus, and semiconductor device manufacturing apparatus
US20060049495A1 (en) 2002-11-20 2006-03-09 Nec Corporation Semiconductor package and laminated semiconductor package
US20050161793A1 (en) 2002-12-17 2005-07-28 Takao Ohno Semiconductor device and stacked semiconductor device that can increase flexibility in designing a stacked semiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2192613A4

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011065544A1 (ja) * 2009-11-27 2011-06-03 日本電気株式会社 半導体装置、３次元実装型半導体装置、半導体モジュール、電子機器、及びその製造方法
JPWO2011065544A1 (ja) * 2009-11-27 2013-04-18 日本電気株式会社 半導体装置、３次元実装型半導体装置、半導体モジュール、電子機器、及びその製造方法
JP2011171411A (ja) * 2010-02-17 2011-09-01 Nec Tohoku Ltd 半導体装置の製造方法
US20120074589A1 (en) * 2010-09-27 2012-03-29 Xilinx, Inc. Corner structure for ic die
US8659169B2 (en) * 2010-09-27 2014-02-25 Xilinx, Inc. Corner structure for IC die
JP2014011385A (ja) * 2012-07-02 2014-01-20 Nec Access Technica Ltd 電子デバイス、電子機器、および電子デバイスの製造方法
JP2017011274A (ja) * 2015-06-25 2017-01-12 スリーディー プラス ボールグリッドアレイパッケージの積層を含む３次元電子モジュール
CN112713131A (zh) * 2019-10-27 2021-04-27 台湾积体电路制造股份有限公司 半导体器件、包含半导体器件的电子器件以及其制造方法
US12557710B2 (en) 2019-10-27 2026-02-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device, electronic device including the same, and manufacturing method thereof

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EP2192613A1 (en) 2010-06-02
US8093709B2 (en) 2012-01-10
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EP2192613A4 (en) 2011-03-16
CN101569008B (zh) 2012-05-02
JPWO2009038169A1 (ja) 2011-01-06
KR101174056B1 (ko) 2012-08-13
US7928556B2 (en) 2011-04-19
US20110140264A1 (en) 2011-06-16
US20120028419A1 (en) 2012-02-02
US20100025844A1 (en) 2010-02-04
CN101569008A (zh) 2009-10-28
US8236616B2 (en) 2012-08-07

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