WO2009057924A2 - Pixel d'unité de répétition 4t-2s - Google Patents

Pixel d'unité de répétition 4t-2s Download PDF

Info

Publication number
WO2009057924A2
WO2009057924A2 PCT/KR2008/006337 KR2008006337W WO2009057924A2 WO 2009057924 A2 WO2009057924 A2 WO 2009057924A2 KR 2008006337 W KR2008006337 W KR 2008006337W WO 2009057924 A2 WO2009057924 A2 WO 2009057924A2
Authority
WO
WIPO (PCT)
Prior art keywords
diffusion area
area pattern
photodiode
photodiode diffusion
corner
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/KR2008/006337
Other languages
English (en)
Other versions
WO2009057924A3 (fr
Inventor
Do Young Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix System IC Inc
Original Assignee
Siliconfile Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconfile Technologies Inc filed Critical Siliconfile Technologies Inc
Publication of WO2009057924A2 publication Critical patent/WO2009057924A2/fr
Publication of WO2009057924A3 publication Critical patent/WO2009057924A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/802—Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/813—Electronic components shared by multiple pixels, e.g. one amplifier shared by two pixels

Definitions

  • the present invention relates to a step & repeat unit cell, and more particularly, to a
  • An image sensor is implemented by arranging a plurality of image sensor unit cells in a two-dimensional array structure. That is, a horizontal image sensor unit line is formed by repeatedly arranging a single type of image sensor unit cells in a horizontal direction through a step & repeat process, and then, a vertical image sensor unit line is formed by repeatedly arranging in a vertical direction image sensor unit cells extended from each image sensor unit cell of the horizontal image sensor unit line, thereby implementing a single image sensor.
  • the image sensor unit cell used in such a process is called a step & repeat unit cell.
  • step & repeat unit cell is generally used in a layout stage, the concept of the step & repeat unit cell will be described using a circuit diagram rather than a layout diagram.
  • FIG. 1 is a circuit diagram for describing a process of forming a 4T-2S step & repeat unit cell by combining two image sensor circuits each having four transistors.
  • the 4T-2S step & repeat unit pixel 100 shown in the right-hand side is obtained by combining two step & repeat unit cells 10 and 20 shown in the left- hand side, each having four transistors.
  • a first step & repeat unit cell 10 includes a single photodiode PDl and an image signal conversion circuit for converting image signals generated from the photodiode PDl into electric signals.
  • the image signal conversion circuit has four transistors Mi l, Ml 2, M13, and M 14.
  • the second step & repeat unit cell 20 has a similar structure to the first step & repeat unit cell 10, the reference numerals of its components are differently denoted just for a distinguishing purpose.
  • the 4T-2S step & repeat unit pixel 100 is obtained by sharing a reset transistor M 12 or M22, a conversion transistor M 13 or M23, and a selection transistor M 14 or M24 between two 4T step & repeat unit cell 10 and 20 each having four transistors.
  • the 4T-2S step & repeat unit cell 100 detects and transmits charges corresponding to image signals generated from two photodiodes PDl and PD2 using two transmission transistors Mi l and M21 and three transistors MC2, MC3, and MC4 that are commonly shared.
  • the reset signal Rxl2 applied to the gate of the reset transistor MC2 is enabled once at a corresponding time period when either of the charge transmission control signal TxI or Tx2 applied to the gate of the transmission transistor Ml 1 or M21 is enabled. This fact is reflected in the reference numeral "12" of Rxl2. Similarly, the reference numeral "12" of the selection signal Sxl2 applied to the gate of the selection transistor MC4 is named for the same reason.
  • the 4T-2S step & repeat unit cell obtained by combining two step & repeat unit cells each having four transistors can be laid out in various manners.
  • the most important thing to be considered when the 4T-2S step & repeat unit cell is laid out is an aperture ratio. Disclosure of Invention Technical Problem
  • the present invention provides a layout pattern of a 4T-2S step & repeat unit cell having an improved aperture ratio.
  • a 4T-2S step & repeat unit cell comprising a first photodiode diffusion area pattern, a second photodiode diffusion area pattern, a third photodiode diffusion area pattern, a fourth photodiode diffusion area pattern, a first image signal conversion circuit diffusion area pattern, and a second image signal conversion circuit diffusion area pattern.
  • the second photodiode diffusion area pattern is formed in a diagonal direction from the first photodiode diffusion area pattern.
  • the third photodiode diffusion area pattern is formed above the first photodiode diffusion area pattern beside the second photodiode diffusion area pattern.
  • the fourth photodiode diffusion area pattern is formed in a diagonal direction from the third photodiode diffusion area pattern above the second photodiode diffusion area pattern.
  • the first image signal conversion circuit diffusion area pattern is formed beside the first photodiode diffusion area pattern below the second photodiode diffusion area pattern.
  • the second image signal conversion circuit diffusion area pattern is formed above the third photodiode diffusion area pattern beside the fourth photodiode diffusion area pattern.
  • a 4T-2S step & repeat unit cell comprising a first photodiode diffusion area pattern, a second photodiode diffusion area pattern, a third photodiode diffusion area pattern, a fourth photodiode diffusion area pattern, a first image signal conversion circuit diffusion area pattern, and a second image signal conversion circuit diffusion area pattern.
  • the second photodiode diffusion area pattern is formed in a diagonal direction from the first photodiode diffusion area pattern.
  • the third photodiode diffusion area pattern is formed above the first photodiode diffusion area pattern beside the second photodiode diffusion area pattern.
  • the fourth photodiode diffusion area pattern is formed in a diagonal direction from the third photodiode diffusion area pattern above the second photodiode diffusion area pattern.
  • the first image signal conversion circuit diffusion area pattern is formed beside the first photodiode diffusion area pattern below the second photodiode diffusion area pattern.
  • the second image signal conversion circuit diffusion area pattern is formed beside the third photodiode diffusion area pattern below the fourth photodiode diffusion area pattern above the second photodiode diffusion area pattern.
  • a 4T-2S step & repeat unit cell according to the present invention is advantageous in that an aperture ratio can be improved in comparison with a conventional unit cell by alternately arranging image signal conversion circuits for converting image signals detected from each photodiode into electric signals in the unit of a line.
  • FIG. 1 is a circuit diagram for describing a process of forming a 4T-2S step & repeat unit cell by combining two image sensor circuits each having four transistors;
  • FIG. 2 is a circuit diagram illustrating a 4T-2S step & repeat unit cell according to the present invention;
  • FIG. 3 is a layout diagram illustrating arrangement of active diffusion areas defining a 4T-2S step & repeat unit cell according to an embodiment of the present invention;
  • FIG. 4 is a layout diagram for showing arrangement of the active diffusion areas of
  • FIG. 3 and gate layer patterns formed thereon;
  • FIG. 5 is a layout diagram illustrating active diffusion areas defining a 4T-2S step & repeat unit cell according to another embodiment of the present invention;
  • FIG. 6 is a layout diagram for showing arrangement of the active diffusion areas of
  • FIG. 5 and gate layer patterns formed thereon;
  • FIG. 7 is a layout diagram illustrating active diffusion areas defining a 4T-2S step & repeat unit cell according to another embodiment of the present invention;
  • FIG. 8 is a layout diagram for showing arrangement of the active diffusion areas of
  • FIG. 9 is a layout diagram illustrating active diffusion areas defining a 4T-2S step & repeat unit cell according to another embodiment of the present invention
  • FIG. 10 is a layout diagram for showing arrangement of the active diffusion areas of FIG. 9 and gate layer patterns formed thereon;
  • FIG. 11 is a layout diagram illustrating a 4T-2S step & repeat unit cell implemented on the active diffusion area patterns of FIG. 3;
  • FIG. 12 is a layout diagram illustrating a 4T-2S step & repeat unit cell implemented on the active diffusion area patterns of FIG. 5;
  • FIG. 13 is a layout diagram illustrating a 4T-2S step & repeat unit cell implemented on the active diffusion area patterns of FIG. 7. Best Mode for Carrying Out the Invention
  • a step & repeat unit cell is defined by combining four image sensor unit cells into a single unit, and the layout pattern of the defined unit cell is optimized. It is possible to readily implement an image sensor area by arranging the layout pattern of the defined unit cell in both of horizontal and vertical directions. Now, circuitry corresponding to the layout pattern will be described first to facilitate understanding of the layout pattern pertaining to the present invention.
  • FIG. 2 is a circuit diagram illustrating a 4T-2S step & repeat unit cell according to the present invention.
  • a 4T-2S step & repeat unit cell includes a first subordinate unit cell (i.e., an upper portion with respect to a dotted line) and a second subordinate unit cell (i.e., a lower portion with respect to a dotted line).
  • a reset transistor M 13 In the first subordinate unit cell, a reset transistor M 13, a conversion transistor M 14, and a selection transistor M 15 are shared by two image sensors. Photodiodes PD3 and PD 4 of each image sensor are connected to transmission transistors Mi l and M12.
  • a reset transistor M3, a conversion transistor M4, and a selection transistor M5 are shared by two image sensors. Also, photodiodes PDl and PD2 of each image sensor are connected to transmission transistors Ml and M2.
  • a 4T-2S step & repeat unit cell of FIG. 2 is defined by combining four image sensor unit cells.
  • FIG. 3 is a layout diagram illustrating active diffusion areas defining a 4T-2S step & repeat unit cell according to an embodiment of the present invention.
  • the active diffusion areas of the 4T-2S step & repeat unit cell include areas for four photodiodes PDl, PD2, PD3, and PD4 and areas for image signal conversion circuits RD 1 and RD2.
  • a second photodiode PD2 is implemented in a right diagonal direction from a first photodiode PDl
  • a third photodiode PD3 is implemented in a left-hand side of the second photodiode PD2 above the first photodiode PDl.
  • a fourth photodiode PD4 is implemented in a diagonal direction from the third photodiode PD3 above the second photodiode PD2.
  • a diffusion area pattern for a first image signal conversion circuit RDl is implemented in a right-hand side of the first photodiode PDl below the second photodiode PD2, and a diffusion area pattern for a second image signal conversion circuit RD2 is implemented in a left-hand side of the fourth photodiode PD4 above the third photodiode PD3.
  • Diffusion area patterns of the first photodiode PDl, the second photodiode PD2, and the first image signal conversion circuit RDl are connected to one another in a single pattern.
  • diffusion area patterns of the third photodiode PD3, the fourth photodiode PD4, and the second image signal conversion circuit RD2 are connected to one another in a single pattern.
  • FIG. 4 is a layout diagram for showing arrangement of the active diffusion areas of
  • FIG. 3 and gate layer patterns formed thereon.
  • an upper right corner of the first photodiode PDl is connected to a lower left corner of the second photodiode PD2 by extension.
  • a first transmission transistor Ml for transmitting charges detected from the first photodiode PDl and a second transmission transistor M2 for transmitting charges detected from the second photodiode PD2 are implemented on this extension area.
  • a first reset transistor M3, a first conversion transistor M4, and a first selection transistor M5 are implemented on the diffusion area pattern of the first image signal conversion circuit RDl.
  • An upper right corner of the third photodiode PD3 is connected to a lower left corner of the fourth photodiode PD4 by extension.
  • a third transmission transistor Mi l for transmitting charges detected from the third photodiode PD3 and a fourth transmission transistor M 12 for transmitting charges detected from the fourth photodiode PD4 are implemented on this extension area.
  • a second reset transistor M 13, a second conversion transistor M 14, and a second selection transistor M 15 are implemented on the diffusion area pattern RD2 of the second image signal conversion circuit.
  • FIG. 5 is a layout diagram illustrating active diffusion areas defining a 4T-2S step & repeat unit cell according to another embodiment of the present invention.
  • diffusion area patterns of the first and second image signal conversion circuits RDl and RD2 are separated from the diffusion area patterns of the corresponding photodiodes unlike those shown in FIG. 3. While the diffusion area patterns integrated in a single pattern of FIG. 3 are electrically connected, the diffusion area patterns of FIG. 4 are separated from one another. Therefore, they are connected in a subsequent wiring process. Specifically, contacts are formed on corresponding portions of two diffusion area patterns, and a metal line pattern is formed on the contacts, so that the two diffusion area patterns can be electrically connected to each other.
  • FIG. 6 is a layout diagram for showing arrangement of the active diffusion areas of
  • FIG. 5 and gate layer patterns formed thereon.
  • the arrangement of the diffusion area patterns and the gate layer formed thereon shown in FIG. 4 is similar to the diffusion area patterns and the gate layer formed thereon shown in FIG. 6 except for a fact that the diffusion area patterns of the first and second image signal conversion circuits RDl and RD2 are separated from the diffusion area patterns of the extension between corresponding photodiodes. Therefore, detailed description of FIG. 6 will be omitted.
  • FIG. 7 is a layout diagram illustrating active diffusion areas defining a 4T-2S step & repeat unit cell according to another embodiment of the present invention.
  • the arrangement of the active diffusion areas shown in FIG. 7 according to another embodiment is similar to that shown in FIG. 3 except for a fact that the diffusion area pattern of the second image signal conversion circuit RD2 connected to the extension between the upper right corner of the third photodiode PD3 and the lower left corner of the fourth photodiode PD4 is located on a right-hand side rather than a left-hand side.
  • FIG. 8 is a layout diagram for showing arrangement of the active diffusion areas of
  • an upper right corner of the first photodiode PDl is connected to a lower left corner of the second photodiode PD2 by extension.
  • a first transmission transistor Ml for transmitting charges detected from the first photodiode PDl and a second transmission transistor M2 for transmitting charges detected from the second photodiode PD2 are implemented on this extension area.
  • a first reset transistor M3, a first conversion transistor M4, and a first selection transistor M5 are implemented on the diffusion area pattern of the first image signal conversion circuit RDl.
  • FIG. 9 is a layout diagram illustrating active diffusion areas defining a 4T-2S step & repeat unit cell according to another embodiment of the present invention.
  • RDl and RD2 are separated from the diffusion area patterns of the corresponding pho- todiodes unlike those shown in FIG. 3. Since understanding of difference between embodiments shown in FIGS. 3 and 5 can be similarly applied to this arrangement, its description will be omitted.
  • FIG. 10 is a layout diagram for showing arrangement of the active diffusion areas of
  • FIG. 9 and gate layer patterns formed thereon.
  • the arrangement of the diffusion area patterns and the gate layer formed thereon shown in FIG. 8 is similar to the arrangement of the diffusion area patterns and the gate layer formed thereon shown in FIG. 10 except for a fact that the diffusion area patterns of the first and second image signal conversion circuits RDl and RD2 are separated from the diffusion area patterns of the extension between corresponding pho- todiodes as described above. Therefore, detailed description of FIG. 10 will be omitted.
  • FIG. 11 is a layout diagram illustrating a 4T-2S step & repeat unit cell implemented on the active diffusion area patterns of FIG. 3.
  • the first transmission transistor Ml is implemented on an upper right corner of the first photodiode PDl
  • the second transmission transistor M2 is implemented on a lower left corner of the second photodiode PD2.
  • the first reset transistor M3, the first conversion transistor M4, and the first selection transistor M5 are implanted on the diffusion area pattern of the first image signal conversion circuit RDl in this order from the left side to the right side. Electric signals corresponding to image signals detected from the first and second photodiodes PDl and PD2 are output from the right-side diffusion area of the first selection transistor M5.
  • the third transmission transistor Ml 1 is implemented on the upper right corner of the third photodiode PD3, and the fourth transmission transistor M 12 is implemented on the lower left corner of the fourth photodiode PD4.
  • the second reset transistor M 13, the second conversion transistor M 14, and the second selection transistor M15 are implemented on the diffusion area pattern of the second image signal conversion circuit RD2 in this order from the right side to the left side. Electric signals corresponding to image signals detected from the third and fourth photodiodes PD3 and PD4 are output from the left-side diffusion area of the second selection transistor M15.
  • FIG. 12 is a layout diagram illustrating a 4T-2S step & repeat unit cell implemented on the active diffusion area patterns of FIG. 5.
  • FIG. 13 is a layout diagram illustrating a 4T-2S step & repeat unit cell implemented on the active diffusion area patterns of FIG. 7.
  • FIGS. 12 and 13 The layout diagrams shown in FIGS. 12 and 13 would be readily understood by those skilled in the art by referring to the description of FIG. 7, and thus, their description will be omitted.
  • the image signal conversion circuit is implemented between the lines of the photodiodes in the 4T-2S step & repeat unit cell according to the present invention in order to improve an aperture ratio.
  • a single step & repeat unit cell is defined by combining four image sensor unit cells, and the layout pattern of the defined unit cell is optimized.

Landscapes

  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

L'invention concerne une cellule unitaire de répétition 4T-2S obtenue par combinaison de quatre cellules unitaires de capteur d'image comprenant chacune quatre transistors en une seule unité. Une cellule unitaire de répétition 4T-2S comprend un premier motif de région de diffusion de photodiode, un deuxième motif de région de diffusion de photodiode, un troisième motif de région de diffusion de photodiode, un quatrième motif de région de diffusion de photodiode, un premier motif de région de diffusion de circuit de conversion de signal d'image, et un deuxième motif de région de diffusion de circuit de conversion de signal d'image. Le deuxième motif de région de diffusion de photodiode est formé dans un sens diagonal à partir du premier motif de région de diffusion de photodiode. Le troisième motif de région de diffusion de photodiode est formé au-dessus du premier motif de région de diffusion de photodiode à côté du deuxième motif de région de diffusion de photodiode. Le quatrième motif de région de diffusion de photodiode est formé dans un sens diagonal à partir du troisième motif de région de diffusion de photodiode au-dessus du deuxième motif de région de diffusion de photodiode. Le premier motif de région de diffusion de circuit de conversion de signal d'image est formé à côté du premier motif de région de diffusion de photodiode au-dessous du deuxième motif de région de diffusion de photodiode. Le deuxième motif de région de diffusion de circuit de conversion de signal d'image est formé au-dessus du troisième motif de région de diffusion de photodiode à côté du quatrième motif de région de diffusion de photodiode.
PCT/KR2008/006337 2007-10-29 2008-10-28 Pixel d'unité de répétition 4t-2s Ceased WO2009057924A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020070108634A KR100853194B1 (ko) 2007-10-29 2007-10-29 4ｔ－2ｓ 스텝 ＆ 리피트 단위 셀
KR10-2007-0108634 2007-10-29

Publications (2)

Publication Number Publication Date
WO2009057924A2 true WO2009057924A2 (fr) 2009-05-07
WO2009057924A3 WO2009057924A3 (fr) 2009-07-02

Family

ID=39878264

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2008/006337 Ceased WO2009057924A2 (fr) 2007-10-29 2008-10-28 Pixel d'unité de répétition 4t-2s

Country Status (2)

Country Link
KR (1) KR100853194B1 (fr)
WO (1) WO2009057924A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102442444B1 (ko) * 2017-10-27 2022-09-14 에스케이하이닉스 주식회사 N-형 포토다이오드 및 p-형 포토다이오드를 가진 이미지 센서

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990084630A (ko) * 1998-05-08 1999-12-06 김영환 씨모스 이미지 센서 및 그 구동 방법
KR20020058454A (ko) * 2000-12-30 2002-07-12 박종섭 게이트 전극 하부에 접지와 연결되는 더미 전도막 패턴을구비하는 이미지 센서
KR101003246B1 (ko) * 2004-04-28 2010-12-21 크로스텍 캐피탈, 엘엘씨 Ｃｍｏｓ 이미지센서
KR100772892B1 (ko) * 2006-01-13 2007-11-05 삼성전자주식회사 플로팅 확산 영역의 커패시턴스를 제어할 수 있는 공유픽셀형 이미지 센서

Also Published As

Publication number Publication date
KR100853194B1 (ko) 2008-08-21
WO2009057924A3 (fr) 2009-07-02

Similar Documents

Publication Publication Date Title
JP7696028B2 (ja) 光検出装置
US10950639B2 (en) Image sensors
KR100835892B1 (ko) 칩 적층 이미지센서
JP4953299B2 (ja) 共有ピクセル型イメージセンサ
JP2024038309A (ja) 撮像素子
KR100858033B1 (ko) 4ｔ－4ｓ 스텝 ＆ 리피트 단위픽셀 및 상기 단위픽셀을구비하는 이미지센서
KR102060843B1 (ko) 고체 촬상 소자 및 전자 기기
US20160211299A1 (en) Image capturing device
JP5245572B2 (ja) 半導体装置及び携帯型電子機器
KR101503682B1 (ko) 공유 픽셀형 이미지 센서 및 그 제조 방법
KR102114343B1 (ko) 센싱 픽셀 및 이를 포함하는 이미지 센서
KR20150063365A (ko) Cmos 이미지센서 컬럼 공유 화소유닛 및 화소 어레이
KR20210099350A (ko) 이미지 센싱 장치
EP1049171B1 (fr) Mosaique d'imagerie a semi-conducteurs
WO2008075846A1 (fr) Cellule unitaire de répétition à partage quadruple comportant quatre transistors et capteur d'image à partage quadruple comportant quatre transistors
JP5471439B2 (ja) 半導体チップ及び半導体装置
WO2009057924A2 (fr) Pixel d'unité de répétition 4t-2s
CN215342600U (zh) 图像传感器
CN111146222A (zh) 一种基于多晶圆堆叠技术的多区块像元阵列
JP2009529801A (ja) Ｃｍｏｓイメージセンサの画素アレイ構造及び方法
JP2004153253A (ja) Ｃｍｏｓイメージセンサ
US20230236322A1 (en) Image sensor and detection system using same
CN115701715B (zh) 图像感测装置
KR20250045433A (ko) 이미지 센서의 픽셀
CN120980989A (zh) 图像传感器

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08843651

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: COMMUNICATION PURSUANT TO RULE 112(1) (EPO FORM 1205A DATED 25/08/2010)

122 Ep: pct application non-entry in european phase

Ref document number: 08843651

Country of ref document: EP

Kind code of ref document: A2