WO2009069621A1 - データ処理装置、及びデータ処理方法 - Google Patents

データ処理装置、及びデータ処理方法 Download PDF

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Publication number
WO2009069621A1
WO2009069621A1 PCT/JP2008/071388 JP2008071388W WO2009069621A1 WO 2009069621 A1 WO2009069621 A1 WO 2009069621A1 JP 2008071388 W JP2008071388 W JP 2008071388W WO 2009069621 A1 WO2009069621 A1 WO 2009069621A1
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WIPO (PCT)
Prior art keywords
data processing
code
processing device
ldpc
symbol
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/JP2008/071388
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English (en)
French (fr)
Inventor
Takashi Yokokawa
Makiko Yamamoto
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Sony Corp
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Sony Corp
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Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of WO2009069621A1 publication Critical patent/WO2009069621A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions

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  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)

Abstract

本発明は、バースト誤りや、イレージャ等の、LDPC符号の符号ビットのエラーに対する耐性を向上させることができるデータ処理装置、及びデータ処理方法に関する。 LDPC(Low Density Parity Check)符号の2ビット以上の符号ビットが１個のシンボルとされる場合において、カラムツイストインターリーバ２４は、検査行列の任意の１行にある1に対応する複数の符号ビットが、１個のシンボルにマッピングされないように、LDPC符号の符号ビットを並び替える並び替え処理を行う。本発明は、例えば、LDPC符号を送信する送信装置に適用できる。
PCT/JP2008/071388 2007-11-26 2008-11-26 データ処理装置、及びデータ処理方法 Ceased WO2009069621A1 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007-304690 2007-11-26
JP2007304690 2007-11-26
JP2008-027756 2008-02-07
JP2008027756 2008-02-07

Publications (1)

Publication Number Publication Date
WO2009069621A1 true WO2009069621A1 (ja) 2009-06-04

Family

ID=40678516

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/071388 Ceased WO2009069621A1 (ja) 2007-11-26 2008-11-26 データ処理装置、及びデータ処理方法

Country Status (2)

Country Link
TW (1) TW200939642A (ja)
WO (1) WO2009069621A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2690791A1 (en) * 2012-07-27 2014-01-29 Panasonic Corporation Component interleaving for rotated constellations with quasi-cylic LDPC codes
CN115995249A (zh) * 2023-03-24 2023-04-21 南京大学 一种基于dram的矩阵转置运算装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9952831B1 (en) 2017-02-16 2018-04-24 Google Llc Transposing in a matrix-vector processor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006254466A (ja) * 2005-03-11 2006-09-21 Samsung Electronics Co Ltd 低密度のパリティ検査符号を用いる通信システムにおけるチャンネルインタリービング／デインタリービング装置およびその制御方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006254466A (ja) * 2005-03-11 2006-09-21 Samsung Electronics Co Ltd 低密度のパリティ検査符号を用いる通信システムにおけるチャンネルインタリービング／デインタリービング装置およびその制御方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ROBERT D. MADDOCK ET AL.: "Reliability-Based Coded Modulation With Low-Density Parity-Check Codes", IEEE TRANSACTIONS ON COMMUNICATIONS, vol. 54, no. 3, March 2006 (2006-03-01), pages 403 - 406 *
STEPHANE Y. LE GOFF: "Signal Constellations for Bit-Interleaved Coded Modulation", IEEE TRANSACTIONS ON INFORMATION THEORY, vol. 49, no. 1, January 2003 (2003-01-01), pages 307 - 313 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2690791A1 (en) * 2012-07-27 2014-01-29 Panasonic Corporation Component interleaving for rotated constellations with quasi-cylic LDPC codes
CN115995249A (zh) * 2023-03-24 2023-04-21 南京大学 一种基于dram的矩阵转置运算装置

Also Published As

Publication number Publication date
TW200939642A (en) 2009-09-16

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