WO2009085363A2 - Circuit de désactivation de ci - Google Patents

Circuit de désactivation de ci Download PDF

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Publication number
WO2009085363A2
WO2009085363A2 PCT/US2008/078922 US2008078922W WO2009085363A2 WO 2009085363 A2 WO2009085363 A2 WO 2009085363A2 US 2008078922 W US2008078922 W US 2008078922W WO 2009085363 A2 WO2009085363 A2 WO 2009085363A2
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WO
WIPO (PCT)
Prior art keywords
secure
circuitry
disabling
response
clamping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2008/078922
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English (en)
Other versions
WO2009085363A3 (fr
Inventor
Lawrence T. Clark
Fionn Sheerin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Arizona State University ASU
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Arizona State University ASU
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Arizona State University ASU filed Critical Arizona State University ASU
Publication of WO2009085363A2 publication Critical patent/WO2009085363A2/fr
Publication of WO2009085363A3 publication Critical patent/WO2009085363A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/40—Arrangements for protection of devices protecting against tampering, e.g. unauthorised inspection or reverse engineering
    • H10W42/405—Arrangements for protection of devices protecting against tampering, e.g. unauthorised inspection or reverse engineering using active circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/60—Arrangements for protection of devices protecting against electrostatic charges or discharges, e.g. Faraday shields
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory

Definitions

  • ICs Secure Integrated Circuits
  • the IC needs to be able to detect intrusions, or attacks, and to appropriately respond to those detected intrusions. Accordingly, there is a need for a system and method for responding to detected intrusions on a secure IC by disabling the IC.
  • the present invention relates to a secure Integrated Circuit (IC) and more particularly relates to disabling at least one component of the secure IC in response to detecting an event such as an intrusion, or attack, on the secure IC.
  • a supply voltage (V DD ) node of the secure IC is clamped to, or effectively short circuited to, a reference voltage (Vss) node of the secure IC.
  • V DD supply voltage
  • Vss reference voltage
  • the disabling of the secure IC may be temporary or permanent.
  • the disabling of the secure IC is made permanent by setting a state of a nonvolatile memory element on the secure IC.
  • the nonvolatile memory element is a thin gate transistor, wherein a thin gate oxide of the transistor is blown such that the thin gate transistor operates as a fuse.
  • the secure IC includes intrusion detection circuitry and disabling circuitry. Upon detecting an intrusion upon the core circuitry, the intrusion detection circuitry sends a disable signal to the disabling circuitry. In response, the disabling circuitry clamps a supply voltage (V DD ) node of the secure IC to a reference voltage (V S s) node of the secure IC, thereby disabling at least one component of the secure IC.
  • the disabling circuitry includes fuse circuitry and clamping circuitry.
  • the fuse circuitry includes a thin gate transistor. Upon receiving the disable signal, the fuse circuitry applies a relatively high voltage (V DDH ) to a gate of the thin gate transistor, thereby blowing the thin gate transistor. In response, the clamping circuitry is activated to clamp, or effectively short circuit, the supply voltage (V DD ) node of the secure IC to the reference voltage (V S s) node of the secure IC.
  • the disabling circuitry includes electrostatic discharge (ESD) circuitry and fuse circuitry. The ESD circuitry provides conventional ESD protection for the secure IC.
  • the ESD circuitry provides a high-impedance path or open circuit between a supply voltage (V DD ) node of the secure IC and a reference voltage (Vss) node of the secure IC.
  • V DD supply voltage
  • Vss reference voltage
  • the ESD circuitry clamps the supply voltage (V DD ) node of the secure IC to the reference voltage (Vss) node of the secure IC.
  • the ESD circuitry is also activated in response to detecting an intrusion on the secure IC.
  • the secure IC By activating the ESD circuitry in response to detecting an intrusion on the secure IC, the secure IC is disabled by clamping the supply voltage (V DD ) node of the secure IC and the reference voltage (Vss) node of the secure IC.
  • Figure 1 illustrates a secure Integrated Circuit (IC) including disabling circuitry according to one embodiment of the present invention
  • Figure 2 is a more detailed illustration of the disabling circuitry of Figure 1 according to first embodiment of the present invention
  • Figures 3A and 3B illustrate a thin gate transistor of Figure 2 before and after a gate oxide is ruptured according to one embodiment of the present invention
  • Figure 4 illustrates one implementation of a resistor that may be utilized in the disabling circuitry of Figure 2 according to one embodiment of the present invention
  • Figure 5 illustrates an exemplary embodiment of a thick gate inverter included in the disabling circuitry of Figure 2;
  • FIGS 6 through 8 graphically illustrate the operation of the disabling circuitry of Figure 2 according to one embodiment of the present invention
  • Figure 9 is a more detailed illustration of the disabling circuitry of Figure 1 according to a second embodiment of the present invention.
  • Figure 10 is a more detailed illustration of the disabling circuitry of Figure 1 according to a third embodiment of the present invention
  • Figure 1 1 is a more detailed illustration of the disabling circuitry of Figure 1 according to a fourth embodiment of the present invention
  • Figure 12 illustrates a secure IC including disabling circuitry according to another embodiment of the present invention
  • Figure 13 is a more detailed illustration of the disabling circuitry of Figure 12 according to one embodiment of the present invention.
  • the present invention relates to a secure Integrated Circuit (IC) and more particularly relates to disabling the secure IC in response to detecting an intrusion, or attack, on the secure IC.
  • IC Integrated Circuit
  • FIG. 1 is a block diagram of a secure IC 10 including IC disabling circuitry 12 (hereinafter “disabling circuitry") according to one embodiment of the present invention.
  • the secure IC 10 may be any type of IC wherein security is desired.
  • the secure IC 10 may be utilized in military applications or commercial applications.
  • the secure IC 10 may be a secure Field Programmable Gate Array (FPGA) integrated circuit, a secure Read Only Memory (ROM) integrated circuit, a secure Erasable Programmable Read Only Memory (EPROM) integrated circuit such as a flash memory integrated circuit, an IC for controlling operation of a Smart Card, or the like.
  • the secure IC 10 includes core circuitry 14, intrusion detection and authentication circuitry 16, and a fuse block 18.
  • the secure IC 10 is a single integrated circuit die including the core circuitry 14, the intrusion detection and authentication circuitry 16, and the fuse block 18.
  • the secure integrated circuit 10 is a single integrated circuit package including the core circuitry 14, the intrusion detection and authentication circuitry 16, and the fuse block 18.
  • the secure integrated circuit 10 may be implemented as multiple die soldered together without the use of a package.
  • the core circuitry 14 may vary depending on the particular implementation of the secure IC 10.
  • the core circuitry 14 may be core circuitry of an FPGA, ROM, EPROM, or the like.
  • the intrusion detection and authentication circuitry 16 operates to provide authentication and to detect intrusions for the secure IC 10.
  • a Personal Identification Number (PIN) or other authentication password is provided to the secure IC 10.
  • PIN Personal Identification Number
  • the intrusion detection and authentication circuitry 16 compares the authentication password to a stored correct value. Upon receiving a predetermined number of incorrect authentication passwords, the intrusion detection and authentication circuitry 16 triggers a fuse to be blown in the fuse block 18.
  • the fuse block 18 is exemplary. Other types of non- volatile or, alternatively, volatile storage may be used. Further, the fuse block 18 or other type of non-volatile storage, or alternative volatile storage, may alternatively be implemented outside of the secure integrated circuit 10.
  • the intrusion detection and authentication circuitry 16 sends a disable signal to the disabling circuitry 12.
  • the disabling circuitry 12 disables the secure IC 10 by either permanently or temporarily clamping a supply voltage (V DD ) of the secure IC 10 to a reference voltage (V S s) of the secure IC 10.
  • the intrusion detection and authentication circuitry 16 is coupled to a supply voltage (V DD
  • the supply voltage (V DDIO ) may be a supply voltage used for input/output circuitry to systems implemented in processes that use supply voltages greater than the supply voltage (V DD )-
  • the supply voltage (V DD ) may be 1 .8 volts (V) and the supply voltage (V DDIO ) may be 3.3V or 5V.
  • a decoupling capacitor 22 provides charge storage to the intrusion detection and authentication circuitry 16 for some amount of time after the supply voltage (V DDI O) is removed. In this manner, the intrusion detection and authentication circuitry 16, or at least a desired subset thereof, may continue to operate after the supply voltage (V DDIO ) has been driven to ground.
  • the intrusion detection and authentication circuitry 16 may detect and respond to power attacks or attempts to remove power before the intrusion detection and authentication circuitry 16 can respond to an incorrect authentication attempt by blowing one of the fuses in the fuse block 18.
  • the fuses in the fuse block 18 may also be coupled to the supply voltage (V DDIO ) by the diode 20 by the optional connection shown in Figure 1 .
  • the secure IC 10 may have a number of independent voltage domains.
  • each power supply pin of the secure IC 10 may correspond to an independent voltage domain.
  • the disabling circuitry 12 may operate to disable only a subset of the independent voltage domains or all of the independent voltage domains.
  • FIG. 12 is a block diagram of the disabling circuitry 12 of Figure 1 according to one embodiment of the present invention.
  • the disabling circuitry 12 includes modified electrostatic discharge (ESD) circuitry 24 and fuse circuitry 26.
  • the modified ESD circuitry 24 includes RC timer circuitry 28 formed by a transistor 30, a resistor 32, and a capacitor-connected transistor 34 connected as shown.
  • the RC timer circuitry 28 operates such that a timing node (TIMING_NODE) of the RC timer circuitry 28 is at a logic level "0,” as will be appreciated by one of ordinary skill in the art upon reading this disclosure.
  • the RC timer circuitry 28 When an ESD event is not present, the RC timer circuitry 28 operates such that the timing node (TIMING_NODE) is at a logic level "1."
  • the output of the RC timer circuitry 28 at the timing node (TIMING_NODE) is inverted by an inverter 36 and provided to a first input (NORA) of a NOR gate 38.
  • an output of the NOR gate 38 is connected to an input of clamping circuitry 40 via an inverter chain 42.
  • the clamping circuitry 40 is a P-type Metal Oxide Semiconductor (PMOS) transistor 44.
  • PMOS P-type Metal Oxide Semiconductor
  • the PMOS transistor 44 When the PMOS transistor 44 is in an off state (i.e., when a logic level "1 " is provided to a gate of the PMOS transistor 44), the PMOS transistor 44 provides a high impedance path or open circuit between the supply voltage (V DD ) and the reference voltage (Vss), or more specifically a high impedance path or open circuit between corresponding supply voltage (V DD ) and reference voltage (Vss) nodes.
  • V DD supply voltage
  • Vss reference voltage
  • the PMOS transistor 44 When the PMOS transistor 44 is in an on state (i.e., when a logic level "0" is provided to the gate of the PMOS transistor), the PMOS transistor 44 provides a low impedance path or short circuit between the supply voltage (V DD ) and the reference voltage (Vss), or more specifically a low impedance path or short circuit between corresponding supply voltage (V DD ) and reference voltage (Vss) nodes.
  • the inverter chain 42 connecting the output of the NOR gate 38 and the input of the clamping circuitry 40 includes an even number of inverters 46-1 through 46-N.
  • the input provided to the clamping circuitry 40 (i.e., the input provided to the gate of the PMOS transistor 44) is at a logic level "0" when the output of the NOR gate 38 is at a logic level "0,” and at a logic level “1 " when the output of the NOR gate 38 is at a logic level “1 .”
  • the PMOS transistor 44 is a relatively large transistor.
  • the inverter chain 42 operates to "buffer up" the output of the NOR gate 38 such that the output of the NOR gate 38 can drive the PMOS transistor 44.
  • the timing node (TIMING_NODE) In normal operation when no ESD event is present, the timing node (TIMING_NODE) is at a logic level "1.” As a result, the output of the NOR gate 38 and thus gate of the PMOS transistor 44 is at a logic level "1.” Since the gate of the PMOS transistor 44 is at a logic level “1 ,” the PMOS transistor 44 is in an off state, thereby presenting a high impedance path or open circuit between the supply voltage (V DD ) and the reference voltage (Vss)- In contrast, during an ESD event, the timing node (TIMING_NODE) is at a logic level "0.” As a result, the output of the NOR gate 38 and thus the gate of the PMOS transistor 44 is at a logic level "0.” Since the gate of the PMOS transistor 44 is at a logic level "0,” the PMOS transistor 44 is in an on state, thereby effectively shorting the supply voltage (V DD ) to the reference voltage (Vss)- Once the E
  • an output of the fuse circuitry 26 is applied to a second input (NORB) of the NOR gate 38.
  • the output of the fuse circuitry 26 is normally at a logic level "0" such that, unless there is an ESD event, the PMOS transistor 44 is in an off state.
  • the output of the fuse circuitry 26 is set to a logic level "1 " such that the PMOS transistor 44 is set to an on state to clamp the supply voltage (V DD ) to the reference voltage (V S s) > thereby disabling the secure IC 10.
  • the fuse circuitry 26 includes a thick gate transistor 48, a thin gate transistor 50, a resistor 52, and a thick gate inverter 54.
  • a "thick gate” device is a device formed by a transistor or transistor(s) having a gate oxide thickness that is sufficient to withstand the application of a supply voltage (V DDH ), which is higher than some other supply voltage (V DD ) used in the circuit. For example, if V DD is 1.8V, then V DDH may be 3.3V or 5V. However, the present invention is not limited thereto.
  • a "thin gate” transistor is a transistor having a gate oxide thickness that is not sufficient, or is most likely not sufficient, to withstand the application of the higher supply voltage potential (V DDH ), which again is higher than the supply voltage (V DD )- AS discussed below, the supply voltage (V DDH ) is utilized to blow, or rupture, a gate oxide of the thin gate transistor 50 when the secure IC 10 is to be disabled.
  • V DDH supply voltage
  • the thin gate transistor 50 operates as a form of non-volatile storage, or memory.
  • the thick gate transistor 48 is controlled by a disable signal (DISABLE) from the intrusion detection and authentication circuitry 16 ( Figure 1 ).
  • a storage node (STORAGE_NODE) of the fuse circuitry 26 is pulled to a logic level “1 " by the resistor 52.
  • the logic level "1 " at the storage node (STORAG E_NODE) is inverted by the thick gate inverter 54 to provide a logic level "0" to the NOR gate 38.
  • the disable signal (DISABLE) is set to a logic level "0,” thereby setting the thick gate transistor 48 to an on state.
  • the supply voltage (V DDH ) is applied to a gate of the thin gate transistor 50.
  • the supply voltage (V DDH ) is greater than a break down voltage of a gate oxide of the thin gate transistor 50.
  • the supply voltage (V DD ) is 1.8V
  • the supply voltage (V DDH ) is either 3.3V or 5V
  • a thickness of a gate oxide of the thin gate transistor 50 is less than 35 Angstroms (A).
  • the present invention is not limited thereto.
  • the thickness of the gate oxide of the thin gate transistor 50 and the voltage level of the supply voltage (V DDH ) may vary depending on the voltage level used for the supply voltage (V DD )-
  • the storage node (STORAG E_NODE) is pulled to a logic level "0."
  • a ratio of the resistance of the resistor 52 and a resistance of the blown thin gate transistor 50 is such that the storage node (STORAG E_NODE) is at a logic level "0" when the thin gate transistor 50 is blown.
  • the logic level "0" at the storage node (STORAGE_NODE) is inverted by the thick gate inverter 54 to provide a logic level "1 " to the NOR gate 38.
  • the PMOS transistor 44 is set to the on state such that a low impedance path or short circuit is presented between the supply voltage (V DD ) and the reference voltage (V S s), thereby disabling the secure IC 10.
  • Figures 3A and 3B illustrate the thin gate transistor 50 before and after the thin gate oxide has been blown, or ruptured, according to an exemplary embodiment of the present invention. More specifically, Figure 3A illustrates the thin gate transistor 50 before the supply voltage (V DDH ) has been applied to the gate of the thin gate transistor 50. A thin gate oxide layer 56 creates a high impedance path between a polysilion gate 58 and a source 60, a drain 62, and a body 64 of the thin gate transistor 50. As illustrated in Figure 3B, once the supply voltage (V DDH ) is applied to the gate of the thin gate transistor 50, the thin gate oxide layer 56 is ruptured, or blown.
  • V DDH supply voltage
  • FIG. 4 illustrates an exemplary implementation of the resistor 52 of Figure 2.
  • the resistor 52 is implemented as a thick gate PMOS transistor 66 connected as shown.
  • Figure 5 illustrates an exemplary embodiment of the thick gate inverter 54 of Figure 2.
  • the thick gate inverter 54 is implemented as a thick gate PMOS transistor 68 and a thick gate NMOS transistor 70 connected as shown in Figure 5.
  • FIG. 8 graphically illustrates the operation of the disabling circuitry 12 of Figure 2 when the secure IC 10 is disabled.
  • the clamping circuitry 40 is permanently activated such that the supply voltage (V DD ) is clamped to the reference voltage (V S s)- As a result, the supply voltage (V DD ) is prevented from rising to a voltage sufficient for normal operation of the secure IC 10.
  • V MIN is the minimum V DD required for proper circuit operation.
  • Figure 9 illustrates the disabling circuitry 12 of Figure 1 according to another embodiment of the present invention that is substantially the same as the embodiment of Figure 2.
  • the clamping circuitry 40 is formed by an N-type Metal Oxide Semiconductor (NMOS) transistor 44', rather than the PMOS transistor 44 ( Figure 2). Since the NMOS transistor 44' is on when the input to the gate of the NMOS transistor 44' is at a logic level "1 " and off when the input to the gate of the NMOS transistor 44' is at a logic level "0," the inverter chain 42 includes an odd number of inverters 46-1 through 46-N.
  • NMOS N-type Metal Oxide Semiconductor
  • Figure 10 illustrates the disabling circuitry 12 of Figure 1 according to another embodiment of the present invention. This embodiment is substantially the same as that in Figure 2 without the RC timer circuitry 28. More specifically, in this embodiment, the disabling circuitry 12 includes the fuse circuitry 26, wherein the output of the fuse circuitry 26 drives clamping circuitry 72 via an inverter chain 74. The clamping circuitry 72 is formed by a PMOS transistor 76 connected as shown.
  • the clamping circuitry 72 is formed by an NMOS transistor.
  • the inverter chain 74 includes a number of inverters 78-1 through 78-N. Since the clamping circuitry 72 is implemented as a PMOS transistor 76, there is an odd number of inverters 78-1 through 78-N in the inverter chain 74.
  • the storage node (STORAG E_NODE) is at a logic level "1.”
  • the output of the thick gate inverter 54 is at a logic level "0,” and the output of the inverter chain 74 is at a logic level “1.” Therefore, the PMOS transistor 76 is off such that a high impedance or open circuit is presented between the supply voltage (V DD ) and the reference voltage (Vss)-
  • the storage node (STORAG E_NODE) is at a logic level "0.”
  • the output of the thick gate inverter 54 is at a logic level "1 ”
  • the output of the inverter chain 74 is at a logic level "0.” Therefore, the PMOS transistor 76 is on such that a low impedance or short circuit is presented between the supply voltage (V DD ) and the reference voltage (Vss).
  • the outputs of the fuse circuitries 26-1 through 26-M are input to a NOR gate 80.
  • the output of the NOR gate 80 then drives the clamping circuitry 72 via the inverter chain 74.
  • the clamping circuitry 72 is implemented as a PMOS transistor 76, there is an even number of inverters 78-1 through 78-N in the inverter chain 74.
  • the multiple fuse circuitries 26-1 through 26-M in the embodiment of the disabling circuitry 12 of Figure 1 1 may be used in the same manner as in the embodiments of the disabling circuitry 12 of Figures 2 and 9.
  • the outputs of the multiple fuse circuitries 26-1 through 26-M may be input to the NOR gate 38 of Figure 2 or Figure 9.
  • FIG. 12 illustrates the secure IC 10 according to another embodiment of the present invention.
  • the secure IC 10 also includes IC disabling circuitry 82 (hereinafter “disabling circuitry") coupled to the supply voltage (V DDI O)-
  • the secure IC 10 also includes the disabling circuitry 12 connected to the supply voltage (V DD )-
  • the present invention is not limited thereto.
  • the secure IC 10 may include multiple voltage domains.
  • the secure IC 10 may include multiple voltage domains for the intrusion detection and authentication circuitry 16.
  • the disabling circuitry 82 may be associated with one or more of these voltage domains such that all of the functionality of the intrusion detection and authentication circuitry 16 is disabled by the disabling circuitry 82 or, alternatively, such that some of the functionality of the intrusion detection and authentication circuitry 16 is disabled by the disabling circuitry 82 while other functionality of the intrusion detection and authentication circuitry 16 is not disabled by the disabling circuitry 82.
  • Figure 13 illustrates the disabling circuitry 82 of Figure 12 according to one embodiment of the present invention. This embodiment of the disabling circuitry 82 is substantially the same as the embodiment of the disabling circuitry 12 illustrated in Figure 2.
  • the disabling circuitry 82 includes modified ESD circuitry 84 and fuse circuitry 86.
  • the modified ESD circuitry 84 includes RC timer circuitry 88 formed by a thick gate transistor 90, a resistor 92, and a capacitor-connected thick gate transistor 94 connected as shown.
  • the RC timer circuitry 88 operates such that a timing node (TIMING_NODE) of the RC timer circuitry 88 is at a logic level "0," as will be appreciated by one of ordinary skill in the art upon reading this disclosure.
  • the RC timer circuitry 88 When an ESD event is not present, the RC timer circuitry 88 operates such that the timing node (TIMING_NODE) is at a logic level "1."
  • the output of the RC timer circuitry 88 at the timing node (TIMING_NODE) is inverted by an inverter 96 and provided to a first input (NORA) of a NOR gate 98.
  • the NOR gate 98 is a thick gate device.
  • An output of the NOR gate 98 is connected to an input of clamping circuitry 100 via an inverter chain 102.
  • the clamping circuitry 100 is implemented as a thick gate PMOS transistor 104.
  • the input provided to the clamping circuitry 100 (i.e., the input provided to the gate of the PMOS transistor 104) is at a logic level "0" when the output of the NOR gate 98 is at a logic level “0” and at a logic level “1 " when the output of the NOR gate 98 is at a logic level "1.”
  • the PMOS transistor 104 is a relatively large transistor.
  • the inverter chain 102 operates to "buffer up" the output of the NOR gate 98 such that the output of the NOR gate 98 can drive the PMOS transistor 104.
  • the timing node (TIMING_NODE) In normal operation when no ESD event is present, the timing node (TIMING_NODE) is at a logic level "1.” As a result, the output of the NOR gate 98 and thus gate of the PMOS transistor 104 is at a logic level "1 .” Since the gate of the PMOS transistor 104 is at a logic level “1 ,” the PMOS transistor 104 is in an off state, thereby presenting a high impedance path or open circuit between the supply voltage (V DD ) and the reference voltage (V S s)- In contrast, during an ESD event, the timing node (TIMING_NODE) is at a logic level "0.” As a result, the output of the NOR gate 98 and thus the gate of the PMOS transistor 104 is at a logic level "0.” Since the gate of the PMOS transistor 104 is at a logic level "0,” the PMOS transistor 104 is in an on state, thereby effectively shorting the supply voltage (V DD ) to the reference
  • the thick gate transistor 108 is controlled by a disable signal (DISABLE) from the intrusion detection and authentication circuitry 16 ( Figure 12). Initially, a storage node (STORAGE_NODE) of the fuse circuitry 86 is pulled to a logic level “1 " by the resistor 1 12. As such, the logic level "1 " at the storage node (STORAG E_NODE) is inverted by the thick gate inverter 1 14 to provide a logic level "0.” The output of the thick gate inverter 1 14 is provided to the NOR gate 98 via a level-shifter 1 16.
  • the level-shifter 1 16 includes thick gate transistors 1 18, 120, 122, and 124 and an inverter 126 connected as shown and operates to shift a logic level of the output of the thick gate inverter 1 14 from V DD logic levels to V DDIO logic levels. Because the output of the NOR gate 98, and thus the output of the level-shifter 1 16, is at a logic level "0" at this point, the PMOS transistor 44 is in an off state unless there is an ESD event. [0047] When an attack or intrusion is detected, the disable signal
  • a supply voltage (V DDH ) which is substantially higher than the supply voltage (V DD ), is applied to a gate of the thin gate transistor 1 10. More specifically, the supply voltage (V DDH ) is greater than a break down voltage of a gate oxide of the thin gate transistor 1 10.
  • the supply voltage (V DD ) is 1.8V
  • the supply voltage (V DDH ) is either 3.3V or 5V
  • a thickness of a gate oxide of the thin gate transistor 1 10 is less than 35 Angstroms (A).
  • the present invention is not limited thereto.
  • the PMOS transistor 104 is set to the on state such that a low impedance path or short circuit is presented between the supply voltage (V DD ) and the reference voltage (V S s), thereby disabling the secure IC 10.
  • the clamping circuitry 100 may alternatively be implemented as an NMOS transistor.
  • the disabling circuitry 82 may not include the RC timer circuitry 88 in a manner similar to the embodiment of the disabling circuitry 12 illustrated in Figure 10.
  • the secure IC 10 may be permanently or temporarily disabled after a predefined amount of time has expired since a triggering event occurred.
  • the triggering event may be, for example, power-up of the secure IC 10.
  • the present invention is not limited thereto.
  • the discussion above focuses on blowing the thin gate transistor 50/1 10 by applying the higher supply voltage (V DDH ) to the gate of the thin gate transistor 50/1 10, the present invention is not limited thereto.
  • the normal supply voltage (V DD ) may be applied to the gate of the thin gate transistor 50/1 10.
  • the reference voltage (V S s) applied to the source and drain of the thin gate transistor 50/1 10 may be pulled to a lower voltage.
  • the reference voltage (Vss) normally applied to the source and drain of the thin gate transistor 50/1 10 is ground
  • the reference voltage (Vss) applied to the source and drain of the thin gate transistor 50/1 10 may be pulled to a negative voltage that is sufficient to blow or rupture the thin gate oxide of the thin gate transistor 50/1 10.

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Abstract

L'invention concerne des systèmes et des procédés pour désactiver un circuit intégré (CI) sécurisé. En général, en réponse à la détection d'un événement tel qu'une intrusion sur le CI sécurisé, un nœud de tension d'alimentation (VDD) du CI sécurisé est connecté ou réellement court-circuité à un nœud de tension de référence (Vss) du CI sécurisé. La désactivation du CI sécurisé peut être temporaire ou permanente. Dans un mode de réalisation, la désactivation du CI sécurisé est rendue permanente en fixant un état d'un élément de mémoire non volatile sur le CI sécurisé. Dans un mode de réalisation, l'élément de mémoire non volatile est un transistor à porte mince dans lequel un oxyde de porte mince du transistor à porte mince est gonflé de telle sorte que le transistor à porte mince fait office de fusible.
PCT/US2008/078922 2007-10-05 2008-10-06 Circuit de désactivation de ci Ceased WO2009085363A2 (fr)

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US97799207P 2007-10-05 2007-10-05
US60/977,992 2007-10-05

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WO2009085363A2 true WO2009085363A2 (fr) 2009-07-09
WO2009085363A3 WO2009085363A3 (fr) 2009-09-03

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US10579536B2 (en) 2016-08-09 2020-03-03 Arizona Board Of Regents On Behalf Of Arizona State University Multi-mode radiation hardened multi-core microprocessors
EP4509845A1 (fr) * 2023-08-13 2025-02-19 Nxp B.V. Dispositif semi-conducteur ayant des capteurs d'interférence électromagnétique (emi) et circuit de détection pour détecter des attaques par interférences électromagnétiques
US12333229B2 (en) 2021-11-11 2025-06-17 International Business Machines Corporation Logic circuit locking with self-destruct

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US10579536B2 (en) 2016-08-09 2020-03-03 Arizona Board Of Regents On Behalf Of Arizona State University Multi-mode radiation hardened multi-core microprocessors
US12333229B2 (en) 2021-11-11 2025-06-17 International Business Machines Corporation Logic circuit locking with self-destruct
EP4509845A1 (fr) * 2023-08-13 2025-02-19 Nxp B.V. Dispositif semi-conducteur ayant des capteurs d'interférence électromagnétique (emi) et circuit de détection pour détecter des attaques par interférences électromagnétiques

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