WO2009103723A1 - Procédé de codage de canaux, procédé et appareil de décodage de canaux - Google Patents

Procédé de codage de canaux, procédé et appareil de décodage de canaux Download PDF

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Publication number
WO2009103723A1
WO2009103723A1 PCT/EP2009/051896 EP2009051896W WO2009103723A1 WO 2009103723 A1 WO2009103723 A1 WO 2009103723A1 EP 2009051896 W EP2009051896 W EP 2009051896W WO 2009103723 A1 WO2009103723 A1 WO 2009103723A1
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Prior art keywords
code
sequence
channel
data
runlength
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PCT/EP2009/051896
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English (en)
Inventor
Oliver Theis
Xiao-ming CHEN
Friedrich Timmermann
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Thomson Licensing SAS
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Thomson Licensing SAS
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Priority claimed from EP08101915A external-priority patent/EP2093884A1/fr
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits
    • H03M5/02—Conversion to or from representation by pulses
    • H03M5/04—Conversion to or from representation by pulses the pulses having two levels
    • H03M5/14—Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
    • H03M5/145—Conversion to or from block codes or representations thereof

Definitions

  • the present invention relates to data detection and channel encoding and decoding for partial response channels, for example to channel encoding and decoding digital data under a run- length-limited code with a Repeated Minimum Transition Runlength constraint .
  • the code is of code rate 2/3, signifying that for every 2 bits of payload, 3 code bits are generated.
  • a decoder structured as a Finite State Machine or FSM, and having 21 states and 79 state transitions also called “branches" has been described in: MIYAUCHI et al Soft-Output Decoding of 17 Parity Preserve/Prohibit Repeated Minimum Transition Runlength (PP) Code. Japanese Journal of Applied Physics. 2004, VoI 43 No 7B, pages 4882-4883.
  • Finite state machine decoders for binary data receive code bits in groups or tuples of a first length, and produce therefrom data bits in groups or tuples of a second length smaller than the first length.
  • code tuples have a length of 3
  • data tuples have a length of 2.
  • the Miyauchi decoder can be seen to have the disadvantage of having a large number of states and state transitions corresponding to a complicated structure and a big implementation effort.
  • US 4337458 A describes a (1,7) RLL channel code and a pertaining FSM decoder having a markedly smaller number of 6 states and 24 state transitions.
  • this code does not obey any RMTR- limitation.
  • the decoder of US 4337458 A is not usable on RMTR-limitation obeying codes .
  • European Patent Application EP 1 988 636 Al which was unpublished at the priority date of this application, describes a channel encoding method and apparatus, where a known (d, kl) RLL encoding is combined with a separate postprocessing which achieves compliance with a RMTR constraint.
  • the postprocessing does so by substituting instances of a predefined forbidden sequence, which would violate the RMTR constraint, by individual replacement sequences containing a runlength outside the internal upper runlength limit kl but within an upper runlength limit k>kl .
  • the individual replacement sequences are selected from a set of two predefined replacement sequences.
  • the encoding method of EP 1 988 636 Al can be seen to have the drawback, that the bitstreams generated from that method are such, that for decoding any code tuple therefrom, the next two code tuples have also to be known.
  • decoding the code bit sequences produced by the method of EP 1 988 636 Al has a delay of two code tuples, because some code bit sequences are not decodable with a lookahead of only one code tuple.
  • the maximum lookahead depth needed for decoding data that have been coded according to EP 1 988 636 Al is two code tuples . This can be seen as a drawback of a more complicated decoder structure and implementation effort.
  • a so-called PR or partial response equalizer which shapes the inter-symbol-interference in such a way that the physical channel in series with the equalizer together behave like the so-called PR target.
  • the PR target is an FIR filter that models the storage channel.
  • data detection is then carried out e.g. by means of a Viterbi detector which has a trellis structure matched to the PR target. In the Viterbi trellis, the minimum run-length constraint of an assumedly underlying RLL code is taken into account. After Viterbi data detection, RLL decoding is performed.
  • Another known read channel structure interprets the effects of the processing steps RLL encoding, non-return-to-zero precoding, and PR channel as one single finite state machine (FSM) , and uses this state machine in a trellis decoder. This amounts to jointly performing data detection and RLL decoding. Obviously, the latter approach is the optimal solution, but it typically is of a higher complexity than the former approach.
  • FSM finite state machine
  • digital data are channel decoded by steps of, when a current state and a received code triplet are as listed in one of the lines of the Decoding Table (code according to this invention) , outputting a data duplet and transiting to a next state as listed in that line of the Decoding Table.
  • an apparatus for channel decoding digital data has 9 states and 30 state transitions and is equipped and configured to perform a decoding method according to the invention.
  • the apparatus allows to decode data that have been coded using an RMTR-limitation-obeying code.
  • this invention also provides a Finite State Machine which enables that, on data encoded with the code of this invention, simultaneous data detection and RLL decoding is performed.
  • the RLL encoder, the NRZI- mapper, and the PR channel of a storage channel are all together regarded as a single equivalent RLL-NRZI-PR Finite State Machine, which may be obtained by extending an encoder/decoder FSM of the RLL code.
  • a low-complexity RLL-NRZI-PR FSM is disclosed for the (1,9) -RLL code of the invention. In this, low complexity refers to the number of states and branches in the corresponding trellis representation.
  • the disclosed combined FSM makes it possible that detectors based on Viterbi, Max-Log-MAP, or SOVA algorithms are used.
  • Fig. 1 shows the state diagram of a Finite State Machine decoder according to the invention
  • Fig. 2 shows the state diagram of a Finite State Machine decoder for a known channel code.
  • Fig. 3 shows the system model in the presence of an RLL encoder .
  • RLL channel codes convert any sequence of arbitrary payload words into a sequence of channel words that has at least a minimum number d and at most a maximum number k of "0" valued bits between consecutive "1" valued bits; in a shorthand notation, such codes are also known as " (d,k) codes", accordingly.
  • a transcoding or precoding step takes place, where the sequence of channel words from the first step is converted to an output signal or output sequence where each of the "l”s in the sequence of channel words causes a change in the output signal.
  • RMTR constrained RLL channel codes are used in recent high-density optical storage media, like blue laser optical discs. Same as the lower runlength limitation itself, the RMTR constraint aims at reducing the high frequency portions of the channel signal.
  • the Running Digital Sum or RDS is used.
  • the RDS corresponds to the time integral or sum taken from some start time tO up to a current time t.
  • the RDS is derived before the NRZI precoder, i.e. in the domain of the dk-encoded data.
  • ECC Error Correcting Coding
  • Incoming data to be stored are being ECC encoded prior to being channel encoded; and correspondingly, the read back signal from the storage medium is channel decoded and then ECC decoded, in sequence .
  • so-called "soft input” algorithms like those known in the art as “BCJR”, “Max-Log-MAP” or “SOVA” are known to be particularly powerful, but they require a reliability or confidence information about the channel decoded symbols entering them.
  • An important property of channel codes is whether or not they are decodable with a Finite State Machine FSM; also termed the code's "FSM decodability" .
  • FSM decodable channel code is a prerequisite for using soft output channel decoding methods, which in turn provide the sought reliability information for subsequent soft decision ECC decoding, or for a soft decision joint channel and ECC decoding.
  • these decoding methods which are trellis based, the state transition structure of the decoding FSM is used as a trellis.
  • an internal state of the decoder takes into account a current tuple of code bits, also termed a current code symbol, together with some more, subsequent code bits.
  • the number of code bits that are needed in addition to the code bits of the current code symbol is also termed the lookahead depth of the FSM decoder.
  • a channel code that is FSM decodable with a lookahead depth of 3 code bits means that, for determining the current state of the decoder, the code bits of the current code symbol together with 3 more, subsequent code bits from the code bit sequence are needed.
  • Fig. 1 shows the state diagram of a Finite State Machine decoder according to the invention. It can best be understood by comparing it with a counterpart of a known code.
  • Fig. 2 shows the state diagram of a Finite State Machine decoder for the known (1,7) RLL channel code of US 4337458 A.
  • the code is described by its encoding rule, namely by a basic coding table and a substitution coding table. Both tables describe the transformation of certain data words - in this case data duplets comprising two bits - into code words - in this case code triplets comprising three bits.
  • code triplets starting with a "1" as well as code triplets ending with a "1" both exist.
  • Fig. 2 The state diagram of Fig. 2 is presented in a modified Mealy automaton style.
  • a decoder output, i.e. a recognised data duplet, is associated to every state transition and is accordingly written at or near each arrow.
  • a decoder input i.e. a code triplet, would also be associated to every state transition and ascribed to the arrows. But the FSM decoder of Fig.
  • FIG. 2 has the special property that, for each specific state, all state transitions ending in that state relate to the same decoder input. This enables, that a simplified notion is used in Fig. 2, where the decoder input is ascribed to the states instead of to the state transitions.
  • the diagram of Fig. 2 illustrates the decoding of any regular sequence of code triplets: A path as dictated by the code triplets in received order is being traversed in the diagram, and the output duplets of the branches thus traversed are being output sequentially.
  • the decoding as represented by the state diagram of Fig. 2 is equivalently described by the following decoding table, which lists, in its 24 table line entries, 24 combinations of a current state, the received code triplet, the next state, and the decoded data duplet. Each of these combinations represents one branch in the state diagram. In the decoding table the combinations are grouped and ordered by their current state and ordered by their code triplet.
  • Table 1 Decoding Table (prior art code)
  • channel encoding comprises runlength encoding user data into an interim bitstream, and subsequently searching and replacing RMTR patterns in the interim bitstream.
  • the overall result of runlength encoding and replacing amounts to a modified channel code which does obey an RMTR limitation.
  • the interim bitstream is sequentially scanned for occurrences of a code bit sequence "1010101010” or its inverse, which constitutes a sixfold RMTR, and all found occurrences are replaced by a replacement sequence that has the same length as the RMTR pattern being replaced.
  • the second case is given when a code triplet of "XXO", i.e. a code triplet that ends in a "0", precedes the sixfold RMTR sequence that results from the data duplets "11 00 ".
  • XXO code triplet that ends in a "0"
  • Such a code triplet results when the basic coding table is being applied to data duplets "01" or "11"; it also results as the second code triplet when the substitution code table is being applied to any of the data duplet pairs contained therein.
  • the notion of the data duplet being indicated as "??”, together with the code triplet being indicated as "XXO" shall symbolise these cases .
  • both replacement sequences can be decoded with a lookahead of 3 code bits, so that selectively using either the fifth or the sixth replacement sequence allows to control the DC content of the code bit sequence. That the fifth and sixth replacement sequence have a different influence on the DC content can most easily be illustrated if one keeps in mind the NRZI precoding which is the next processing step performed on these bit sequences. Specifically, every "1" in the replacement output causes the polarity of the NRZI output to toggle.
  • Fig. 1 shows the state diagram of a Finite State Machine decoder according to the invention, shown in the same style as used in Fig. 2.
  • three additional states S7, S8, S9 exist, along with a total of 30 branches.
  • Decoding the above mentioned first replacement sequence amounts to transiting the state sequence S4, Sl, S7, S9, S3, S6 in that order.
  • Decoding the above mentioned fourth replacement sequence amounts to transiting the state sequence S6, S6, S5, S2, S8, S6 in that order.
  • the decoding amounts to transiting the state sequence S2, S5, S2, S8, S6, S3 in that order.
  • the decoding amounts to transiting the state sequence S5, S5, S2, S8, S6, S3 in that order.
  • the decoding amounts to transiting the state sequence S2, S3, Sl, S7, S9, S3 in that order.
  • the decoding amounts to transiting the state sequence S5, S3, Sl, S7, S9, S3 in that order.
  • a channel encoding method which comprises dk-encoding and NRZI precoding, the output of which obeys a repeated minimum transition runlength constraint and is FSM decodable with a given lookahead depth. Occurrences of RMTR violating critical bit sequences are replaced by same length replacement sequences containing extended zero runs; and the FSM decodability with the given lookahead depth is achieved by using only those replacement sequences that are decodable with the given lookahead depth.
  • a pertaining FSM channel decoding method and channel decoding apparatus are disclosed.
  • RLL code is FSM-decodable, i.e., the decoding can be accomplished by means of a finite-state machine.
  • s [n] denotes states of the FSM
  • u[n] denotes infowords
  • c[n] denotes codewords.
  • Table 2 illustrates state transitions in the decoder FSM. Except for using the new notation and employing an encoding point of view, it corresponds to the "Decoding Table (code according to this invention) " given above.
  • Fig. 1 shows the system model for a typical storage system in the presence of an RLL encoder.
  • xl[n] x[3n]
  • x2 [n] x [3n+l ]
  • x3 [n] x [3n+2] .
  • An important aspect of this is, that each channel output depends on L+l data symbols after NRZI.
  • the derivation of the FSM for the RLL-NRZI-PR channel is accomplished by extending the RLL decoder FSM in Table 2. Because Table 2 only provides data symbols a[n] before NRZI, a single extra data symbol after NRZI is necessary as a phase reference. Therefore, states in the RLL-NRZI-PR FSM are defined as
  • Data symbols x[3n], x[3n+l], and x[3n+2] can be determined from the state transitions s[n-l]-> s[n] of Table 2, if the phase reference x[3n-l] is available. For a specific state s [n] in Table 2, the upcoming RLL codebits are the same, which can be exploited to obtain data symbols x[3(n+l)], x[3(n+l)+l], and x[3(n+l)+2] .
  • Table 3 State transition table for the (1, 9) -RLL-NRZI-PR FSM
  • Table 4 shows the complete state transition table for the RLL-NRZI-PR FSM, including the PR channel outputs.
  • the RLL-NRZI-PR FSM takes as inputs the u[n] and outputs the z[n+l] .
  • the number of states and the number of branches are the same for the RLL-NRZI-PR FSM, namely, 18 states and 60 branches, respectively.
  • those data symbols x[3(n+l)-l] are emphasized by underlining, which serve as phase reference in states s' [n] . Because Table 2 only provides data symbols before NRZI, a single extra data symbol after NRZI is necessary to provide a phase reference anyway. Therefore, the number of states and branches in the FSM representing the RLL-NRZI-PR channel is at least twice as big as the corresponding numbers of Table 2.
  • Table 3 actually provides the most efficient way to represent a RLL- NRZI-PR channel. This is only possible because of the above metnioned special property of the (1,9) -RLL decoder FSM, that for a specific state the upcoming RLL codebits are the same.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

L'invention concerne un procédé de codage de canaux comprenant un codage DK et un précodage NRZI dont le résultat obéit à une contrainte de longueur de plage de transition minimale répétée (RMTR) et se prête à un décodage par FSM avec une profondeur de reconnaissance donnée. Les occurrences de violation de la RMTR par des séquences de bits critiques sont remplacées par des séquences de remplacement de même longueur contenant des plages de zéros prolongées, et l’aptitude au décodage par FSM avec une profondeur de reconnaissance donnée est obtenue en n’utilisant que les séquences de remplacement décodables avec la profondeur de reconnaissance donnée. L'invention concerne également un procédé apparenté de décodage par FSM de canaux et un appareil de décodage de canaux, ainsi que l’utilisation d’une FSM dans le décodage en treillis.
PCT/EP2009/051896 2008-02-22 2009-02-18 Procédé de codage de canaux, procédé et appareil de décodage de canaux Ceased WO2009103723A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP08101915.0 2008-02-22
EP08101915A EP2093884A1 (fr) 2008-02-22 2008-02-22 Procédé pour coder un canal, appareil et procédé pour le décodage de canal
EP08101916.8 2008-02-22
EP08101916 2008-02-22

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WO2009103723A1 true WO2009103723A1 (fr) 2009-08-27

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4337458A (en) * 1980-02-19 1982-06-29 Sperry Corporation Data encoding method and system employing two-thirds code rate with full word look-ahead
WO1999063671A1 (fr) * 1998-05-29 1999-12-09 Koninklijke Philips Electronics N.V. Appareil et procede de modulation/demodulation avec limitation de longueur de plage minimale consecutive

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4337458A (en) * 1980-02-19 1982-06-29 Sperry Corporation Data encoding method and system employing two-thirds code rate with full word look-ahead
WO1999063671A1 (fr) * 1998-05-29 1999-12-09 Koninklijke Philips Electronics N.V. Appareil et procede de modulation/demodulation avec limitation de longueur de plage minimale consecutive

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
COENE W ET AL: "A New d=1, k=10 Soft-Decodable RLL Code with r=2 MTR-Constraint and a 2-to-3 PCWA Mapping for DC-Control", OPTICAL DATA STORAGE TOPICAL MEETING, 2006 MONTREAL, QUEBEC, CANADA 23-26 APRIL 2006, PISCATAWAY, NJ, USA,IEEE, 23 April 2006 (2006-04-23), pages 168 - 170, XP010916954, ISBN: 0-7803-9494-1 *
H. HONG AND J. LEE: "A New Run-length-limited (2,7) Parity Preserving Code Limiting the Repeated Minimum Transition Run for Optical Storage Systems.", JAPANESE JOURNAL OF APPLIED PHYSICS, vol. 43, no. 7B, 2004, pages 4879 - 4881, XP002475665 *
T. MIYAUCHI, Y. IIDA, T. WATANABE, Y. URAKAWA: "Soft-Output Decoding of 17 Parity Preserve/Prohibit Repeated Minimum Transition Runlength (PP) Code.", JAPANESE JOURNAL OF APPLIED PHYSICS, vol. 43, no. 7B, 2004, pages 4882 - 4883, XP002475666 *

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