WO2009104129A2 - Circuits électroniques et procédé de commande de circuits électroniques - Google Patents

Circuits électroniques et procédé de commande de circuits électroniques Download PDF

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Publication number
WO2009104129A2
WO2009104129A2 PCT/IB2009/050637 IB2009050637W WO2009104129A2 WO 2009104129 A2 WO2009104129 A2 WO 2009104129A2 IB 2009050637 W IB2009050637 W IB 2009050637W WO 2009104129 A2 WO2009104129 A2 WO 2009104129A2
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WO
WIPO (PCT)
Prior art keywords
clock
logic
node
latch
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2009/050637
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English (en)
Other versions
WO2009104129A3 (fr
Inventor
Joseph Briaire
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
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Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of WO2009104129A2 publication Critical patent/WO2009104129A2/fr
Publication of WO2009104129A3 publication Critical patent/WO2009104129A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H03K3/356034—Bistable circuits using additional transistors in the input circuit the input circuit having a differential configuration
    • H03K3/356043—Bistable circuits using additional transistors in the input circuit the input circuit having a differential configuration with synchronous operation

Definitions

  • the present invention relates to an electronic circuitry and to a method of controlling an electronic circuitry.
  • current-mode logic CML In electronic circuitry, current-mode logic CML as well as CMOS logic are known.
  • the power consumption of current-mode logic CML is often considered as higher as that of CMOS logic due to the fact that current-mode logic requires a constant current while in the ON state while on the other hand CMOS logic only requires power when the logic has to change its state. Accordingly, if the switching activity is low, the power efficiency of CMOS logic will be better than the power efficiency of current mode logic.
  • this does not necessarily also apply for the clock circuitry or clock network required for the logic function. Due to its inherent characteristics, clock circuitries will always switch their state. This applies for current mode logic as well as CMOS logic. Accordingly, the power efficiency of current mode logic is not inferior to the power efficiency of CMOS logic for the cases of clock circuitry or a clock network.
  • US 2002/0003443 Al discloses a toggle flip-flop circuit with a master latch circuit with an emitter-coupled logic circuit, i.e. a current-mode logic circuit.
  • the clock of the master and slave latches are controlled simultaneously.
  • the global clock signal is provided in the voltage domain.
  • Fig. 2 shows a circuit diagram of a current-mode logic latch according to the prior art.
  • the latch comprises a current source I 0 , two transistors Tl, T2 which receive the clock signals CLK, CLK', respectively, and transistors T3, T4 which receive the input A, A', respectively.
  • the latch also comprises output terminals Z, Z'.
  • the input constitutes a differential input, wherein the differential bit is applied to the input terminals A, A'.
  • the input signal is sampled and hold at the output terminals Z, Z'.
  • the clock signals CLK, CLK' serve to define which leg is active and which is passive.
  • the current source Io is used to bias the latch.
  • the two transistors, T5, T6 are used to hold the sampled differential input bits.
  • the clock signals must be provided throughout the system, i.e. the clock signals need to be present for all latches within an electronic circuitry.
  • the electronic circuitry comprises a clock unit and a logic unit.
  • the logic unit comprises a plurality of latch logic units each with a hold node and sample node.
  • the clock unit comprises a clock circuitry for providing clock signals for the latch logic units.
  • the clock unit furthermore comprises a sample node and a hold node each for providing clock controlled current to the latch logic units.
  • the hold nodes and the sample nodes of the latch logic units are coupled to the sample node and the hold node of the clock unit, respectively.
  • each latch logic unit comprises an input for receiving an input signal and an output for holding the input signal.
  • the clock unit comprises a current source for providing a current according to the number of latch logic units in the logic unit. Accordingly, the current source must be able to provide sufficient current to drive all the latch logic units which are supplied with clock signals from the clock unit.
  • the sample node and hold node of the clock circuitry can be coupled to the sample and hold nodes of each latch logic unit.
  • the invention also relates to a method of controlling an electronic circuitry based on current-mode logic.
  • the electronic circuitry comprises a logic unit having a plurality of latch logic units each with a hold node and a sample node and a clock unit having a sample node and a hold node as well as a clock circuitry.
  • Each latch logic unit is coupled via their hold nodes and their sample nodes to the respective sample node and the hold node of the clock unit.
  • Clock signals are provided by the clock circuitry to the logic unit by providing clock controlled current to the latch logic units.
  • the present invention relates to the realization that for a latch based on current-mode logic CML, the current will be steered to the sample V s and hold Vh nodes.
  • the hold Vh (Vhoid) node is present between the transistors T5 and T6.
  • the sample V s (V samp ie) node is provided between the transistor T3 and T4.
  • the present invention also relates to the idea to split a latch based on a current- mode logic into its logic part (upwards from the V s and Vh nodes) and into a clock part which comprises the clock controlled current steering circuitry below the V s and Vh nodes.
  • the logic part of the latch will remain as it is but the clocked current steering circuitry will be placed centrally for several latches in an electronic circuitry. Accordingly, a plurality of logic latch cells will share common sample V s and hold Vh nodes or rails. Therefore, the clocked current will flow through these two lines or nodes and will increase as the number of latches increases. While the conventional voltage-based clock distribution has been used in the prior art, for example as depicted in Fig.
  • the distribution of the clock signals according to the invention is based on a current switching which is distributed over the electronic circuitry instead of a distribution of the clock signals itself. Accordingly, the current via the clock lines or via the sample and hold nodes is used for a clock distribution as well as to keep the latches in their desired state. As the power of a latch can also be used for a clock distribution, the power efficiency of the clock network can be improved.
  • One advantage of the electronic circuitry according to the invention is that a lower voltage swing is required for the clock distribution lines. Hence, a current mode logic clock network can be more power efficient than a CMOS based clock network. It should be noted that the parasitic clock wire capacitance will only increase at a slower rate. This is advantageous as the charging time for the parasitic capacitance will be reduced.
  • Fig. 1 shows a circuit diagram of an electronic circuitry according to the invention
  • Fig. 2 shows a circuit diagram of an electronic circuitry of a current-mode logic latch according to the prior art.
  • Fig. 1 shows a circuit diagram of an electronic circuitry according to the invention.
  • the electronic circuitry according to the invention relates to a plurality of current- mode logic latches.
  • the electronic circuitry comprises two units, namely a clock unit CP and a logic unit LP.
  • the clock unit CP is used for a plurality of logic units of the latches.
  • the clock unit CP comprises a current source Io for biasing the latch logic units of the logic unit LP and a first and second transistor Tl, T2.
  • the first transistor Tl receives the clock signal CLK and the second transistor T2 receives the clock signal CLK' at their gates, respectively.
  • the current source Io should be able to produce the required current to supply or drive all the latches in the electronic circuitry. IfN latches, i.e. N latch logic units are present, the current source should be able to supply NxIo current.
  • the logic unit LP may comprise the latch logic units of N latches.
  • a first latch logic unit Ll may comprise the input terminals A 1 , A'] and the output terminals Z 1 , Z'] for holding the input signal or bits as well as the transistors T31, T41, T51, T61.
  • the function of the transistors T31, T41, T51, T61 substantially correspond to the function of the transistors T3, T4, T5, T6 according to Fig. 2.
  • a first hold node Hl is coupled between the transistors T51, T61.
  • a first sample node Sl is coupled between the transistors T31, T41.
  • a second latch L2 may comprise the input terminals A 2 , A' 2 , the output terminals Z 2 , Z' 2 and the transistors T32, T42, T52 and T62.
  • the second latch L2 comprises a second hold node H2 coupled between the transistors T52, T62.
  • a N-th latch LN may comprise the input terminals A N , A' N , the output terminals Z N , Z' N as well as the transistors T3N, T4N, T5N, T6N.
  • the N-th latch LN comprises a nth hold node HN and a N-th sample node SN.
  • the clock unit CP comprises a first and second output terminal sample node, hold node SO, HO at which the sample voltage V s and the hold voltage Vh is applied, respectively.
  • the sample nodes Sl - SN are coupled to the first output terminal SO of the clock unit.
  • the hold nodes Hl - HN are coupled to the second output terminal HO of the clock unit CP.
  • the sample and hold nodes V s and Vh are shared between all latch parts of the electronic circuitry. Furthermore, instead of a dedicated clock unit for each latch the clock units CP are shared between a plurality of latches.
  • the clocked current flows through the sample and hold nodes SO, HO and will increase with the number of latches present in the circuitry.
  • the parasitic clock wire capacitance will increase at a slower pace such that the charging time for this parasitic capacitance will be reduced.
  • the voltage swing on the clock lines will be determined by the amount of overdrive voltage required to switch a logic state from active to passive or from passive to active.
  • the overdrive voltage will correspond to V GS -V T for a MOS technology.
  • the overdrive voltage is also influenced by the transconductance of the switches and by the amount of current being switched.
  • the overdrive voltage is also determined by the amount of leakage or bias current which is present in the passive state. Accordingly, a relative small amount of constant bias current can be added to the clock lines such that the switches do not switch off completely when switched into the passive state.
  • the current of the current-mode logic latch may be used to route clock signals across an electronic circuitry. The required voltage swing on these clock lines can be minimal such that less power is required for charging and discharging the clock network.
  • the clock distribution according to the present invention is based on a current switching by the clock signals CLK, CLK' .
  • the switched current is distributed over the circuitry instead of the clock signals themselves. Therefore, the current flowing through the clock lines can be used for the clock distribution as well as to keep the latches in their desired state.
  • the electronic circuitry according to the invention requires a lower voltage swing over the clock distribution lines such that a current mode logic clock network can be more power efficient than a CMOS based clock network.
  • the resistance in the paths towards the latches can be distributed symmetrically in order to ensure a symmetrical current distribution.
  • the electronic circuitry may also use source-coupled logic SCL or emitter-coupled logic ECL if a clock signal switches a bias current to more than one latch unit.

Landscapes

  • Logic Circuits (AREA)

Abstract

La présente invention concerne des circuits électroniques fondés sur une logique de mode de courant qui comprennent une unité logique (LP) possédant une pluralité d'unités logiques de verrouillage (L1, L2, LN), chacune de ces unités possédant un noeud de maintien (H1-HN) et un noeud d'échantillon (SI-SN) et une unité horloge (CP) possédant un noeud d'échantillon (SO) et un noeud de maintien (HO) ainsi que des circuits d'horloge (T1, T2, IN) destinés à fournir des signaux d'horloge à l'unité logique (LP) par la fourniture d'un courant commandé par l'horloge vers les unités logiques de verrouillage (L1 - LN). Chaque unité logique de verrouillage (L1, L2, LN) est couplé via leurs noeuds de maintien (HI-HN) et leurs noeuds d'échantillon (SI-SN) au noeud d'échantillon (SO) et au noeud de maintien (HO) respectifs de l'unité horloge (CP).
PCT/IB2009/050637 2008-02-18 2009-02-17 Circuits électroniques et procédé de commande de circuits électroniques Ceased WO2009104129A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP08101703.0 2008-02-18
EP08101703 2008-02-18

Publications (2)

Publication Number Publication Date
WO2009104129A2 true WO2009104129A2 (fr) 2009-08-27
WO2009104129A3 WO2009104129A3 (fr) 2009-12-17

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PCT/IB2009/050637 Ceased WO2009104129A2 (fr) 2008-02-18 2009-02-17 Circuits électroniques et procédé de commande de circuits électroniques

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI580232B (zh) * 2014-09-24 2017-04-21 瑞昱半導體股份有限公司 線性等化器

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002026717A (ja) * 2000-07-06 2002-01-25 Fujitsu Ltd トグルフリップフロップ回路、プリスケーラ及びｐｌｌ回路
US6614371B2 (en) * 2001-07-19 2003-09-02 Broadcom Corporation Synchronous data serialization circuit
US6501314B1 (en) * 2002-03-06 2002-12-31 Teradyne, Inc. Programmable differential D flip-flop

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI580232B (zh) * 2014-09-24 2017-04-21 瑞昱半導體股份有限公司 線性等化器

Also Published As

Publication number Publication date
WO2009104129A3 (fr) 2009-12-17

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