WO2009113015A2 - Système de traitement de données - Google Patents

Système de traitement de données Download PDF

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Publication number
WO2009113015A2
WO2009113015A2 PCT/IB2009/050978 IB2009050978W WO2009113015A2 WO 2009113015 A2 WO2009113015 A2 WO 2009113015A2 IB 2009050978 W IB2009050978 W IB 2009050978W WO 2009113015 A2 WO2009113015 A2 WO 2009113015A2
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WO
WIPO (PCT)
Prior art keywords
signal
phase
input signal
signals
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2009/050978
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English (en)
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WO2009113015A3 (fr
Inventor
Harald Witschnig
Peter Thueringer
Christian Patauner
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NXP BV
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NXP BV
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Filing date
Publication date
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Publication of WO2009113015A2 publication Critical patent/WO2009113015A2/fr
Publication of WO2009113015A3 publication Critical patent/WO2009113015A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
    • H03D3/007—Demodulation of angle-, frequency- or phase- modulated oscillations by converting the oscillations into two quadrature related signals

Definitions

  • the invention relates to a device for processing an input signal.
  • the invention further relates to a method of processing an input signal.
  • the invention relates to a program element.
  • the invention relates to a computer-readable medium.
  • contactless identification systems like transponder systems (for instance using an RFID tag) are suitable for a wireless transmission of data in a fast manner and without cable connections that may be disturbing.
  • Such systems use the emission and/or absorption of electromagnetic waves, particularly in the high frequency domain (for instance at frequencies of 800 MHz to 900 MHz).
  • such systems may be based on a magnetic coupling (for instance at a frequency of 13.56 MHz).
  • Such and other systems may use a phase modulated signal of a 13.56 MHz carrier from a reader to a card. Therefore, it is of significance to provide a proper corresponding receiver structure on the label side.
  • Phase demodulators itself are well known but have to be adapted for specific needs.
  • the need of very high data rates (several Mbit/s) based on a 13.56 MHz carrier may make it necessary to use higher order modulation schemes, and therefore new receive structures may be necessary as the actual concepts will not be able to handle the needs. Additionally it is to mention that the receive structure should be implemented on the card side and therefore the technical effort has to be as low as possible.
  • Fig. 6 schematically shows a conventional demodulation circuit 600 in which a received signal (phase modulated) 602 is coupled to a mixer 604 for mixing the signal 602 with cos(phi).
  • the mixed signal 606 is supplied to a matched filter unit 608 filtering the signal 606 to generate a signal 610 which is then supplied to a threshold detector 612.
  • the phase modulated signal 602 received via an antenna can thus be mixed by means of the mixer or multiplier 604 with cos(phi).
  • the received signal 606 is filtered by the filter unit 608.
  • the threshold detector 612 serves for assigning the voltage levels of the, for instance, step-shaped voltage characteristic to different logical states, to thereby reconstruct the information included in the radio signal 602.
  • the demodulator circuit 600 shown in Fig. 6 requires a relatively large space on an integrated circuit and consumes a lot of energy during operation. Furthermore, it may be difficult to detect PSK modulated signals, regarding current and area.
  • a device for processing an input signal comprising a plurality of phase shifting units (which may be connected in parallel signal paths to thereby obtain a cascade architecture) each adapted for phase shifting a synchronisation signal (which may be derived from the input signal; such a signal may be based on the input signal, for instance may be the carrier wave of the input signal, or may be a synchronized signal, such as a clock signal, which can be generated on the basis of the input signal) by an assigned phase value (wherein phase values assigned to different ones of the phase shifting units may be different, and one specific phase value may be assigned to each phase shifting unit), a plurality of mixer units (such as multiplier units; alternatively it is also possible to mix by sampling the signal, particularly to derive the base signal and to eliminate the carrier signal) each adapted for mixing the input signal with one of the plurality of phase shifted synchronisation signals (particularly in such a manner that each phase shifted synchron
  • a method of processing an input signal comprising phase shifting a synchronisation signal by a plurality of assigned phase values to thereby generate a plurality of phase shifted synchronisation signals (particularly, each of the phase shifted synchronisation signals may be generated in a separate signal path independent of the generation of the other phase shifted synchronisation signals in parallel signal paths, thereby providing a cascade architecture), mixing the input signal with each of the plurality of phase shifted synchronisation signals (particularly individually, i.e. each of the mixed signals may be generated in a separate signal path independent of the generation of the other mixed signals in parallel signal paths, thereby providing a cascade architecture), and extracting information from each of the mixed signals.
  • a computer-readable medium for instance an EEPROM, a CD, a DVD, a USB stick, a floppy disk or a harddisk
  • a computer program of data processing is stored which, when being executed by a processor, is adapted to control or carry out a method having the above mentioned features.
  • Data processing which may be performed according to embodiments of the invention can be realized by a computer program, that is by software, or by using one or more special electronic optimization circuits, that is in hardware, or in hybrid form, that is by means of software components and hardware components.
  • a receiver structure for demodulating a phase modulated signal may be provided.
  • Such a system may be implemented in different technical fields but may be specifically advantageous for RFID (Radio Frequency
  • NFC Near Field Communication
  • Exemplary embodiments of the invention may further consume much less silicon area and - A - energy during operation as compared to conventional demodulator circuits. Thus, such an architecture is specifically suitable for RFID and NFC applications with high data rates.
  • Systems according to exemplary embodiments of the invention may use a phase modulated signal (for instance of a 13.56 MHz carrier) from a reader to a card, or from a card to a reader.
  • a demodulator in which an input signal can be processed by mixing the input signal with a plurality of manipulated signals.
  • the manipulated signals may be formed based on the input signal.
  • an intermediate signal may be formed which may represent a recovered carrier wave of the input signal or may be generated by centrally synchronizing the input signal to generate a common clock.
  • the intermediate signal may be subsequently (in parallel signal paths) phase shifted with individual phase shift values which are different for the different processing paths, thereby forming the manipulated signals.
  • mixers may combine each of the manipulated signals individually with the input signal and may individually reconstruct information portions encoded in the input signal in the different processing paths.
  • the input signal can be mixed using a plurality of mixers or multipliers with several phase shifted signals received from a circuit formed by a phase locked loop (PLL) and a number of phase shifters.
  • PLL phase locked loop
  • the received signals can be supplied to parallel-arranged filters (particularly low pass filters) and comparators. For example (see also Fig.
  • a first comparator delivers a logical value "1" only, when the phase position is 45° of the input signal (see also diagram 460)
  • a second comparator delivers a logical value "1" only, when the phase position is 135° of the input signal (see also diagram 470) and so on.
  • a number of (for instance four) parallel data streams may be received which can be combined with a multiplier (not shown).
  • Such a circuit architecture can be implemented with any desired number of stages. Differences as compared to conventional approaches are not only the implementation of a phase locked loop in the signal path, but a cascaded structure based on phase shifts and the following detection by comparators.
  • a device for demodulating a phase modulated input signal comprising a phase locked loop to generate a clock signal based on said input signal, N phase shifters having said clock signal as input signal and providing N phase shifted clock signals, N mixers for mixing said input signal with said N phase shifted clock signals, and N filter stages and N downstream comparators for assigning a logical state to said mixed signals, wherein N is a natural number greater than one.
  • a cascaded receive structure for phase modulated signals is provided, particularly in the 13.56 MHz signal domain.
  • Applications of RFID systems in particular Near Field Communication Systems, NFC
  • NFC Near Field Communication Systems
  • An example of such an application is an electronic passport where pictures, fingerprints and other biometric data have to be transferred with the shortest time possible.
  • a new (transmission)concept and strategy is provided, enabling high transmission rates.
  • the device may comprise a synchronisation unit arranged upstream (related to a direction of the signal propagation) of the plurality of phase shifting units and adapted for deriving the synchronization signal from the input signal.
  • a dedicated component may be connected between an input signal terminal and the parallel circuited phase shift units which dedicated component manipulates the input signal, for instance to generate a recovered carrier wave (which may function as a clock signal) from the input signal being a modulated carrier wave.
  • a centrally arranged synchronisation unit may be followed by a splitting of the signal path to several parallel or cascaded paths.
  • the synchronisation unit may be a phase-locked loop (PLL).
  • phase-locked loop may particularly denote an entity that generates a signal that has a fixed relation to the phase of a reference signal.
  • a phase-locked loop circuit may be denoted as a circuit member by which a local oscillator is synchronized in phase and frequency with a signal being received.
  • a PLL may be implemented, according to an exemplary embodiment, to derive frequency information and thus timing information for the signal processing.
  • the synchronisation unit may be a costas loop, a polarity loop, or a remodulator.
  • any other electric member may be implemented which has the capability of deriving a signal representing the carrier signal of the input unit.
  • the synchronisation signal may be indicative of a carrier wave of the input signal.
  • the input signal may comprise a carrier wave (for instance a 13.56 MHz carrier wave in case of an RFID system) on which the use information is modulated, for instance by phase modulation or amplitude modulation.
  • the carrier wave may be recovered or isolated and may be used (after phase-shifting) for multiplication with the input signal for the purpose of use information recovery.
  • the synchronisation signal is measured, known or pre-stored in the system, for instance is stored in a memory unit of an RFID tag operating at a standard of, for instance, a 13.56 MHz carrier wave.
  • a synchronisation unit may be omitted.
  • the carrier wave frequency is known in advance, i.e. without determination by a PLL or the like, and should therefore be known with sufficient accuracy.
  • the device may be adapted for demodulating a phase modulated input signal. Phase modulation may be denoted as a form of modulation that represents information as variations in the instantaneous phase of a carrier wave.
  • the extraction unit may comprise a filter unit adapted for filtering the mixed signals.
  • a filter unit may be a low pass filter unit, in order to remove undesired high frequency contributions.
  • a low pass filter may be denoted as a filter that passes all frequencies below its cut-off frequency and rejects those above the cut-off.
  • an output of the mixer for instance a multiplier
  • the filter may have the capability of removing or suppressing such a double frequency.
  • the extraction unit may further comprise a comparator unit adapted for comparing the filtered mixed signals with a threshold value to extract a logical value for each of the filtered mixed signals.
  • a logical value may be a logical value "1" or a logical value "0".
  • the comparator unit may be formed as a single comparator member having, in addition to an input at which a reference signal is provided, a plurality of use signal inputs, or may be formed as a plurality of separate comparator members each having, in addition to an input at which a reference signal is provided, one or more use signal inputs. In other words, instead of using a number M of comparators, it is possible to use only one comparator with M inputs, or another set in between.
  • the device may comprise a plurality of parallel signal processing paths. This may allow for a fast parallel processing, since different signals can be evaluated parallel in time.
  • a cascade of several circuit paths which are connected in parallel to one another may be each provided with a serial arrangement of mixer unit, filter unit and comparator unit.
  • the parallel signal processing enabled with such an architecture may result in a fast and accurate signal evaluation.
  • the device may comprise a plurality of phase shifting units having assigned phase values which are equally distributed.
  • the term "equally distributed” may particularly denote that the distance or delta between phase shifts of subsequent phase shifting units have a constant value. For example, this may be achieved by phase shifting units which shift the signal by 90°, 180°, and 270°. Alternatively, this may be achieved by phase shifting units which shift the signal by 45°, 135°, 225° and 315°. Many other combinations are, of course, possible.
  • the device may comprise a multiplexer unit adapted for multiplexing signals output by the extraction unit. Thus, such a multiplexer may generate a data stream based on the output signals of the comparators.
  • a multiplexer may be denoted as a device that selects one of many data sources at a time and outputs that source into a single channel.
  • transponder may particularly denote an RFID tag or a contactless chip card. More generally, a transponder may be a device (for instance comprising a chip) which may automatically transmit certain (for example coded) data when activated by a special signal from an interrogator. The transponder may be a (for instance contactless) smartcard.
  • An RFID tag may comprise a semiconductor chip (having an integrated circuit) in which data may be programmed or rewritten, and a high frequency antenna matched to an operation frequency band used (for example 13.56 MHz).
  • an RFID system may comprise a read/write device (i.e. a base station) and a system antenna enabling a bidirectional wireless data communication between the RFID tag and the read/write device. Use of a dipole antenna is possible.
  • an input/output device for instance a computer
  • Different types of RFID systems are distinguished, namely active RFID systems (supply by a battery) and passive RFID systems (supplied with energy via the RF field).
  • semi-active (semi-passive) systems which are passively activated and in which a battery is used on demand (for instance for transmitting data) are available.
  • polymer tags can be used, according to an exemplary embodiment of the invention.
  • a smartcard or chip card can be a tiny secure crypto processor embedded within a credit card-sized card or within an even smaller card.
  • a smartcard does usually not contain a battery, but power is supplied by a card reader/writer, that is to say by a read and/or write device for controlling the functionality of the smartcard by reading data from the smartcard or by writing data in the smartcard.
  • a smartcard device may particularly be used in the areas of finance, security access and transportation.
  • Such smartcards may contain high security processors that function as a security storage of data like card holder data (for instance name, account numbers, a number of collected loyalty points).
  • the device (for instance an RFID tag) may be free of any oscillating crystal generating a frequency. Thus, the device may be manufactured in a very small dimension. Thus, no oscillator has to be used for clock generation, but in contrast to this, energy and clock are derived from the generating field.
  • the device may be adapted as a receiver device (such as an RFID tag) to be communicatively coupled to a sender device (such as a base station).
  • a signal may be modulated (for instance in a conventional manner) and transmitted to the receiver device for demodulation, as described herein.
  • Exemplary fields of application of embodiments of the invention relate to eGovernment public services, for instance National ID, health cards, driving licenses, etc.
  • Applications like digital signature, log on, secure transactions are further fields of application.
  • Fig. 1 illustrates a demodulator circuit according to an exemplary embodiment of the invention.
  • Fig. 2 illustrates a demodulator circuit according to another exemplary embodiment of the invention.
  • Fig. 3 illustrates an RFID tag according to an exemplary embodiment of the invention.
  • Fig. 4 shows signal forms obtainable with a demodulator circuit according to an exemplary embodiment of the invention.
  • Fig. 5 illustrates a demodulator circuit according to another exemplary embodiment of the invention.
  • Fig. 6 illustrates a conventional demodulator.
  • Fig. 1 illustrates a demodulator circuit 100 according to an exemplary embodiment of the invention.
  • the demodulator circuit 100 is adapted for demodulating a phase modulated input signal 102.
  • the input signal 102 is supplied to an input of a phase locked loop 104 adapted for generating a clock signal or synchronization signal 108 on the basis of the input signal 102.
  • the PLL 104 may derive a carrier frequency of the phase-modulated input signal 102 as the synchronization signal 108.
  • the synchronized signal 108 output by the phase locked loop 104 is supplied in parallel to each of a plurality of phase shifting units 106 each adapted for phase shifting the synchronized signal 108 by an assigned phase value.
  • a phase shifting unit 106 provides for a phase shifting by 45°.
  • a phase shifting unit 106 provides for a phase shifting by 135°.
  • the corresponding phase shifting unit 106 provides for phase shifting of 225°.
  • the corresponding phase shifting unit 106 provides for a phase shifting by 315°.
  • An output signal 112 of each of the phase shifting unit 106 which may be denoted as a phase shifted synchronisation signal 112 is supplied to a corresponding one of mixer units 110 in each of the signal paths, as can be taken from Fig. 1.
  • Each of the mixer units 110 mixes (particularly multiplies or samples) the input signal 102 with the respective phase shifted signal 112 at another input of the respective mixer unit 110, namely the respective phase shifted signals 112 in all four signal paths of the cascaded configurations.
  • a mixed signal 116 of each signal path provided at an output of the corresponding mixer units 110 is then supplied to an extraction unit 114 which is adapted for extracting information from each of the mixed signals 116 to reconstruct a data content of the input signal 102.
  • the extraction unit 114 comprises, in each of the four parallel signal paths, a respective low pass filter 118 for low pass filtering the signal 116 to derive a filtered signal 122.
  • the filtered signal 122 is then supplied to a comparator unit 120 which is provided as well in each of the signal paths of Fig. 1.
  • the comparator unit 120 compares the filtered mixed signal 122 with a reference value to extract a logical value for each of the filtered mixed signals 122 in accordance with a logic which is schematically indicated by reference numeral 124.
  • a multiplexer unit 126 is supplied with the signals 130 output by the extraction unit 114 to multiplex these signals 130.
  • a signal indicative of the content of the phase modulated input signal 102 is provided.
  • the demodulator circuit 100 relates to a receiver structure of an RFID tag which allows to detect a 4-PSK.
  • M is a natural number larger than one.
  • the first comparator 120 provides a logical value "1" only when the phase position is 45° of the input signal 102 (see also the output signal 460 of the comparator in Fig. 4), otherwise the first comparator 120 provides a logical value "0".
  • four parallel data streams are received which can be combined by the multiplexer 126.
  • the demodulator circuit 100 of Fig. 1 can be extended to any desired value of stages.
  • a demodulator device 200 according to another exemplary embodiment of the invention which is shown in Fig. 2 differs from the embodiment of Fig. 1 particularly in that no multiplexer 126 is provided so that individual data signals 130 are provided at the output of the demodulator circuit 200. Furthermore, instead of providing an individual comparator unit 120 for each of the parallel signal processing paths of Fig. 1, the embodiment of Fig. 2 uses a single comparator member 202 having four use signal inputs.
  • Fig. 3 illustrates an RFID tag 300 according to an exemplary embodiment of the invention.
  • the RFID tag 300 comprises a substrate 302 such as a fabric or a plastic label.
  • a substrate 302 such as a fabric or a plastic label.
  • an integrated circuit 306 (such as an electronic chip, for instance a silicon chip, but other materials are possible) is mounted which may be formed in silicon technology.
  • the integrated circuit 306 includes, inter alia, a demodulator circuit 100.
  • the integrated circuit 306 may include further electronic components, such as a rectifier, a modulator, a memory, an encryptor, a decryptor, etc.
  • An antenna coil 304 is coupled with the integrated circuit 306.
  • the antenna 304 is adapted for receiving a magnetic or an electromagnetic wave 308 generated by a reader/writer device (not shown).
  • the demodulator circuit 100 of the integrated circuit 306 may demodulate the received signal.
  • Fig. 4 shows diagrams illustrating various signals occurring in the demodulator circuit 100.
  • Each of the diagrams of Fig. 4 has an abscissa (horizontally aligned) along which a time is plotted in microseconds.
  • abscissa horizontal aligned
  • a time is plotted in microseconds.
  • ordinates vertical aligned
  • corresponding signal values are plotted.
  • a diagram 400 of Fig. 4 shows the time dependence of the phase modulated input signal 102.
  • a diagram 410 shows the digital content of the phase modulated input signal 102 to be reconstructed by the demodulator circuit 100.
  • diagram 410 shows a baseband signal representing four different phases.
  • a diagram 420 shows the signal 116 output by the low-pass filter 118 in the first (most upper) signal processing path of the demodulator circuit 100.
  • a diagram 430 shows the signal 116 output by the low-pass filter 118 in the second signal processing path of the demodulator circuit 100.
  • a diagram 440 shows the signal 116 output by the low-pass filter 118 in the third signal processing path of the demodulator circuit 100.
  • a diagram 450 shows the signal 116 output by the low-pass filter 118 in the forth (lowest) signal processing path of the demodulator circuit 100.
  • the signal content is still smeared out due to overlaid high-frequency components. Since the filter units 118 are not ideal filters, it may happen that a small contribution of a high frequency disturbation is still present on the signals shown in diagrams 420, 430, 440, and 450.
  • a diagram 460 shows the signal 130 output downstream the comparator unit 120 in the first (most upper) signal processing path of the demodulator circuit 100.
  • a diagram 470 shows the signal 130 output downstream the comparator unit 120 in the second signal processing path of the demodulator circuit 100.
  • a diagram 480 shows the signal 130 output downstream the comparator unit 120 in the third signal processing path of the demodulator circuit 100.
  • a diagram 490 shows the signal 130 output downstream the comparator unit 120 in the forth (lowest) signal processing path of the demodulator circuit 100. As can be taken from Fig. 4, the signal content 410 can be reconstructed based on the comparator outputs shown in diagrams 460, 470, 480, 490.
  • Fig. 5 illustrates a demodulator circuit 500 according to another exemplary embodiment of the invention. This circuit is simplified and is only schematical to illustrate the function. According to Fig. 5, the synchronisation signal 108 is directly supplied to the phase shift units 106.
  • the synchronisation signal 108 is pre-stored in the system 500 and is indicative of the carrier frequency of the input signal 102.
  • a synchronisation unit is omitted.
  • Fig. 5 further illustrates an electronic ground potential 502 applied to several terminals of the circuit 500.
  • a plurality of resistors 504 are interconnected in the demodulator circuit 500.
  • a PSK unit 506 Phase Shift Keying is connected upstream of the mixers 110.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

La présente invention concerne un dispositif (100) pour traiter un signal d'entrée (102), le dispositif (100) comprenant une pluralité d'unités de déphasage (106), chacune conçue pour déphaser un signal de synchronisation (108) d'une valeur de phase attribuée, une pluralité d'unités de mixage (110), chacune conçue pour mixer le signal d'entrée (102) avec un signal de la pluralité de signaux de synchronisation déphasés (112), et une unité d'extraction (114) conçue pour extraire des informations de chacun des signaux mixés (116).
PCT/IB2009/050978 2008-03-10 2009-03-09 Système de traitement de données Ceased WO2009113015A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP08102449 2008-03-10
EP08102449.9 2008-03-10

Publications (2)

Publication Number Publication Date
WO2009113015A2 true WO2009113015A2 (fr) 2009-09-17
WO2009113015A3 WO2009113015A3 (fr) 2010-06-03

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104112108A (zh) * 2014-06-30 2014-10-22 广西瀚特信息产业股份有限公司 一种多频段rfid读取装置及方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52149951A (en) * 1976-06-08 1977-12-13 Nec Corp Carrier regeneration circuit
JP3414052B2 (ja) * 1995-05-18 2003-06-09 三菱電機株式会社 位相変調信号復調方式
JP2002076976A (ja) * 2000-08-28 2002-03-15 Matsushita Electric Ind Co Ltd ダイレクトコンバージョン受信装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104112108A (zh) * 2014-06-30 2014-10-22 广西瀚特信息产业股份有限公司 一种多频段rfid读取装置及方法

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