WO2009122579A1 - Procédé et dispositif destinés à améliorer la stabilité d'une cellule sram cmos sgt 6t - Google Patents

Procédé et dispositif destinés à améliorer la stabilité d'une cellule sram cmos sgt 6t Download PDF

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WO2009122579A1
WO2009122579A1 PCT/JP2008/056682 JP2008056682W WO2009122579A1 WO 2009122579 A1 WO2009122579 A1 WO 2009122579A1 JP 2008056682 W JP2008056682 W JP 2008056682W WO 2009122579 A1 WO2009122579 A1 WO 2009122579A1
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sgt
plane
transistor
sram
access
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Japanese (ja)
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富士雄 舛岡
建宰 李
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Unisantis Electronics Japan Ltd
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Unisantis Electronics Japan Ltd
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Priority to PCT/JP2008/056682 priority Critical patent/WO2009122579A1/fr
Priority to TW098110603A priority patent/TW200947676A/zh
Priority to PCT/JP2009/056949 priority patent/WO2009123306A1/fr
Publication of WO2009122579A1 publication Critical patent/WO2009122579A1/fr
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/405—Orientations of crystalline planes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies

Definitions

  • the present invention relates to a method and structure for improving the stability of 6T SGT CMOS SRAM cells.
  • SRAM Static random access memory
  • NPD NMOS pulldown NMOS
  • the stability at the time of writing to the SRAM is mainly determined by the relative strength of the drive capability of the pull-up PMOS (or load transistor) and pull-down NMOS transistor.
  • Static noise margin is defined as the minimum noise voltage required to invert the cell state present at each storage node of the cell.
  • the access NMOS transistor is arranged in parallel with the pull-up PMOS, and this reduces the gain of the SRAM inverter during the read operation.
  • the node storing “0” in the SRAM rises to a voltage higher than the ground voltage due to voltage division along the access NMOS and pull-down NMOS. That is, the ratio of the conductance of the drive NMOS transistor to the conductance of the access NMOS transistor is a basic measure for knowing the read stability of the SRAM cell.
  • ⁇ ratio This ratio is called “beta ratio ( ⁇ ratio)” in the design field of CMOS SRAM. Since the drive capability ( ⁇ ) of each transistor is equal to ⁇ C ox W / L (mobility ⁇ capacitance ⁇ channel width / gate length), the ⁇ ratio is expressed as follows. (For more detailed information, see Seevinck et al., “Static noise margin analysis of MOS SRAM cells”, IEEE JSSC, sc-22, No. 5, October 1987, page 748)
  • V s the storage node voltage (V s ) is determined by the beta ratio and is expressed as: V ds ⁇ V dsat (linear) V ds > V dsat (sat)
  • the beta ratio determines how much the voltage V s at the node where “0” is stored at the time of reading increases.
  • Vs storage node voltage
  • the larger the beta ratio the more stable the cell and the larger the SNM.
  • the beta ratio when the beta ratio is increased, the required W drive is increased, and as a result, the cell size is increased (and therefore the cost is increased). For this reason, balancing cell size and SRAM stability is an important point in designing an optimal SRAM cell.
  • SGT Surrounding Gate Transistor
  • FIG. 4 is a layout diagram showing an SGT SRAM composed of two drive transistors (NMOS) 1001, two access transistors 1002, and two load transistors 1003.
  • Reference numeral 1004 denotes a contact portion.
  • FIG. 5 (a) shows a FINFET SRAM cell having four drive transistors (DR1, DR2, DR3, DR4), two access fin transistors (TR1, TR2), and two load transistors (LO1, LO2). Yes.
  • FIG. 5 (a) shows a FINFET SRAM cell having four drive transistors (DR1, DR2, DR3, DR4), two access fin transistors (TR1, TR2), and two load transistors (LO1, LO2). Yes.
  • FIG. 5 (b) shows a 6T FINFET SRAM cell having two drive transistors (NPD, NPD 2 ), two access fin transistors (Access, Access 2 ), and two load transistors (Load, Load 2 ).
  • the driving transistor (NPD, NPD 2 ) has a crystal plane rotated by 45 ° with respect to the access transistor (Access, Access 2 ) and the load transistor (Load, Load 2 ) so that the gain varies depending on the corresponding crystal plane. It is supposed to be.
  • FIG. 5 (c) shows a 6T FINFET SRAM cell having two drive transistors (N102, N103), two access fin transistors (N100, N101), and two load transistors (P100, P101).
  • N102, N103 two drive transistors
  • N100, N101 two access fin transistors
  • P100, P101 two load transistors
  • the drive transistors (N102, NP103) are made to be crystals rotated by 45 ° with respect to the access transistors (N100, N101) and the load transistors (P100, P101) so as to have different gains depending on the corresponding crystal planes. ing.
  • An object of the present invention is to provide a device structure of a 6T SGT CMOS ⁇ ⁇ ⁇ ⁇ SRAM cell having a sufficiently high SNM and a manufacturing method thereof.
  • a SGT body comprising a first portion having a first surface orientation of a sidewall providing a first carrier mobility and a second portion having a second surface orientation of the sidewall providing a second carrier mobility
  • An access transistor formed in the first portion of the SGT body portion;
  • a drive transistor formed in the second portion of the SGT body; Including
  • the access transistor is an n-channel transistor;
  • the driving transistor is an n-channel transistor;
  • the access transistor and the drive transistor are part of a memory cell;
  • the access transistor is connected to the drive transistor for passing data, It is characterized by that.
  • the first carrier mobility can be made smaller than the second carrier mobility.
  • the access transistor and the latch transistor have a gain, and the access transistor gain may be smaller than the latch transistor gain because the first carrier mobility is smaller than the second carrier mobility. it can.
  • the first plane may be a ⁇ 110 ⁇ plane and the second plane may be a ⁇ 100 ⁇ plane.
  • the memory cell is, for example, an SRAM memory cell.
  • the present invention provides an SGT semiconductor memory including a plurality of SGTs, First and second SGTs each having a first line as a gate and having one end of a current path of each SGT connected to a reference electrode to which a reference potential is supplied; Third and fourth SGTs having a second line as a gate and having one end of a current path of each SGT connected to the reference electrode; A fifth SGT having a first word line as a gate and one end of the current path of the SGT connected to the other side of the current path of the first and second SGTs; A sixth SGT having a second word line as a gate, one end of the current path of the SCT being connected to the other side of the current path of the third and fourth SGTs; A seventh field effect transistor having the first line as a gate; An eighth field effect transistor having the second line as a gate; Including The current paths of the first and second SGTs are connected in parallel between the one end of the current path of the fifth SGT and the reference electrode, and the
  • Each of the first, second, third, and fourth transistors can form a drive transistor, and each of the fifth and sixth transistors can form an access transistor.
  • One end of the current paths of the seventh and eighth SGTs is connected to, for example, a power supply electrode supplied with a power supply voltage.
  • Embodiments of the present invention are applicable to any device where it is desirable for each transistor to have a different gain. Such include a wide range of logic circuits such as latches. In one embodiment, the present invention applies to the design and manufacture of “static random access memory (SRAM)” cells.
  • SRAM static random access memory
  • the first embodiment of the present invention is an SGT device, an access NMOS device whose side wall surface is a first crystal plane so as to have a first carrier mobility, and a second carrier mobility. Including a pull-down NMOS device having a second crystal plane on the side wall and a pull-up PMOS device having a third crystal plane on the side wall to achieve a third carrier mobility. And an SGT device in which at least one of the third crystal planes is different from the other two crystal planes.
  • This embodiment is formed of an SGT transistor having a relatively low gain having a surface with low carrier mobility and an SGT transistor having a relatively high gain having a surface having high carrier mobility.
  • An SGT having a surface with high mobility has a higher gain than an SGT having a surface with low mobility. Therefore, the first embodiment of the 6T SGT SRAM cell can provide a device in which SNM is improved by using SGTs having different gains and a design method thereof without disadvantageously increasing the SRAM cell area. .
  • the n-type SGT rectangular pillar side wall surface orientation is ⁇ 110 ⁇
  • another n-type SGT rectangular pillar side wall surface orientation is ⁇ 100 ⁇ .
  • the electron mobility in the ⁇ 110 ⁇ plane is about half of the electron mobility in the ⁇ 100 ⁇ plane. Therefore, the n-type SGT formed with the ⁇ 110 ⁇ plane as a side wall has a gain about half that of the n-type SGT formed with the ⁇ 100 ⁇ plane as a side wall.
  • SRAM the body of n-type SGT used as a transfer device is formed along the ⁇ 110 ⁇ plane.
  • the body parts of the n-type SGT and the p-type SGT used as the memory latch are formed along ⁇ 100 ⁇ .
  • the hole mobility in the ⁇ 100 ⁇ plane is less than half of the electron mobility in the ⁇ 110 ⁇ plane.
  • the side wall of the cylindrical pillar of n-type SGT is formed with various crystal planes, and the side orientation of the side wall of another rectangular pillar of n-type SGT is ⁇ 100 ⁇ .
  • the electron mobility of the cylindrical pillar is about 3/4 of the electron mobility of the ⁇ 100 ⁇ plane. That is, the cylindrical pillar n-type SGT has a gain of about 3/4 of that of the n-type SGT whose side wall is a ⁇ 100 ⁇ plane.
  • the second embodiment of the present invention includes two access NMOS devices, each access NMOS having a single SGT pillar, four pull-down NMOS devices, each pull-down NMOS having a single SGT pillar, and each pull-up PMOS.
  • Each atom forming a crystal in a solid crystal is periodically arranged, and this periodic arrangement is called a lattice.
  • the crystal lattice repeats regularly throughout the lattice.
  • the orientation in the lattice is represented by the same set of three integers with the same vector components as the orientation.
  • the three vector components are represented by multiples of the basic vector components.
  • a cubic lattice such as silicon having a diamond structure exists along the diagonal [111] direction.
  • the brackets [] indicate a specific direction.
  • crystals many directions are equivalent in symmetric transformation, depending on how the axis orientation is selected. For example, crystal orientations [100], [010], and [001] in the cubic lattice are all crystallographically equivalent.
  • ⁇ > brackets a certain orientation and all equivalent orientations are indicated by ⁇ > brackets. Therefore, when ⁇ 100> is specified, all equivalent orientations [100], [010], and [001] are included. Since these orientations are on the negative side of the origin (optionally defined), the crystal orientation includes both positive and negative integers unless a separate explanation or indication is in the present application. Thus, for example, when ⁇ 100> is designated, in addition to [100], [010], and [001], each orientation of [ ⁇ 100], [0-10], and [00-1] is included.
  • the plane orientation in the crystal can be specified by a set of three integers. The set of three integers in parentheses () used to define a set of parallel planes specifies a particular plane.
  • the plane specified by a particular three integers is perpendicular to the orientation specified by the same three integers.
  • a plane perpendicular to the azimuth [100] is represented by (100). Therefore, if the direction or plane of the cubic lattice is known, the counterpart perpendicular to it can be known without calculation. Similar to the direction case, many planes in the lattice are equivalent by symmetric transformation. For example, the (100) plane, (010) plane, and (001) plane are inherently symmetrical planes. In this application, a plane and all of its equivalent planes are represented by parentheses ⁇ . Therefore, the plane specified by ⁇ 100 ⁇ includes the (100) plane, the (010) plane, and the (001) plane.
  • crystal planes in this application include positive and negative integers unless otherwise stated or indicated.
  • the plane ⁇ 100 ⁇ includes the (-100) plane, the (0-10) plane, and the (00-1) plane in addition to the (100) plane, the (010) plane, and the (001) plane. .
  • the first embodiment of the present invention provides a FET current channel and column shape.
  • various crystal planes can be used to easily adapt to various methods of fabricating CMOS SGTs on the same substrate.
  • FIG. 1 shows various plane orientations of the sidewalls of Si-SGT pillars manufactured on the (100) plane (FIG. 1 (a)) and (110) plane (FIG. 1b) of the Si wafer.
  • FIG. 2 is a side view of the SGT pillar sidewall described in relation to FIG. The mobility of electrons and holes corresponding to the orientation is shown (see US Pat. No. 3,603,848 to Sato et al.).
  • the device on (100) of the wafer uses the left curve (0 ° / (011) to 45 ° / (001) sidewall, [100] zone) and the device on (110) 0 ° / (011) to 90 ° / (001) sidewalls, [110] zone). In any case, the direction of current flow is perpendicular to the wafer surface.
  • FIG. 3 shows a table of normalized current values for various CMOS SGT combinations described in PCT / JP2007 / 071052. Shown are 25 different CMOS combinations with different shapes and rotated shapes, each combination having a different pillar shape and corresponding plane orientation.
  • the relative gain of the access NFET is the relative gain of the access NFET. For example, if the access NFET is too weak (ie, the beta value is small), it cannot be said that the write stability is reliable to store data in the SRAM storage latch. If the access NFET is too strong (ie, the beta value is large), the storage latch can be reversed unexpectedly by an external noise source or the internal capacitance of the bit line. Therefore, the relative gain of the access NFET must be carefully determined. With normal design parameters, the access NFET gain should be about half of the NFET gain in the storage latch.
  • the relative dimension between devices was changed to make a difference between gains of access NFETs.
  • the width of the device is increased. Therefore, to increase the gain of the above-described transistor relative to the transfer NFET, the width of the storage latch NFET is increased.
  • the transfer NFET gate length can be increased to reduce the relative gain of the NFET described above.
  • these methods increase the size of the FET device with increased strength and cannot increase the device density.
  • the present invention makes it possible to form NFETs having different gains without adversely affecting the size of many devices.
  • the gain is relatively reduced by forming it in the low carrier mobility plane.
  • the gain is relatively increased by forming it on the high carrier mobility surface.
  • the gain that is, only by changing the plane orientation of the side wall between the drive NMOS transistor and the access NMOS transistor
  • Different beta ratio the gain
  • FIG. 8A shows a circuit diagram of the completed SGT SRAM and a plan view of the device for an example of one SRAM optimized from the combination of SRAMs shown in FIG. 6 (SRAM 12 in FIG. 6). ing.
  • the SRAM is formed on the (100) plane of the Si wafer. As shown in the figure, this SRAM has two square access NMOSs (N12, N22, all four sidewalls of the square pillar are (110) planes), two square load PMOSs (P12, P22, four square pillars, four The side walls are all (100) planes), and two square drive NMOSs (N32, N42, the four side walls of the square pillar are all (100) planes).
  • the load PFETs (P12 and P22) and the drive NFETs (N12 and N22) form a storage latch used to store data in the SRAM cell, and the access NFETs (N32, N42) are between the storage latches. It serves as a transfer device for exchanging data.
  • the SRAM cell shown in FIG. 8A is connected as follows to form an SGT SRAM cell.
  • the drive NMOS (N32) has a first gate line common to the gate, and one end of a current path for current is connected to a reference electrode to which a reference potential V SS is supplied.
  • the drive NMOS (N42) has a second gate line common to the gate, and one end of the current path is connected to a reference electrode to which a reference potential V ss is supplied.
  • the access NMOS (N12) the first word line is connected to the gate, and one end of the access NMOS (N12) current path is connected to the opposite side of the current path of the drive NMOS (N32).
  • the access NMOS (N22) has a second word line connected to the gate, and one end of the access NMOS (N22) current path is connected to the opposite side of the current path of the drive NMOS (N42).
  • the current path of the drive NMOS (N32) is connected between one end of the current path of the access NMOS (N12) and the reference electrode.
  • the current path of the drive NMOS (N42) is connected between the current path of the access NMOS (N22) and the reference electrode.
  • the load PMOS (P12) has the first gate line as a gate, and one end of the current path is connected to a power supply electrode to which a power supply voltage is supplied.
  • the load PMOS (P22) has the second gate line as a gate, and one end of the current path is connected to a power supply electrode to which a power supply voltage is supplied.
  • the other end of the current path of the drive NMOS (N32) is connected to the other end of the current path of the load PMOS (P12).
  • the opposite side of the current path of the drive NMOS (N42) is connected to the opposite side of the current path of the load PMOS (P22).
  • the gates of the drive NMOS (N32) and the load PMOS (P12) are connected to the opposite side of the current path of the drive NMOS (N42).
  • the gates of the drive NMOS (N42) and the load PMOS (P22) are connected to the opposite side of the current path of the load PMOS (P12).
  • FIGS. 8B to 8E show the completed 6T SGT CMOS taken along lines AA ′, BB ′, CC ′, and DD ′ in FIG. 8A. It is a longitudinal cross-sectional view of an SRAM device.
  • the Si pillars of NMOS (N12, N22, N32, N42) and Si pillars of PMOS (P12, P22) are formed on the SOI wafer and surrounded by the gate oxide film 131 and the gate conductor 132.
  • Reference numeral 81 represents a buried oxide
  • reference numeral 82 represents a handle Si wafer.
  • the NMOS (N12, N22, N32, N42) includes an N + -type source and drain 118, and the PMOS (P12, P22) includes a P + -type source and drain 116.
  • Each SGT SRAM device is connected by the self-aligned salicide 120 and the metal line 152 to form the SGT CMOS SRAM shown in FIG. Dielectrics 130 and 136 separate conductors.
  • FIG. 9A shows an SGT SRAM device structure (SRAM 15 in FIG. 6) of the second example of the first embodiment.
  • FIG. 9A is a circuit diagram of the SRAM formed on the (100) plane of the Si wafer and a plan view of the device.
  • the SRAM of this embodiment has two cylindrical access NMOSs (N11, N21), two square load PMOSs (P11, P21) whose rectangular sidewalls are all (100) planes, and all four sidewalls ( 100) plane square drive NMOSs (N31, N41).
  • FIGS. 9B to 9E show the completed 6T SGT CMOS taken along lines AA ′, BB ′, CC ′, and DD ′ in FIG. 9A. It is a longitudinal cross-sectional view of an SRAM device.
  • the Si pillars of NMOS (N 11, N 21, N 31, N 41) and Si pillars of PMOS (P 11, P 21) are formed on the SOI wafer and are surrounded by the gate oxide film 231 and the conductor 232.
  • Reference numeral 181 denotes a buried oxide film
  • reference numeral 182 denotes a handle Si wafer.
  • the NMOS (N11, N21, N31, N41) includes an N + type source and drain 218, and the PMOS (P11, P21) includes a P + type source and drain 116.
  • Each SGT SRAM device is connected by the self-aligned salicide 220 and the metal line 252 to form the SGT CMOS SRAM shown in FIG.
  • the dielectrics 236 and 230 separate the conductors.
  • FIG. 10A shows an SGT SRAM device structure (SRAM 14 in FIG. 6) of the third example of the first embodiment.
  • FIG. 10A is a circuit diagram of the SRAM formed on the (100) surface of the Si wafer and a plan view of the device.
  • the SRAM of this embodiment has two cylindrical access NMOSs (N10, N20), two cylindrical load PMOSs (P10, P20), and two square drive NMOSs (N30, N40, all four sidewalls of a rectangular pillar). (100) plane).
  • FIGS. 10B to 10E show the completed 6T SGT CMOS taken along lines AA ′, BB ′, CC ′, and DD ′ in FIG. 10A. It is a longitudinal cross-sectional view of an SRAM device.
  • the Si pillar of NMOS (N10, N20, N30, N40) and the Si pillar of PMOS (P10, P20) are formed on the SOI wafer and surrounded by a gate oxide film 331 and a conductor 332.
  • Reference numeral 281 denotes a buried oxide film
  • reference numeral 282 denotes a handle Si wafer.
  • the NMOS (N10, N20, N30, N40) includes an N + -type source and drain 318
  • the PMOS (P10, P20) includes a P + -type source and drain 316.
  • Each SGT SRAM device is connected by the self-aligned salicide 320 and the metal line 352, and the SGT CMOS SRAM shown in FIG. 10A is formed. Dielectrics 336 and 330 separate conductors.
  • FIG. 11A is a circuit diagram of the SRAM circuit of the second embodiment and a plan view of the completed SGT SRAM device.
  • four pillars of driving transistors N33, N43, N53, N63
  • two pillars of NMOS N13 and N23
  • load PMOS P13, P23
  • the plane orientation of the wafer those widely used in this field such as Si (100), Si (110), and Si (111) can be used.
  • various types of Si pillar shapes such as a columnar shape, a square shape, a rectangular shape, and the corresponding plane orientation of the side wall can be used.
  • FIG. 6 is a longitudinal sectional view of a 6T SGT CMOS SRAM device.
  • Si pillars of NMOS (N13, N23, N33, N43, N53, N63) and Si pillars of PMOS (P13, P23) are formed on the SOI wafer and surrounded by a gate oxide film 431 and a conductor 432.
  • Reference numeral 381 denotes a buried oxide film
  • reference numeral 382 denotes a processed Si wafer.
  • the NMOS (N13, N23, N33, N43, N53, N63) includes an N + type source and drain 418
  • the PMOS (P13, P23) includes a P + type source and drain 416.
  • the respective SGT SRAM devices are connected by the self-aligned salicide 420 and the metal line 452 to form the SGT CMOS SRAM device shown in FIG. Dielectrics 436 and 430 separate conductors.
  • the SRAM cell according to the second embodiment of the present invention has a structure using parallel drive transistors instead of the drive transistors of the 6T6 SRAM cell shown in FIG.
  • SGT since the pillar is fixed at the Si pillar diameter, the channel width is generally fixed.
  • the effective channel width is twice that of a driving transistor formed by one pillar. Therefore, the total element resistance of the two drive transistors of this embodiment is half that of the access gate transistor having one transistor. Therefore, the beta ratio is 2, and a high SNM is obtained.
  • the ratio of the number of drive transistors is 2, and two drive transistors are arranged for each access transistor.
  • this ratio is not limited to 2 and can be, for example, 3, 4 or greater.
  • Embodiment 2 of the present invention can be combined with Embodiment 1.
  • four drive transistors N34, N44, N54, N64, all four sidewalls of the pillar are on the (110) plane
  • two access NMOSs P14 and P24, four pillars, four
  • All side walls are (110) planes
  • two load PMOSs P14 and P24, all four side walls of pillars are (100) planes
  • FIGS. 12B to 12F are completed views taken along lines AA ′, BB ′, CC ′, DD ′, and EE ′ of FIG. 12A. It is a longitudinal cross-sectional view of a later 6T SGT CMOS SRAM device.
  • the Si pillar of NMOS (N14, N24, N34, N44, N54, N64) and the Si pillar of PMOS (P14, P24) are formed on the SOI wafer and surrounded by the gate oxide film 531 and the conductor 532.
  • Reference numeral 481 denotes a buried oxide film
  • reference numeral 482 denotes a handle Si wafer.
  • the NMOS (N14, N24, N34, N44, N54, N64) includes an N + -type source and drain 518
  • the PMOS (P14, P24) includes a P + -type source and drain 516.
  • Each SGT SRAM device is connected by the self-aligned salicide 520 and the metal line 552 to form the SGT CMOS SRAM shown in FIG. Dielectrics 536 and 530 separate conductors.
  • FIG. 13 shows a flowchart of a preferred method 10 according to the present invention for forming the actual device structure of an SGT SRAM.
  • FIGS. 14 to 23 are diagrams showing the steps in time series according to the method of FIG. 13. In each figure, the top is a plan view, and the bottom is a view taken along line AA ′ in the plan view. It is a longitudinal cross-sectional view.
  • the procedure for forming SGTSGSRAM by the method 100 of the present invention is as follows. First, a substrate having a first crystal orientation is prepared. This is to make it possible to use a predetermined crystal plane as a channel thereafter.
  • the first step 102 of the method 100 has a first crystal orientation, such as a ⁇ 110 ⁇ plane or ⁇ 100 ⁇ plane, that allows subsequent use of the crystal plane for, for example, a channel of the FET.
  • any combination of n-channel access SGT (NFET), n-channel drive SGT (NFET), and p-channel load SGT (PFET) can be used, for example, ⁇ 100 ⁇ , ⁇ 110 ⁇ , It can be produced by any combination in which a surface having an orientation of ⁇ 111 ⁇ is a side wall.
  • the electron mobility of the access FET is optimized by using the ⁇ 110 ⁇ plane as a side wall in the square SGT formed on the (100) plane of the Si wafer, and the electron mobility of the drive NFET is (
  • the square SGT formed on the (100) plane is optimized by using the ⁇ 100 ⁇ plane as a side wall.
  • the electron mobility of the access NFET can be determined by various planes of the square SGT formed on the (100) plane of the Si wafer (for example, ⁇ 111 ⁇ , ⁇ 510 ⁇ , ⁇ 310 ⁇ , ⁇ 210 ⁇ , ⁇ 320 ⁇ , etc.)
  • the electron mobility of the drive NFET is optimized by using the ⁇ 100 ⁇ face of the square SGT formed on the (100) face of the Si wafer as the sidewall.
  • the electron mobility of the access NFET on the (100) surface of the Si wafer is reduced by adjusting the SNM between the write and read operations utilizing the various surfaces of the columnar SGT.
  • FIG. 14 showing an embodiment of the substrate.
  • This substrate is an SOI wafer, but can also be a single crystal bulk Si wafer.
  • the SOI wafer shown in FIG. 14 includes an upper Si layer 114, a buried oxide film layer 81, and a handle wafer 82.
  • the process in the case of using a bulk wafer is almost the same as the process of an SOI wafer except for a small difference such as a separation membrane.
  • the wafer 114 is shown to be of minimal complexity, but various wafers with different roughness can also be used.
  • III / V compounds such as Si, Ge, GaP, InAs, InP, and GaAs
  • any suitable semiconductor material can be used for the wafer.
  • the wafer has a first crystal plane on which a plane for the FET channel is formed.
  • the upper Si layer of the SOI can be single crystal silicon and the plane orientation can be ⁇ 100 ⁇ .
  • the semiconductor layer 114 is anisotropically etched using the hard mask film 121 to form the separation film and the Si pillar 128.
  • pillars are formed from the SOI wafer 104 by the following method.
  • the hard mask film 113 is patterned.
  • the hard mask film 113 (Si 3 N 4 or SiO 2 ) serves as an etching stop layer.
  • the semiconductor 114 is anisotropically etched using the hard mask film 113, thereby forming the Si pillar 128.
  • RIE reactive ion etching
  • the sidewall can be made to a specific crystal plane, thereby improving the SNM of the SRAM and balancing read and write stability to suit the application.
  • a suitable or desired SNM can be obtained.
  • the side wall of the pillar main body is a crystal plane that can obtain different carrier mobility so that at least one of the first, second, and third crystal planes is not equivalent to the other two crystal planes by symmetrical transformation. be able to.
  • the side wall of the pillar body can be a first specific surface
  • the side wall of the pillar body can be a second specific surface
  • the side wall of the pillar body is a third specific surface. be able to.
  • the pillar can be doped as needed.
  • ion implantation is generally used, whereby a P well structure and an N well structure can be formed in the pillar.
  • the doping level of the P well and the N well is in the range of 10 17 cm ⁇ 3 to 5 ⁇ 10 18 cm ⁇ 3 .
  • NFETs and PFETs can be formed without using a unique Si wafer to create a well structure.
  • an intrinsic Si wafer is used as an example so that a large number of NFETs and a large number of PFETs can be integrated on a common substrate.
  • 16 and 17 show a method of doping the S / D region (source region and drain region).
  • conventional spacer formation ie, uniform RIE etching
  • the Si pillar is covered with a dielectric 119, and then an NMO SS / D region 118 is formed by implanting a dopant into the NMOS semiconductor region 117. Further, an acceptor is injected into the PMOS semiconductor region 125 to form a PMOS S / D 116.
  • the amounts and distribution of acceptors and dopants are determined according to design needs.
  • Various methods for forming the S / D region have been developed. In this embodiment, an appropriate method may be selected from these methods and adjusted for specific performance requirements.
  • the S / D region can be formed from among these using, for example, ion implantation.
  • ion implantation for example, doses in the range of 5 ⁇ 10 14 to 2 ⁇ 10 15 cm ⁇ 3 with energy in the range of 1 keV to 5 keV for P, As, or Sb can be used.
  • a dose in the range of 5 ⁇ 10 14 to 2 ⁇ 10 15 cm ⁇ 3 with energy in the range of 0.5 keV to 3 keV can be used for B, In, or Ga.
  • FIG. 18 illustrates a method of forming S / D silicide (self-aligned salicide) contacts 120 in both NMOS and PMOS device regions.
  • Examples of currently used silicides with low resistance and low contact resistance are TiSi 2 , CoSi 2 , and NiSi.
  • the gate insulating film 131 is formed, but before that, the planar nitride layer (or oxide layer) 130 is made lower than the height of the Si pillar using CMP and a subsequent etch-back process. Form. The purpose of this process is to reduce the parasitic resistance at the overlap between the gate and the lower drain. Therefore, in step 106, the gate insulating film 131 is formed on the Si pillar 128.
  • the gate insulating film 131 can be formed by thermal oxidation at a temperature of 750 ° C. to 800 ° C. or by depositing a dielectric thin film.
  • a well-known SiO 2 , nitrided oxide material, high-K dielectric material, or a combination thereof can be used.
  • a gate conductor is formed.
  • the gate conductor layer 132 is deposited using known photolithography and etching.
  • a polycrystalline silicon material is generally used to form the gate conductor layer 132, but any suitable material such as amorphous silicon, a combination of amorphous silicon and polysilicon, or polysilicon-germanium may be used. it can.
  • a metal gate conductor 132 using a refractory metal such as W, Mo, Ta, or a silicide gate conductor containing polysilicon added with Ni or Co can be used.
  • step 108 if the gate conductor layer 132 surrounds the silicon material, such a layer can be deposited as a doped layer (in situ doping).
  • a doped layer in situ doping.
  • the gate conductor layer 132 is a metal layer, physical vapor deposition or chemical vapor deposition, or any method known in the art can be used. In this manner, the gate structure is formed so as to be in contact with the oxide layer 131 and to face the vertical side wall of the pillar 128.
  • an oxide layer 134 having a sufficient thickness is deposited and polished by CMP until the oxide layer 134 reaches the metal layer 132 as shown in FIG.
  • the gate conductor layer is patterned by etching the exposed gate conductor layer using plasma etching (FIG. 22).
  • a sufficiently thick oxide layer 136 is deposited to provide subsequent contact holes in the final step. Then, as shown in FIG. 24, by connecting each SRAM transistor through the contact hole according to step 110 of the method 100, the SGT SRAM of this embodiment is completed.
  • FIG. 2 is a diagram showing a prior art of a 6T SGT CMOS SRAM layout formed by two drive transistors, two access transistors, and two load transistors, each transistor consisting of a single SGT pillar.
  • FIG. 2 shows the conventional technology of FINFET CMOS SRAM, which is composed of four drive transistors (DR1, DR2, DR3, DR4), two access fin transistors (TR1, TR2), and two load transistors (LO1, LO2). It is a figure which shows a SRAM layout and an equivalent circuit.
  • FIG. 1 shows a SRAM layout and an equivalent circuit.
  • FIG. 4 illustrates the prior art of a FINFET CMOS SRAM, where the drive transistors (NPD, NPD 2 ) are accessed from the access (Access, Access 2 ) and load transistors (Load, Load 2 ) to 45 to utilize different gains caused by different crystal planes.
  • FIG. 6 shows a rotated 6T FINFET SRAM layout and equivalent circuit. A 6T FINFET SRAM cell having two drive transistors (N102, N103), two access fin transistors (N100, N101), and two load transistors (P100, P101) is shown. It is a table
  • the SGT shows a different beta ratio only by rotating the angle between the drive NMOS transistor and the access transistor, where the beta ratio and the square access transistor square drive transistor (all sidewalls are (100)) shows the relationship with the rotation angle.
  • the first implementation of the invention wherein the drive transistors (N32, N42) are rotated 45 ° from the access transistors (N12, N22) and the load transistors (P12, P22) so as to have different gains due to different crystal planes.
  • FIG. 9 is a longitudinal sectional view of a completed CMOS SGT device taken along line A-A ′ of FIG.
  • FIG. 9 is a longitudinal cross-sectional view of the completed CMOS SGT device taken along line B-B ′ of FIG.
  • FIG. 9 is a longitudinal cross-sectional view of the completed CMOS SGT device taken along line C-C ′ of FIG.
  • FIG. 9 is a longitudinal cross-sectional view of the completed CMOS SGT device taken along line C-C ′ of FIG.
  • FIG. 9 is a longitudinal cross-sectional view of the completed CMOS SGT device taken along line D-D ′ in FIG.
  • FIG. 4 is a diagram showing an SGT ⁇ ⁇ CMOS SRAM layout and an equivalent circuit diagram manufactured on a Si (100) wafer formed by transistors (N11, N21) and two square load transistors (P11, P21).
  • FIG. 10 is a longitudinal sectional view of the completed CMOS SGT device taken along line A-A ′ of FIG. 9 (a).
  • FIG. 10 is a longitudinal sectional view of the completed CMOS SGT device taken along line B-B ′ of FIG.
  • FIG. 10 is a longitudinal sectional view of the completed CMOS SGT device taken along line C-C ′ of FIG.
  • FIG. 10 is a longitudinal sectional view of the completed CMOS SGT device taken along line D-D ′ of FIG. 9 (a).
  • Si (100) formed of two circular drive transistors (N30, N40), two circular access transistors (N10, N20), and two circular load transistors (P10, P20) according to the first embodiment of the present invention It is a figure which shows the SGT (CMOS) SRAM layout and equivalent circuit which were manufactured on the wafer.
  • FIG. 10 is a longitudinal sectional view of the completed CMOS SGT device taken along line B-B ′ of FIG.
  • FIG. 10 is a longitudinal sectional view of the completed CMOS SGT device taken along line C-C ′ of FIG.
  • FIG. 10 is a longitudinal section
  • FIG. 11 is a longitudinal sectional view of the completed CMOS SGT device taken along line A-A ′ of FIG. 10 (a).
  • FIG. 11 is a longitudinal sectional view of the completed CMOS SGT device taken along line B-B ′ of FIG.
  • FIG. 11 is a longitudinal sectional view of the completed CMOS SGT device taken along line C-C ′ of FIG.
  • FIG. 11 is a longitudinal sectional view of the completed CMOS SGT device taken along line D-D ′ in FIG.
  • FIG. 12 is a longitudinal sectional view of a completed CMOS SGT device taken along line A-A ′ of FIG.
  • FIG. 12 is a longitudinal sectional view of the completed CMOS SGT device taken along line B-B ′ of FIG.
  • FIG. 12 is a longitudinal sectional view of the completed CMOS SGT device taken along line C-C ′ of FIG.
  • FIG. 12 is a longitudinal sectional view of the SGT (CMOS) SRAM layout and equivalent circuit which were manufactured on Si (100) wafer.
  • FIG. 12 is a longitudinal sectional view of a completed CMOS SGT device taken along line A-A ′ of FIG.
  • FIG. 12 is a longitudinal sectional view of the completed CMOS SGT device taken along line B-B ′ of FIG.
  • FIG. 12 is a longitudinal sectional view of the completed CMOS SGT device taken along line C-C ′ of FIG.
  • FIG. 12 is a longitudinal sectional view of the completed CMOS SGT device taken along line D-D ′ in FIG.
  • FIG. 12 is a longitudinal sectional view of the completed CMOS SGT device taken along line E-E ′ of FIG.
  • the drive transistor (N34, N44, N54, N64) is rotated 45 ° from the access transistor (N12, N22) and the load transistor (P12, P22) to take advantage of different gains caused by different crystal planes.
  • FIG. 13 is a longitudinal sectional view of the completed CMOS SGT device taken along line A-A ′ of FIG.
  • FIG. 13 is a longitudinal sectional view of the completed CMOS SGT device taken along line B-B ′ in FIG.
  • FIG. 13 is a longitudinal sectional view of the completed CMOS SGT device taken along line C-C ′ of FIG.
  • FIG. 13 is a longitudinal sectional view of the completed CMOS SGT device taken along line C-C ′ of FIG.
  • FIG. 13 is a longitudinal sectional view of the completed CMOS SGT device taken along line D-D ′ in FIG.
  • FIG. 13 is a longitudinal sectional view of the completed CMOS SGT device taken along line E-E ′ of FIG. 12 (a).
  • FIG. 14 is a plan view and corresponding longitudinal section of an embodiment of the semiconductor structure of the present invention during the manufacturing method of FIG. 13 with the longitudinal section taken along line A-A ′ of the plan view.
  • FIG. 14 is a plan view and corresponding longitudinal section of an embodiment of the semiconductor structure of the present invention during the manufacturing method of FIG. 13 with the longitudinal section taken along line A-A ′ of the plan view.
  • FIG. 14 is a plan view and corresponding longitudinal section of an embodiment of the semiconductor structure of the present invention during the manufacturing method of FIG. 13 with the longitudinal section taken along line A-A ′ of the plan view.
  • FIG. 14 is a plan view and corresponding longitudinal section of an embodiment of the semiconductor structure of the present invention during the manufacturing method of FIG. 13 with
  • FIG. 14 is a plan view and corresponding longitudinal section of an embodiment of the semiconductor structure of the present invention during the manufacturing method of FIG. 13 with the longitudinal section taken along line A-A ′ of the plan view.
  • FIG. 14 is a plan view and corresponding longitudinal section of an embodiment of the semiconductor structure of the present invention during the manufacturing method of FIG. 13 with the longitudinal section taken along line A-A ′ of the plan view.
  • FIG. 14 is a plan view and corresponding longitudinal section of an embodiment of the semiconductor structure of the present invention during the manufacturing method of FIG. 13 with the longitudinal section taken along line A-A ′ of the plan view.
  • FIG. 14 is a plan view and corresponding longitudinal section of an embodiment of the semiconductor structure of the present invention during the manufacturing method of FIG. 13 with the longitudinal section taken along line A-A ′ of the plan view.
  • FIG. 14 is a plan view and corresponding longitudinal section of an embodiment of the semiconductor structure of the present invention during the manufacturing method of FIG.
  • FIG. 14 is a plan view and corresponding longitudinal section of an embodiment of the semiconductor structure of the present invention during the manufacturing method of FIG. 13 with the longitudinal section taken along line A-A ′ of the plan view.
  • FIG. 14 is a plan view and corresponding longitudinal section of an embodiment of the semiconductor structure of the present invention during the manufacturing method of FIG. 13 with the longitudinal section taken along line A-A ′ of the plan view.
  • FIG. 14 is a plan view and corresponding longitudinal section of an embodiment of the semiconductor structure of the present invention during the manufacturing method of FIG. 13 with the longitudinal section taken along line A-A ′ of the plan view.
  • FIG. 14 is a plan view and corresponding longitudinal section of an embodiment of the semiconductor structure of the present invention during the manufacturing method of FIG. 13 with the longitudinal section taken along line A-A ′ of the plan view.
  • FIG. 14 is a plan view and corresponding longitudinal section of an embodiment of the semiconductor structure of the present invention during the manufacturing method of FIG. 13 with the longitudinal section taken along line A-A ′ of the plan view.
  • FIG. 14 is a circuit diagram and a plan view of a semiconductor structure formed by the manufacturing method of FIG. 13. It is sectional drawing of the semiconductor structure formed by the manufacturing method of FIG.

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Abstract

Cette invention se rapporte à une structure de dispositif d'une cellule SRAM CMOS SGT 6T qui présente un SNM suffisamment élevé et à son procédé de fabrication. Un dispositif SGT comprend un dispositif NMOS d'accès qui utilise une surface de paroi latérale en tant que premier plan cristallin de manière à fournir une première mobilité de porteurs, un dispositif NMOS de rappel vers le niveau bas utilise une surface de paroi latérale en tant que deuxième plan cristallin de manière à fournir une deuxième mobilité de porteurs, et un dispositif PMOS de rappel vers le niveau haut qui utilise une surface de paroi latérale en tant que troisième plan cristallin de manière à fournir une troisième mobilité de porteurs, et l'un au moins des premier, deuxième et troisième plans cristallins, diffère des deux autres plans cristallins. Cette constitution est formée à partir de transistors SGT qui présentent un gain relativement faible et un plan à mobilité de porteurs faible, et des transistors SGT qui présentent un gain relativement élevé et un plan à mobilité de porteurs élevée. Le SGT qui présente le plan à mobilité élevée présente un gain plus élevé que le SGT qui présente le plan à mobilité faible.
PCT/JP2008/056682 2008-04-03 2008-04-03 Procédé et dispositif destinés à améliorer la stabilité d'une cellule sram cmos sgt 6t Ceased WO2009122579A1 (fr)

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TW098110603A TW200947676A (en) 2008-04-03 2009-03-31 Method and device for improving stability of 6T SGT CMOS SRAM cell
PCT/JP2009/056949 WO2009123306A1 (fr) 2008-04-03 2009-04-03 Procédé et dispositif destinés à améliorer la stabilité d'une cellule sram cmos sgt 6t

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JP2011216657A (ja) * 2010-03-31 2011-10-27 Unisantis Electronics Japan Ltd 半導体装置
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JP2014140053A (ja) * 2014-02-27 2014-07-31 Unisantis Electronics Singapore Pte Ltd 半導体装置
JP2017526157A (ja) * 2014-06-23 2017-09-07 インテル・コーポレーション 縦型トランジスタアーキテクチャを形成するための技術

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