WO2009138545A1 - Circuit intégré permettant la lecture numérique de capteurs d'image à haute vitesse - Google Patents

Circuit intégré permettant la lecture numérique de capteurs d'image à haute vitesse Download PDF

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Publication number
WO2009138545A1
WO2009138545A1 PCT/ES2009/070157 ES2009070157W WO2009138545A1 WO 2009138545 A1 WO2009138545 A1 WO 2009138545A1 ES 2009070157 W ES2009070157 W ES 2009070157W WO 2009138545 A1 WO2009138545 A1 WO 2009138545A1
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Prior art keywords
digital
pdm
modulator
integrated circuit
cds
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Ceased
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PCT/ES2009/070157
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English (en)
Spanish (es)
Inventor
Francisco Serra Graells
Josep Mª MARGARIT TAULÉ
Lluis TERÉS TERÉS
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Consejo Superior de Investigaciones Cientificas CSIC
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Consejo Superior de Investigaciones Cientificas CSIC
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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
    • H03M3/326—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors
    • H03M3/338—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors by permutation in the time domain, e.g. dynamic element matching
    • H03M3/342—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors by permutation in the time domain, e.g. dynamic element matching by double sampling, e.g. correlated double sampling
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/94—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the way in which the control signals are generated
    • H03K17/941—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the way in which the control signals are generated using an optical detector
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
    • H04N3/155—
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M3/43—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a single bit one
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/436—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type
    • H03M3/456—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a first order loop filter in the feedforward path

Definitions

  • the present invention relates to the sectors of information technology and communications, and describes a specific microelectronic device for digital capture of static or dynamic images. Said images are broken down into pixels, whose individual value is obtained from the reading of a monolithic or hybrid optical sensor. The matrix grouping of these sensors constitutes the focal plane of the image to be captured. Taking into account the current state of the art, the present invention has the advantage of allowing the resolution to be maintained in the face of a higher image capture rate or alternatively reducing the power consumption in the active pixels.
  • FPA focal plane arrays
  • APS Active Pixel Sensor
  • the ADC architectures most currently adopted for DPS cells are predictive, compared to direct alternatives (eg parallel) and algorithmic (eg successive approximations), since they allow simplifying the parts ADC analog.
  • the complete or partially included processing chain within each DPS is shown in Figure 1. Its basic principle of operation is as follows: the optical sensor (1) generates a current l sens (2) proportional to the power of the incident lighting (3) and its response function; the current level (2) is converted to discrete digital output b ou t (4), in amplitude and time, by the predictive ADC block (5).
  • Said ADC (5) consists of two stages in cascade: a PDM modulator, Pulse Density Modulation, (6) and a digital filter (11).
  • the first stage (6) is responsible for discretizing the amplitude to 1 bit in the form of a pulse train Vpdm (7);
  • the main parts of this modulator (6) are a low frequency gain block (8), a quantizer (9) and a digital-to-analog converter (DAC) (10) that supplies the necessary feedback for the prediction.
  • the quantification error power resulting from said modulation is mainly concentrated in the high frequency components of Vp dm (7), whereby a low-pass digital filtering is then applied in the second stage (11), which also completes the discretization in time.
  • the modulator (6) is usually implemented by asynchronous design techniques, whether they are of the "time to first spike" type [US5565915, 1996-10-15, Matsushita Electric Industrial Co; US6271785, 2001-09-07, Texas Instruments Inc; US6377303, 2002-04-23, Intel Corp; US6525304, 2003-02-25, Foveon Inc; US6559788, 2003-05-06; US6969879, 2005-11-29, STMicroelectronics Ltd; US7071982, 2006-07-04, Texas Instruments Inc; US7164114, 2007-01-16, Via Technologies Inc], or of type "event counting” (spike counting) [US7095439, 2006-09-22, Motorola Inc].
  • the advantage of the second strategy is the low activity of digital switching during analog-digital conversion, with the consequent reduction of electronic noise.
  • the circuit topology commonly used for PDM modulators (6) for counting events and also for digital filtering (11) are shown in Figure 2.
  • modulator compact event count (200) PDM reduces to an integrator implemented by capacitive transimpedance amplifier (amplifier Translmpedance capacitive CTIA) (201) capable of integration Cj n t (202 ), which functions as a low frequency gain block (8) and polarizes the optical sensor (1) to a reference V re f (203); a comparator (204), which functions as a quantifier (9) with respect to a threshold V th (205); and a feedback of the pulse train V P dm (7) towards the initialization (206) of the CTIA (201), which performs the functions of DAC (10).
  • capacitive transimpedance amplifier amplifier Translmpedance capacitive CTIA
  • the CTIA (201) also by the same mechanism previously initialized to the phase of analog-digital conversion by the signal Vf n t 's (207) and ( 206).
  • AACC (201) is particularly suitable for cells DPS high speed requiring low values of C n t (202), as to compensate high values of parasitic input capacitance C pa r (208), whether due to the optical sensor itself (1), to the CTIA (201), or to the monolithic or hybrid interconnection between the two.
  • the PDM modulator (200) can also incorporate a second capacity C C ds (209) controlled by the same signal V P d m (7) through the key (210), and intended to cancel by CDS (Correlated Double Sampling) the low frequency noise AACC (201) in the integrated Vj nt (211) signal.
  • C C ds controlled by the same signal V P d m (7) through the key (210), and intended to cancel by CDS (Correlated Double Sampling) the low frequency noise AACC (201) in the integrated Vj nt (211) signal.
  • the digital filter (11) its performance is reduced to a low pass first order filter implemented by a digital counter (212), which functions as integrator and a reset input (213) controlled by Vf n ⁇ T (207), which implements the losses in said integrator.
  • a pulse (303) pdm signal V (7) causing Ia CTIA initialization (201) and the return of the signal integrated Vf n t (211) to the resting level V occurs in re Ia f (203) to start the cycle again.
  • the power limitations in the different blocks of the PDM modulator (200) cause a non-zero duration T res (307) of the pulses (308) in V pdm (7).
  • the real evolution (305) of the signal integrated V ⁇ n t (211) has a periodicity Tp dm reai (309) greater than the ideal Tp dm ideai (304), causing a loss of pulses in the signal V pdm (7) (eg 1 pulse in Figure 3) at the output of the PDM modulator (200).
  • This loss is especially evident in high-speed DPS cells, in which the ideal periodicity of the Tpcjmideai (304) pulses is short and comparable at the same time T res (307).
  • Said analog-digital conversion curve (401) is calculated for different values of current consumption lb ⁇ as (400) in each block of the PDM modulator (200), equivalent to setting different values of T res (307).
  • the power available in the circuits of the DPS cell is limited by lowering the b ( as ) (400), the consequent increase in T res (307) rapidly accentuates the loss of pulses in the signal V P d m (7).
  • the integrated circuit presented in this report of the invention tries to solve this unwanted effect of non-linearity and saturation of the output signal by means of a compact PDM modulator topology of event counting that does not require a high power consumption in its circuits, especially for high-speed DPS cells for data acquisition (images).
  • the present invention also seeks to overcome the limitations that circuits currently have on the market and for this purpose a new PDM modulator topology is introduced, especially indicated to avoid the loss of pulses due to the initialization time of the CTIA block. This topology facilitates the reduction of the power dissipated in each active pixel or alternatively allows to increase the image capture speed.
  • Speed object of the present invention is characterized by comprising an optical sensor (1), and a predictive ADC (5) completely or partially within the DPS cell.
  • Said ADC (5) is composed, according to Figure 5, by a new PDM event counting modulator (500), which performs the initialization of the
  • CTIA (501) and the reduction of noise by the injection CDS controlled load Ia integration capacity Cj n t (502); as well as by a digital counter (212), for the low-pass filtering of the quantization noise of the PDM modulator (500).
  • the new PDM event count modulator block (500) uses a specific capacity C r eset / cds (503) that allows the integration of the sensor current l se ns (2) during the initialization of the CTIA itself (501). Likewise, the capacity C reS et / cds (503) is also used to sample the low output noise of the CTIA (501) and perform its pre-compensation during the generation of each pulse in Vp dm (7).
  • the invention allows maintaining the linearity of the ADC (5) even for CTIA initialization time values (501) close to the period of the Vpdm pulses (7). Consequently, the acquisition speed of the image can be increased for the same dissipated power or, alternatively, reduce the power consumption in the PDM modulator circuits (500) while maintaining the acquisition speed.
  • the Integrated Circuit for the Digital Reading of High Speed Image Sensors object of the present invention is characterized by comprising an optical sensor (1), and a predictive ADC (5), completely or partially within the cell DPS, composed according to Figure 5 by a new PDM event counting modulator (500) and by a digital counter (212).
  • the new compact modulator PDM event count (500) includes: one CTIA (501) capable of integration Cj nt (502), bootable by the switch (504), which functions as a gain block low frequency ( 8); a comparator (204), which functions as a quantifier (9) with respect to a threshold V t h (205); eset capacity C r / cds (503), identical to that of integration Cj nt (502), which functions as a DAC (10) and is connected at one end to the resting level V re f (203) of Ia integrated Vf n t (505), while the other end of the same signal Creset / cds (503) can be alternately connected at the output or Ia noninverting input of CTIA (501) through switches (506) and (507 ), respectively, according to the output V pdm (7) of the PDM modulator itself (500).
  • the operating principle of the new PDM modulator (500) is illustrated in Figure 6, taking into account that the switches of Figure 5 perform the operation indicated in each case for high logic levels of their control signals.
  • Phase analog-digital conversion starts with the opening of Ia key (504) by Vf n t 's (207).
  • the stream l ns (2) generated by the illumination incident (3) in the sensor (1) is allowed can be integrated into Cj nt (502) by CTIA (501) , while the capacity C re set / cds (503) remains connected to the output of the CTIA itself (501) through the switch (506) sampling the value of the integrated signal V ⁇ nt (505).
  • the same CTIA (501) is also responsible for polarizing the sensor (1) to the resting voltage level V ref (203) and compensating the effect of the parasitic input capacity C pa r (208).
  • the evolution of the signal integrated Vf n t (505) at the output of the CTIA (501) describes a negative ramp (601), or as positive sign l ns (2), until the trigger level comparator ( 204) located at a distance V tr , (205), positive or negative according to the sign of l sens (2), with respect to the resting level V re f (203).
  • a pulse (602) is produced in the signal Vp d m (7), causing the opening of the key (506) and the closing of the key (507).
  • C consequent re switching set / cds (503) injects the charge level needed in the capacity Cj n t (502) to cause the return Vf n of the signal t (505) to its quiescent value V re f (203), thus completing initialization Ia CTIA (501).
  • CTIA (501) operates as a continuous integrator in time during the entire conversion window T fra me (305), blocking only C ⁇ n t (502) during the phase prior to said window in order to initialize Ia polarization of the optical sensor (1). Consequently, the real period Tp dm reai (604) of the signal Vp dm (7) coincides with the theoretical period T pdm ⁇ deai (304) under ideal conditions (301), even for comparable initialization times T res (603) with the nominal period T P dm ⁇ deai (304).
  • the digital output reading b ou t (4) in real conditions (600) coincides with the ideal case (301) and is proportional to the Uens current (2) of the optical sensor (1) to be measured according to the expression
  • C r eset / cds Apart from the function of initialization of C n t (502), the capacitance C r eset / cds (503) is also used for the attenuation of low frequency electronic noise of AACC (501) by CDS. Before firing of the comparator (204) occur, C r eset / cds (503) keeps the electronic noise sampled in Vj nt (505) generated by the CTIA (501). During initialization time T res (603), said pre-noise is subtracted from Cj n t (502) towards the next integration cycle, thus implementing the CDS mechanism. Consequently, the noise components of the CTIA (501) are attenuated in a manner inversely proportional to their frequency.
  • the CTIA integrator block (501) is implemented in this case by a single stage inverting amplifier composed of the N-type field effect transistor MOS (N-type MOS Field Effect Transistor, NMOSFET) M1 ( 700) and the current source l b as (701), with the capacity Cj nt integration (502).
  • the resting level V ref (203) is generated locally within the modulator itself through the NMOSFET M2 (702), identical to M1 (700), and the current source lb ⁇ as (703), also identical to lb ⁇ as (701).
  • Both the pre-initialization key (504) and the switching keys (506) and (507) of C reS et / cds (503) are implemented by NMOSFETs of minimum dimensions.
  • NMOSFET M3 (704) with aspect ratio 1 / K with respect to M1 (700), and the current source l b ⁇ as (705), identical to b aces (701) cascaded with a digital inverter (706) complementary MOSFETs compound of minimum dimensions.
  • Fig. 1 The figure shows a general scheme of digital pixel reading, partially or completely included in each DPS cell, as it is currently manufactured (see State of the Art). It shows the existence of: an optical sensor (1), and a predictive ADC (5), formed by a PDM modulator (6) and a digital low-pass output filter (11). Said PDM modulator (6) is composed of: a low frequency gain block (8), a quantifier (9), and a DAC (10) that provides the necessary feedback for the prediction.
  • Fig. 2 The figure shows a compact topology of predictive ADC (5), partially or completely included in each DPS cell, as it is currently manufactured (see State of the Art).
  • Said PDM modulator (200) is composed of: a CTIA integrator (201) with C ⁇ n t (202) integration capability, a second capacity C C ds (209) for noise cancellation by CDS, a comparator (204) and a feedback of the pulse train V pdm (7) towards the initialization (206) of the CTIA (201).
  • Fig. 3 The figure shows the operation of the PDM topology (200) presented in Figure 2, as it is currently manufactured (see State of the Art).
  • Vt n 207
  • integration Vt n t 211
  • Vp dm output Vp dm (7)
  • Fig. 4 The figure shows an example of electrical simulation results for the PDM topology (200) presented in Figure 2.
  • the transfer curve (401) of the predictive ADC (5) in terms of digital word can be seen output b ou t (4) depending on the current l se ns (2), generated in the optical sensor (1), for different values of current consumption Ibias (400) in each block of the PDM modulator (200).
  • Fig. 5 The figure shows the new topology of PDM modulator of high speed event counting (500) proposed in the invention.
  • said modulator PDM (500) comprises: one CTIA (501) capable of integration Cj nt (502) and pre-bootable by means of key (504), a comparator (204), and eset capacity C r / cds (503) connected at one end to the resting level V re f (203) of the integrated Vf n t (505), while the other end of the same Creset / cds signal (503) It can alternatively be connected to the output or to the non-inverting input of the CTIA (501) by means of the keys (506) and (507), respectively, according to the output V P d m (7) of the PDM modulator itself (500).
  • FIG. 6 The figure shows the operation of the new PDM topology (500) proposed in the invention.
  • Ia Ia same temporal evolution of the signal acquisition window V ⁇ n ⁇ t (207), integration Vf n t (211) and output V P dm (7) is seen for both the ideal case (301 ) as for real implementations (600).
  • Fig. 7 The figure shows an example of a compact embodiment of the new PDM topology (500) proposed in the invention. It shows the implementation of the blocks of Figure 5 through MOSFETs (700, 702 and 704), current sources (701, 703 and 705), keys (504, 506 and 507) and logic gates (706).
  • Fig. 8 The figure shows an example of electrical simulation results for the practical realization of the new PDM topology (500) proposed in the invention. It shows the transfer curve (801) of the predictive ADC (5) in terms of digital output word b ou t (4) as a function of the current l sens (2), generated in the optical sensor (1) , for different values of current consumption lb ⁇ as (800) in each current source (701, 703 and 705).

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

La présente invention concerne des circuits intégrés de lecture (Read-Out Integrated Circuit, ROIC) de matrices de capteurs d'image. L'invention propose une nouvelle topologie de modulateur d'impulsions faisant partie d'un convertisseur analogique-numérique pour des pixels actifs numériques, laquelle topologie permet d'atténuer les pertes de signal résultant des durées d'initialisation de l'intégrateur analogique. L'invention permet également de mettre en oeuvre la fonction de suppression de bruit basse fréquence de l'intégrateur analogique grâce à un double échantillonnage corrélé. Comparativement à la technologie actuelle, l'invention présente l'avantage d'augmenter la vitesse de capture de l'image ou, en variante, de réduire la consommation de puissance dans les pixels actifs sans impliquer de perte de résolution.
PCT/ES2009/070157 2008-05-16 2009-05-14 Circuit intégré permettant la lecture numérique de capteurs d'image à haute vitesse Ceased WO2009138545A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
ESP200801428 2008-05-16
ES200801428A ES2328779B1 (es) 2008-05-16 2008-05-16 Circuito integrado para la lectura digital de sensores de imagen de alta velocidad.

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WO2009138545A1 true WO2009138545A1 (fr) 2009-11-19

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013127450A1 (fr) * 2012-02-29 2013-09-06 Sabanci Üniversitesi Droic à modulation d'impulsions en fréquence asynchrone à réinitialisation automatique, à comptage étendu et à bruit de quantification réduit
US20230134892A1 (en) * 2021-11-03 2023-05-04 Teledyne Innovaciones Microelectrónicas, SLU Analogue to digital converter for image sensor readout

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0767042A (ja) * 1993-06-15 1995-03-10 Matsushita Electric Ind Co Ltd 固体撮像素子
US5565915A (en) * 1993-06-15 1996-10-15 Matsushita Electric Industrial Co., Ltd. Solid-state image taking apparatus including photodiode and circuit for converting output signal of the photodiode into signal which varies with time at variation rate depending on intensity of light applied to the photodiode
EP0954167A2 (fr) * 1998-04-29 1999-11-03 Texas Instruments Incorporated Améliorations apportées à des systèmes de traitement d'images
WO2002047377A1 (fr) * 2000-12-07 2002-06-13 Hamamatsu Photonics K.K. Photodetecteur et procede de photodetection

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0767042A (ja) * 1993-06-15 1995-03-10 Matsushita Electric Ind Co Ltd 固体撮像素子
US5565915A (en) * 1993-06-15 1996-10-15 Matsushita Electric Industrial Co., Ltd. Solid-state image taking apparatus including photodiode and circuit for converting output signal of the photodiode into signal which varies with time at variation rate depending on intensity of light applied to the photodiode
EP0954167A2 (fr) * 1998-04-29 1999-11-03 Texas Instruments Incorporated Améliorations apportées à des systèmes de traitement d'images
WO2002047377A1 (fr) * 2000-12-07 2002-06-13 Hamamatsu Photonics K.K. Photodetecteur et procede de photodetection

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013127450A1 (fr) * 2012-02-29 2013-09-06 Sabanci Üniversitesi Droic à modulation d'impulsions en fréquence asynchrone à réinitialisation automatique, à comptage étendu et à bruit de quantification réduit
US9197834B2 (en) 2012-02-29 2015-11-24 Sabanci Üniversitesi Self-reset asynchronous pulse frequency modulated DROIC with extended counting and having reduced quantization noise
US20230134892A1 (en) * 2021-11-03 2023-05-04 Teledyne Innovaciones Microelectrónicas, SLU Analogue to digital converter for image sensor readout
US12289555B2 (en) * 2021-11-03 2025-04-29 Teledyne Innovaciones Microelectrónicas, SLU Analogue to digital converter for image sensor readout

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ES2328779A1 (es) 2009-11-17

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