WO2009144384A1 - Procédé et appareil de pagination de mémoire - Google Patents

Procédé et appareil de pagination de mémoire Download PDF

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Publication number
WO2009144384A1
WO2009144384A1 PCT/FI2009/050461 FI2009050461W WO2009144384A1 WO 2009144384 A1 WO2009144384 A1 WO 2009144384A1 FI 2009050461 W FI2009050461 W FI 2009050461W WO 2009144384 A1 WO2009144384 A1 WO 2009144384A1
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Prior art keywords
cache
page
ram
paging
pages
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Jonathan Medhurst
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Nokia Inc
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Nokia Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/122—Replacement control using replacement algorithms of the least frequently used [LFU] type, e.g. with individual count value
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms

Definitions

  • Embodiments of the present invention relate to a memory paging control method and apparatus.
  • the invention relates to such a method and apparatus for controlling which pages are maintained in a paging cache in the executable memory of a computing device.
  • a method comprising: maintaining a paging cache of memory pages which have been paged into random access memory (RAM) for use by a processor, the paging cache being arranged in at least a first part and a second part, each part being configured to operate on a respective First-In, First- Out (FIFO) basis; loading a new page into RAM, the new page being loaded into the first part of the cache; outputting a page from the first part of the cache into the second part of the cache; and when a page is required which is located in the second part of the cache, removing the required page from the second part of the cache and placing the required page into the first part of the cache.
  • RAM random access memory
  • apparatus comprising: a processor; and a paging cache of memory pages which have been paged into random access memory (RAM), the paging cache being arranged in at least a first part and a second part, each part being configured to operate on a respective First-In, First-Out (FIFO) basis; wherein the processor is configured to cause the apparatus to perform the following:- i) load a new page into RAM, the new page being loaded into the first part of the cache; ii) output a page from the first part of the cache into the second part of the cache; and iii) when a page is required which is located in the second part of the cache, remove the required page from the second part of the cache and place the required page into the first part of the cache.
  • RAM random access memory
  • the invention provides apparatus comprising: processor means; and paging cache means for storing memory pages which have been paged into random access memory (RAM), the paging cache means being arranged in at least a first part and a second part, each part being configured to operate on a respective First-In, First- Out (FIFO) basis; wherein the processor means is configured to cause the apparatus to perform the following:- i) load a new page into RAM, the new page being loaded into the first part of the cache; ii) output a page from the first part of the cache into the second part of the cache; and iii) when a page is required which is located in the second part of the cache, remove the required page from the second part of the cache and place the required page into the first part of the cache.
  • RAM random access memory
  • the processor means may include one or more separate processor cores.
  • the paging cache means may be provided in any suitable type of memory.
  • the invention may include a computer program, a suite of computer programs, a computer readable storage medium, or any software arrangement for implementing the method of the first example. Aspects of the invention may also be carried out in hardware, or in a combination of software and hardware.
  • Figure 1 is a block diagram of a smartphone architecture
  • Figure 2A is a diagram illustrating a memory layout forming background to the invention.
  • Figure 2B is a diagram illustrating a memory layout forming background to the invention
  • Figure 2C is a diagram illustrating a memory layout according to an embodiment of the invention
  • Figure 3 is a diagram illustrating how paged data can be paged into RAM
  • Figure 4 is a diagram illustrating a paging cache
  • Figure 5 is a diagram illustrating how a new page can be added to the paging cache
  • Figure 6 is a diagram illustrating how pages can be aged within a paging cache
  • Figure 7 is a diagram illustrating how aged pages can be rejuvenated in a paging cache
  • Figure 8 is a diagram illustrating how a page can be paged out of the paging cache
  • Figure 9 is a diagram illustrating the RAM savings obtained using demand paging
  • FIG. 1 shows an example of a device that may benefit from embodiments of the present invention.
  • the smartphone 10 comprises hardware to perform the telephony functions, together with an application processor and corresponding support hardware to enable the phone to have other functions which are desired by a smartphone, such as messaging, calendar, word processing functions and the like.
  • the telephony hardware is represented by the RF processor 102 which provides an RF signal to antenna 126 for the transmission of telephony signals, and the receipt therefrom.
  • baseband processor 104 which provides signals to and receives signals from the RF Processor 102.
  • the baseband processor 104 also interacts with a subscriber identity module 106.
  • a display 116 and a keypad 118. These are controlled by an application processor 108, which is often a separate integrated circuit from the baseband processor 104 and RF processor 102.
  • a power and audio controller 120 is provided to supply power from a battery to the telephony subsystem, the application processor, and the other hardware. Additionally, the power and audio controller 120 also controls input from a microphone 122, and audio output via a speaker 124.
  • the application processor 108 In order for the application processor 108 to operate, various different types of memory are often provided. Firstly, the application processor 108 is provided with some Random Access Memory (RAM) 112 into which data and program code can be written and read from at will. Code placed anywhere in RAM can be executed by the application processor 108 from the RAM.
  • RAM Random Access Memory
  • separate user memory 110 which is used to store user data, such as user application programs (typically higher layer application programs which determine the functionality of the device), as well as user data files, and the like.
  • user application programs typically higher layer application programs which determine the functionality of the device
  • user data files and the like.
  • An operating system is the software that manages the sharing of the resources of the device, and provides programmers with an interface to access those resources.
  • An operating system processes system data and user input, and responds by allocating and managing tasks and internal system resources as a service to users and programs on the system. At its most basic, the operating system performs tasks such as controlling and allocating memory, prioritising system requests, controlling input and output devices, facilitating networking, and managing files.
  • An operating system is in essence an interface by which higher level applications can access the hardware of the device.
  • an operating system is provided, which is started when the smartphone system 10 is first switched on.
  • the operating system code is commonly stored in a Read-Only Memory, and in modern devices, the Read-Only Memory is often NAND Flash ROM 114.
  • the ROM will store the necessary operating system component in order for the device 10 to operate, but other software programs may also be stored, such as application programs, and the like, and in particular those application programs which are mandatory to the device, such as, in the case of a smartphone, communications applications and the like. These would typically be the applications which are bundled with the smartphone by the device manufacturer when the phone is first sold. Further applications which are added to the smartphone by the user would usually be stored in the user memory 110.
  • ROM Read-Only Memory
  • ROM Read-Only Memory
  • XIP eXecute-In- Place
  • the ROM situation is further complicated when the underlying media is not XIP. This is the case for NAND flash, used in many modern devices. Here code in NAND is copied (or shadowed) to RAM, where it can be executed in place. One way of achieving this is to copy the entire ROM contents into RAM during system boot and use the Memory Management Unit (MMU) to mark this area of RAM with read-only permissions.
  • MMU Memory Management Unit
  • the data stored by this method is called the Core ROM image (or just Core image) to distinguish it from other data stored in NAND.
  • the Core image is an XIP ROM and is usually the only one; it is permanently resident in RAM.
  • layout A shows how the NAND flash 20 is structured in a simple example. All the ROM contents 22 are permanently resident in RAM and any executables in the user data area 24 (for example the C: or D: drive) are copied into RAM as they are needed.
  • ROFS Read-Only File System
  • ROFS there are several ROFS images, for example localisation and/or operator-specific images.
  • the first one (called the primary ROFS) is combined with the Core image into a single ROM- like interface by what is known as the Composite File System.
  • Layout B in Figure 2 shows a Composite File System structure of another example.
  • ROM 30 is divided into the Core Image 32 comprising those components of the OS which will always be loaded into RAM, and the ROFS 34 containing those components which do not need to be continuously present in RAM, but which can be loaded in and out of RAM as required.
  • components in the ROFS 34 are loaded in and out of RAM as whole components when they are required (in the case of loading in) or not required. Comparing this to layout A, it can be seen that layout B is more RAM-efficient because some of the contents of the ROFS 34 are not copied into RAM at any given time. The more unused files there are in the ROFS 34, the greater the RAM saving.
  • Virtual memory techniques are known in the art, where the combined size of any programs, data and stack exceeds the physical memory available, but programs and data are split up into units called pages.
  • the pages which are required to be executed can be loaded into RAM, with the rest of the pages of the program and data stored in non XIP memory (such as on disk).
  • Demand paging refers to a form of paging where pages are loaded into memory on demand as they are needed, rather than in advance. Demand paging therefore generally relies on page faults occurring to trigger the loading of a page into RAM for execution.
  • An example embodiment of the invention to be described is based upon the smartphone architecture shown in Figure 1, and in particular a smartphone running Symbian OS.
  • Symbian OS the part of the operating system which is responsible overall for loading programs and data from non XIP memory into RAM is the "loader".
  • loader the part of the operating system which is responsible overall for loading programs and data from non XIP memory into RAM.
  • Many further details of the operation of the loader can be found in Sales J. Symbian OS Internals John Wiley & Sons, 2005, and in particular chapter 10 thereof, the entire contents of which are incorporated herein be reference.
  • the operation of the loader is modified to allow demand paging techniques to be used within the framework of Symbian OS.
  • a smartphone having a composite file system as previously described, wherein the CFS provides a Core Image comprising those components of the OS which will always be loaded into RAM, and the ROFS containing those components which do not need to be continuously present in RAM, but which can be loaded in and out of RAM as required.
  • the principles of virtual memory are used on the core image, to allow data and programs to be paged in and out of memory when required or not required. By using virtual memory techniques such as this, then RAM savings can be made, and overall hardware cost of a smartphone reduced.
  • XIP ROM Paging can refer to reading in required segments ("pages") of executable code into RAM as they are required, at a finer granularity than that of the entire executable. Typically, page size may be around 4kB; that is, code can be read in and out of RAM as required in 4kB chunks. A single executable may comprise a large number of pages. Paging is therefore very different from the operation of the ROFS, for example, wherein whole executables are read in and out of RAM as they are required to be run.
  • an XIP ROM image is split into two parts, one containing unpaged data and one containing data paged on demand.
  • the unpaged data is those executables and other data which cannot be split up into pages.
  • the unpaged data consists of kernel-side code plus those parts that should not be paged for other reasons (e.g. performance, robustness, power management, etc).
  • the terms 'locked down' or 'wired' can also be used to mean unpaged.
  • Paged data in this example is those executables and other data which can be split up into pages.
  • the unpaged area at the start of the XIP ROM image is loaded into RAM as normal but the linear address region normally occupied by the paged area is left unmapped - i.e. no RAM is allocated for it in this example.
  • a thread accesses memory in the paged area, it takes a page fault.
  • the page fault handler code in the kernel then allocates a page of RAM and reads the contents for this from the XIP ROM image contained on storage media (e.g. NAND flash).
  • storage media e.g. NAND flash
  • a page is a convenient unit of memory allocation: in this example it is 4kB.
  • the thread then continues execution from the point where it took the page fault. This process is referred to in this example embodiment as 'paging in' and is described in more detail later.
  • a page may contain data from one or more files and page boundaries do not necessarily coincide with file boundaries in the example embodiment.
  • layout C shows an XIP ROM paging structure according to the example embodiment.
  • ROM 40 comprises an unpaged core area 42 containing those components which should not be paged, and a paged core area 44 containing those components which should reside in the core image rather than the ROFS, but which can be paged.
  • ROFS 46 then contains those components which do not need to be in the Core image.
  • the unpaged area of the Core image may be larger than the total Core image in layout B, only a fraction of the contents of the paged area needs to be copied into RAM compared to the amount of loaded ROFS code in layout B.
  • Live Page A page of paged memory whose contents are currently available.
  • Dead Page A page of paged memory whose contents are not currently available.
  • Page Out The act of making a live page into a dead page.
  • the RAM used to store the content of this may then be reused for other purposes.
  • efficient performance of the paging subsystem is dependent on the algorithm that selects which pages are live at any given time, or conversely, which live pages should be made dead.
  • the paging subsystem of this embodiment approximates a Least Recently Used (LRU) algorithm for determining which pages to page out.
  • LRU Least Recently Used
  • the memory management unit 28 (MMU) provided in the example device is a component comprising hardware and software which has overall responsibility for the proper operation of the device memory, and in particular for allowing the application processor to write to or read from the memory.
  • the MMU is part of the paging subsystem of this example embodiment.
  • the paging algorithm according to the present embodiment provides a "live page list".
  • All live pages are stored on the 'live page list', which is a part of the paging cache.
  • FIG 4 shows the live page list.
  • the live page list is split into two sub-lists, one containing young pages (the "young page list” 72) and the other, old pages (the "old page list” 74).
  • the memory management unit (MMU) 58 in the device of this example is used to make all young pages accessible to programs but the old pages inaccessible.
  • Figure 5 shows what happens when a page is "paged in” in this example embodiment. When a page is paged in, it is added to the start of the young list 72 in the live page list, making it the youngest.
  • the paging subsystem of some embodiments attempts to keep the relative sizes of the two lists equal to a value called the young/old ratio. If this ratio is R, the number of young pages is Ny and the number of old pages is No then if (Ny > RNo ) , a page is taken from the end of the young list 72 and placed at the start of the old list 74. This process is called ageing, and is shown in Figure 6.
  • the operating system When the operating system requires more RAM for another purpose then it may obtain the memory used by a live page.
  • the 'oldest' live page is selected for paging out, turning it into a dead page, as shown in Figure 8. If paging out leaves too many young pages, according to the young/old ratio, then the last young page (e.g. Page D in Figure 8) would be aged. In this way, the young/old ratio helps to maintain the stability of the paging algorithm, and ensure that there are always some pages in the old list.
  • the above actions are executed in the context of the thread that tries to access the paged memory.
  • RAM that is being used to store paged memory is freed up for use. This is referred to as 'paging out' and happens by the following process:
  • a purpose of demand paging is to save RAM, but there may also be at least two other potential benefits. These benefits can be dependent on a paging configuration, discussed later.
  • DP demand paging
  • Figure 2, layout B non-DP composite file system case
  • the performance overhead of paging can be outweighed by the performance gain of loading less code into RAM. This is sometimes known as 'lazy loading' of code.
  • non-DP case consists of a large core image (i.e. something closer to Figure 2, layout A)
  • most or all of the code involved in a use-case may already be permanently loaded, and so the performance improvement of lazy loading may be reduced.
  • An exception to this is during boot, where the cost of loading the whole core image into RAM contributes to the overall boot time.
  • a second possible performance improvement lies in improved stability of the device.
  • the stability of a device is often at its weakest in Out Of Memory (OOM) situations. Poorly written code may not cope well with exceptions caused by failed memory allocations. As a minimum, an OOM situation will degrade the user experience.
  • OOM Out Of Memory
  • the RAM saving achieved by DP is proportional to the amount of code loaded in the non-DP case at a particular time. For instance, the RAM saving when 5 applications are running is greater than the saving immediately after boot. This can make it even harder to induce an OOM situation.
  • demand paging can introduce three new configurable parameters to the system. These are:
  • the first two are discussed below.
  • the third should be determined empirically.
  • a number of components are explicitly made unpaged in example embodiments of the invention, to meet the functional and performance requirements of a device.
  • the performance overhead of servicing a page fault is unbounded and variable so it may be desirable to protect some critical code paths by making files unpaged. Chains of files and their dependencies may need to be unpaged to achieve this. It may be possible to reduce the set of unpaged components by breaking unnecessary dependencies and separating critical code paths from non-critical ones.
  • a minimum paging cache size can be defined. If a system memory allocation would cause the paging cache to drop below the minimum size, then the allocation fails.
  • the paging cache grows but any RAM used by the cache above the minimum size does not contribute to the amount of used RAM reported by the system. Although this RAM is really being used, it will be recycled whenever anything else in the system requires the RAM. So the effective RAM usage of the paging cache is determined by its minimum size.
  • the minimum paging cache size relates to a minimum number of pages which should be in the paging cache at any one moment.
  • the pages in the paging cache are divided between the young list and the old list. This is not essential, however, and in other embodiments the paging cache may not be divided, or may be further sub divded into more than two lists. To help prevent thrashing, it is useful to maintain an overall minimum size of the list, and to make the pages therein accessible without having to be re-loaded into memory.
  • the effective RAM saving is the size of all paged components minus the minimum size of the paging cache. Note that when a ROFS section is introduced, this calculation is much more complicated because the contents of the ROFS are likely to be different between the non-DP and DP cases.
  • the RAM saving can be increased by reducing the set of unpaged components and/or reducing the minimum paging cache size (i.e. making the configuration more 'stressed'). Performance can be improved (up to a point) by increasing the set of unpaged components and/or increasing the minimum paging cache size (i.e. making the configuration more 'relaxed'). However, if the configuration is made too relaxed then it is possible to end up with a net RAM increase compared with a non-DP ROM.
  • the techniques of the present invention may be used to provide embodiments with different applications, such as for example, as a general purpose computer, or as a portable media player, or other audio visual device, such as a camera.
  • Any device or machine which incorporates a computing device provided with RAM into which data and programs need to be loaded for execution may benefit from the invention and constitute an embodiment thereof.
  • the invention may therefore be applied in many fields, to provide improved devices or machines that require less RAM to operate than had heretofore been the case.
  • NRU Not Recently Used
  • LRU Least Recently Used
  • FIFO First-In First-Out
  • the FIFO algorithm simply maintains a list of all pages currently in memory, with the page at the head of the list the oldest one and the page at the tail the most recent arrival. On a page fault, the page at the head of the list is removed, and the new page added to the tail of the list. Whilst a FIFO page replacement algorithm is therefore easy to implement, it is rarely used because it makes no account for whether the page that is being removed might actually be required again in the near future. In this respect, if the removed page is required again, then a further page fault will be triggered, and the removed page will have to be re-loaded from storage into RAM.
  • a variation on the FIFO algorithm is the second chance algorithm.
  • each page has a Read flag R, which says whether the pages has been referenced recently (i.e. in the last n clock cycles).
  • R Read flag
  • the pages are maintained in a FIFO cache, but if the oldest page has its flag set such that it has been accessed recently, then when it comes to the head of the list and hence is subject to be removed, instead of being removed it is placed back at the tail of the queue, and hence may work its way back through the FIFO cache.
  • This provides a large performance improvement over the FIFO algorithm, but it is dependent on a page being read as it approaches the end of the queue.
  • a page may be maintained which is not in fact required very often. The problem therefore lies in the fact that the algorithm only looks to give a page a "second chance" as it is about to be deleted from the cache. If that chance is not taken, then the page is lost, and may need to be re-loaded.
  • Another algorithm is the LRU algorithm. Tanenbaum describes the LRU algorithm as "excellent, but difficult to implement”. The LRU algorithm approximates well an optimal page replacement algorithm. In this respect, an optimal page replacement algorithm would remove the page from RAM which is the page which will not be required again until farthest into the future (if at all), thereby putting off another page fault as long as possible.
  • the LRU algorithm is based on the premise that pages which have been heavily used in the last few instructions will probably be heavily used again in the next few (and hence should be retained in RAM). However, pages that have not been used for a long time will probably remain unused for a long time, and hence can be replaced. Therefore, an LRU algorithm operates to try and replace the page that has been unused for the longest time.
  • embodiments of the pagng algorithm of the present invention can be beneficial, since they can offer the benefits of LRU, but be easier to implement with smaller processing overhead.
  • Certain embodiments of the invention may provide a new page replacement algorithm which provides substantially the benefits of an LRU algorithm but with the implementation simplicity of a FIFO arrangement.
  • pages which have been paged into memory are maintained in a paging cache, which is split into at least two parts.
  • each part of the cache is maintained as a separate FIFO, and new pages are loaded into the first part, with pages output from the first part being placed into the second part.
  • essentially the arrangement of these embodiments is no more complex than simply maintaining two FIFO lists.
  • pages are not immediately deleted from the cache when they reach the output of the first part of the cache, they are retained in the second part of the cache, and whilst they are working their way through the second part of the cache they can be re-instated into the input of the first part of the cache whenever required.
  • Such operation approximates a least recently used type algorithm, because whilst in the first part of the cache the page can be used by the processor.
  • the page when the page is relegated to the second part of the cache, if it is needed again whilst in the second part of the cache it can be immediately promoted to the first part of the cache, and will not need to be re-loaded.
  • the page if the page is not required whilst it is resident in the second part of the cache i.e. it is not recently used, then it will eventually be paged out.
  • the second part of the cache therefore provides a buffer which acts to sort out which pages are recently used and which are not.
  • the second part of the cache is inaccessible to the processor, and the movement of the required page from the second part of the cache into the first part of the cache renders the page accessible.
  • the memory controller in charge of the process has to move the required page into the first part of the cache, and hence the page is rejuvenated, and will not be subject to relegation into the second part of the cache until it has worked through the first part of the cache.
  • a page is available in the cache for some time.
  • the relative sizes of the first and second parts of the cache are maintained in accordance with one embodiment of the invention in dependence on a predetermined ratio coefficient R.
  • This provides a mechanism to ensure that the first part of the cache does not become too large, and hence that pages move through the first and second parts of the cache lists in accordance with the control algorithm.
  • a page is removed from the first part of the cache and placed in the second part of the cache if the number of pages in the first part of the cache is greater than the product of the ratio coefficient R and the number of pages in the second part of the cache.
  • a page is removed from the second part of the cache when it is necessary to free RAM for another purpose.
  • a page which has been relegated into the second part of the cache remains in the cache, and the cache simply grows large. This means that if a relegated page is required, it can be simply transferred back into the first part of the cache, and does not need to be re-loaded.
  • the position of the accessed page in the first part of the cache is not altered.
  • the page stays in its same position in the FIFO queue.
  • the reason for this is to avoid too much processing overhead in maintaining the FIFO queue. Whilst in the first part of the cache the page can be accessed - it does not matter where in the FIFO queue the page is located. If the page is required again once it has come to the end of the FIFO queue in the first part of the cache then it can be re-instated to the front of the first part of the cache if it is needed again once it has been relegated. In this way, the only FIFO operations are placing pages at the start of the FIFO queue in the first cache, and no queue re-ordering is required.
  • the paging cache can be maintained at a minimum size. Maintaining the paging cache at a minimum size can help prevent a phenomenon known as "thrashing" where pages are being continually paged out from and re-loaded back into RAM. This is very detrimental to processing efficiency, as re-loading a page takes a substantial amount of time (e.g. a few milliseconds, to reload from disk).
  • Various modifications, including additions and deletions, will be apparent to the skilled person to provide further embodiments, any and all of which are intended to fall within the appended claims. It will be understood that any combinations of the features and examples of the described embodiments of the invention may be made within the scope of the invention.

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Abstract

L'invention concerne un algorithme de remplacement de page qui présente sensiblement des avantages d'un algorithme LRU associés à la simplicité de mise en oeuvre d'un agencement FIFO. En particulier, les pages qui ont été paginées dans une mémoire sont conservées dans une antémémoire de pagination qui est séparée en au moins deux parties. Chaque partie est gérée en tant qu'agencement FIFO séparé, et de nouvelles pages sont chargées dans la première partie, les sorties de pages de la première partie étant placées dans la seconde partie. De ce fait, il n'est sensiblement pas plus complexe de gérer ledit agencement que de gérer deux listes FIFO. Toutefois, pour s'assurer que les pages ne sont pas immédiatement supprimées de l'antémémoire lorsqu'elles atteignent la sortie de la première partie de l'antémémoire, elles sont retenues dans la seconde partie de l'antémémoire, et tandis qu'elles traversent cette dernière elles peuvent être réinstallées dans l'entrée de la première partie de l'antémémoire si nécessaire.
PCT/FI2009/050461 2008-05-30 2009-06-01 Procédé et appareil de pagination de mémoire Ceased WO2009144384A1 (fr)

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GB0809926A GB2460464A (en) 2008-05-30 2008-05-30 Memory paging control method using two cache parts, each maintained using a FIFO algorithm
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Cited By (1)

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WO2022070011A1 (fr) * 2020-09-29 2022-04-07 International Business Machines Corporation Gestion d'une mémoire cache de données la plus récemment utilisée avec un corps persistant

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