WO2010054875A1 - Ensemble d'au moins deux tranches liées par soudage et procédé de fabrication d'un tel ensemble - Google Patents

Ensemble d'au moins deux tranches liées par soudage et procédé de fabrication d'un tel ensemble Download PDF

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Publication number
WO2010054875A1
WO2010054875A1 PCT/EP2009/061832 EP2009061832W WO2010054875A1 WO 2010054875 A1 WO2010054875 A1 WO 2010054875A1 EP 2009061832 W EP2009061832 W EP 2009061832W WO 2010054875 A1 WO2010054875 A1 WO 2010054875A1
Authority
WO
WIPO (PCT)
Prior art keywords
bonding
wafer
bonding material
microns
bond
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2009/061832
Other languages
German (de)
English (en)
Inventor
Axel Franke
Achim Trautmann
Ando Feyh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of WO2010054875A1 publication Critical patent/WO2010054875A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00269—Bonding of solid lids or wafers to the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/60—Seals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • B81C2203/0118—Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • B81C2203/0172—Seals
    • B81C2203/019—Seals characterised by the material or arrangement of seals between parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07336—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/331—Shapes of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/856—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors

Definitions

  • the invention relates to an arrangement of at least two wafers with a
  • Bonding of a first and a second bonding material and a method for producing such an arrangement.
  • bonding compounds can be used. Different methods have been developed for the realization of bond connections. Examples of known bonding methods include eutectic bonding, thermocompression bonding and direct bonding.
  • bonding materials there are several bonding materials available, wherein the bonding materials may be different on the two wafers to be joined.
  • the combinations Au-Si, Al-Ge or Au-Sn are known as bonding materials.
  • a disadvantage of eutectic bonding is that, due to the formation of a liquid phase, bleeding and melting of the bonding material occur. As a result, the layer thickness of the bonding material between the wafers changes, and the setting of a defined distance between the wafers is not possible.
  • the reduction of the layer thickness of the bonding material is associated with an increase in the layer area of the bonding material.
  • additional, targeted countermeasures are required. So For example, as a countermeasure, special structures such as trenches are provided to prevent bleeding of the deliquescent bonding material.
  • thermocompression bonding and direct bonding on the other hand, strict requirements are placed on the surfaces to be joined in their hitherto known embodiment. Thus, only bonding surfaces with very low roughness can be considered in these bonding methods.
  • Wafer known wherein various bonding materials are described as suitable. It is suggested to use gold bondpads. As other materials which are also suitable to be joined together, mention is made of silicon, indium, aluminum, copper, silver, alloys of these and compounds thereof.
  • the inventive arrangement and the inventive method have the advantage that the formation of a reliable and stable bond of two wafers is achieved in a simple manner.
  • This beneficial effect is achieved by a special, specific
  • the invention also makes it possible to realize a bond without noticeable melting, crimping or bleeding of the bonding materials occurring.
  • no liquid phase is formed by the proposed combination of materials (eutectic). Consequently, this makes it possible to obtain a defined, i. to set a controlled distance between the two wafers to be joined.
  • the mechanical and electrical properties of the bond connection can be set to a greater extent than with conventional eutectic connections using the bond parameters bonding pressure, bond temperature and bonding time. Comparable mechanical or electrical properties of the bond to be formed can be realized in various ways. For example, instead of a higher bond temperature, a longer bond time can be selected.
  • the process presented no critical temperature, as otherwise known from eutectic bonding, is present in the process presented.
  • the process can be carried out so that only low temperature loads of up to 400 0 C occur. This ensures a simple process control.
  • the invention also offers the advantage that no special requirements are placed on the roughness of the bonding surfaces. By contrast, in previous methods, for example in direct bonding, a very low roughness of the bonding surfaces is required.
  • the method according to the invention also allows the wafers to be joined to have an anti-adhesion layer, for example an anti-adhesion layer on micromechanical structures.
  • the method is thus compatible with possible non-stick layers.
  • Figure 1 shows an embodiment of the invention before the bonding process of two wafers to be joined together
  • FIG. 2 shows the two wafers from FIG. 1 after the bonding process.
  • the method according to the invention for producing a bond connection between at least two wafers basically comprises the following steps: a) applying a first bonding material on a first wafer, wherein as the first bonding material aluminum or an aluminum alloy is selected, b) applying a second bonding material on a second wafer, wherein gold is selected as the second bonding material, and c) performing a bonding process, the first and the second
  • Bond material are joined together to achieve a wafer-to-wafer bond.
  • Fig. 1 the two wafers 1, 4 are shown, which are to be joined together.
  • the first bonding material 3 has been applied according to step a).
  • aluminum (Al) or an aluminum alloy was selected.
  • aluminum alloy AISi, AICu or AISiCu can be provided.
  • a closed circumferential bonding frame 3a is formed in step a) by the application of the first bonding material 3.
  • the later bond has a self-contained, circumferential shape.
  • an electrical contact pad 3b is formed in step a) by the application of the first bonding material 3.
  • a suitable thickness of the first bonding material 3 is 200 nm to 3 ⁇ m.
  • a wafer 1 with a MEMS (microelectromechanical system) element 2 was selected in step a).
  • a second bonding material 6 is applied to a second wafer 4, wherein the second bonding material 6 is gold (Au). It is provided in this embodiment that the second bonding material 6 is not applied directly to the second wafer 4, but on a bonding surface 7.
  • the bonding surface 7 forms a closed circumferential bonding frame 7a or an electrical contact pad 7b of the second wafer 4. While an interior with a set internal pressure is formed by the closed circumferential bonding frame 7a after a later-to-be-performed bonding operation is generated, the electrical contact pad 7b later serves an electrical chip-to-chip contact.
  • Width values also apply to the bonding frame in the layer region of the second bonding material 6a made of gold and to the bonding frame 3a made of the first bonding material 3 of the first wafer 1.
  • width of the electrical contact pad 7b of the second wafer 4 a size of at most 50 ⁇ m, in particular smaller than 30 ⁇ m, is likewise proposed. These width values also apply to the contact pad in the layer region of the second bonding material 6b made of gold and also to the contact pad 3b made of the first bonding material 3 of the first wafer 1.
  • the material of the bonding surface 7 that is, as the material of the bonding frame 7a or the electric bonding pad 7b on the second wafer 4, it is preferable to select Al (aluminum), AISi, AICu or AISiCu.
  • the second bonding material 6 can also consist of a composition of the materials mentioned as needed. In this case, the bonding frame 7a or the electrical
  • Contact pad 7b has a thickness of 200 nm to 3 ⁇ m.
  • step b) gold can be applied as the second bonding material 6 with a sputtering or electroplating process. Both processes are fundamentally suitable, since both processes are within the framework of the presented
  • the sputter process offers a good opportunity to apply gold, in particular thicker than 2 ⁇ m. However, if gold is to be applied 1-30 ⁇ m thick, this can preferably also be achieved with a galvanic process.
  • the presented method can advantageously be used for versatile application examples with regard to the selection of the two wafers 1, 4 to be connected.
  • the first wafer 1 in step a) may be an ME MS wafer, ie the first wafer 1 comprises at least one MEMS element 2.
  • the second wafer 4 a selection is also possible for the second wafer 4 a selection.
  • the second wafer 4 is a cap wafer.
  • the second wafer 4 can have an ASIC (application-specific integrated circuit) element 5, ie the second wafer 4 is an ASIC wafer.
  • ASIC application-specific integrated circuit
  • FIG. 1 shows the particularly advantageous embodiment, in which the first wafer 1 has a MEMS (microelectromechanical system) element 2 and the second wafer 4 has an ASIC (application-specific integrated circuit) element 5.
  • the second wafer 4 serves as a cap wafer at the same time.
  • a bonding process is carried out, wherein the first 3 and the second bonding material 6 are joined together to achieve a wafer-to-wafer bonding connection.
  • This bond connection does not serve for external contacting of circuits or sensors, but rather an internal wafer-to-wafer connection. Thus, this wafer-to-
  • wafer bonding from a bond of an external wire to a wafer technically.
  • the two wafers 1, 4 can be adjusted and bonded by means of marks.
  • FIG. 1 The state of the wafers 1, 4 connected in this way is shown in FIG.
  • a first wafer 1 and a second wafer 4 are connected to one another by a bonding connection, and the bond connection comprises a first bonding material 3 and a second bonding material 6. It is important that the first bonding material
  • the bond is realized by aluminum Al or by an aluminum alloy, while the second bonding material 6 is gold.
  • the transition from the first 3 to the second bonding material 6 is the actual bond 8 between the two wafers 1, 4.
  • the actual bond 8 is the actual bond 8 between the two wafers 1, 4.
  • Bond connection 8 here comprises the bond connection of the bonding frame 8a and the bond connection of the electrical bond pad 8b. It is proposed to perform the bonding process with a bonding pressure of 0.5 to 15 MPa. This pressure range is on the one hand sufficiently large enough to bring about a reliable material connection of the two bonding materials 3, 6, on the other hand not unnecessarily too large, so that possible mechanical damage can be avoided by excessive pressure.
  • a temperature at and below 400 0 C in particular a temperature of 200 0 C to 400 0 C is considered.
  • the bonding time is from a few minutes to an hour.
  • the proposed method is also suitable for connecting a plurality of wafers with a number of wafers to be connected in a row greater than two.
  • a stacking of several wafers can be achieved.
  • the individual wafers arranged one above the other in the stack by means of a bonding connection can comprise both ASIC and MEMS elements.
  • Wafern 1, 4 well defined in wide ranges of at least 2 microns, in particular in a range of 2 microns to 30 microns, can be adjusted. This is made possible by the combination of bonding materials described above, which hardly form fluxes during the bonding process and thus maintain their respective layer thicknesses. These respective layer thicknesses are shown in FIG.
  • the invention ensures a controllable and simple production method of a wafer-to-wafer bond connection and provides a reliable arrangement of two wafers 1, 4 with a stable bond connection.
  • There are disadvantages arising from the state of the Technique are known, eliminated or at least greatly reduced.
  • deliquescence of the bonding materials 3, 6, 7 hardly occurs during the bonding process, as is otherwise known from previous methods.
  • the invention allows, for example, that the environment of the bond connections is free of structures against the flow of the bonding materials 3, 6, 7, in particular structures in the form of trenches. So-called stop trenches, which were necessary in previous arrangements of the wafer-to-wafer bond connections, are now advantageously dispensed with.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Micromachines (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)

Abstract

L'invention concerne un ensemble d'au moins deux tranches (1; 4), où une première tranche (1) et une deuxième tranche (4) sont reliées par soudage. L'invention concerne en outre un procédé de fabrication d'un tel ensemble, le procédé comprenant les étapes suivantes : a) application d'un premier matériau de connexion (3) sur une première tranche (1), le premier matériau de connexion (3) étant l'aluminium (Al) ou un alliage d'aluminium; b) application d'un deuxième matériau de connexion (6) sur une deuxième tranche (4), le deuxième matériau de connexion choisi étant l'or (Au); et c) exécution d'un processus de soudage, le premier (3) et le deuxième matériau de connexion (6) étant reliés l'un à l'autre et formant une connexion entre les deux tranches.
PCT/EP2009/061832 2008-11-14 2009-09-14 Ensemble d'au moins deux tranches liées par soudage et procédé de fabrication d'un tel ensemble Ceased WO2010054875A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102008043735.2 2008-11-14
DE102008043735A DE102008043735A1 (de) 2008-11-14 2008-11-14 Anordnung von mindestens zwei Wafern mit einer Bondverbindung und Verfahren zur Herstellung einer solchen Anordnung

Publications (1)

Publication Number Publication Date
WO2010054875A1 true WO2010054875A1 (fr) 2010-05-20

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DE (1) DE102008043735A1 (fr)
TW (1) TW201019402A (fr)
WO (1) WO2010054875A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015534642A (ja) * 2012-09-18 2015-12-03 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツングＲｏｂｅｒｔ Ｂｏｓｃｈ Ｇｍｂｈ 電磁波を検出するための少なくとも２つのウェハを有する装置、および、当該装置の製造方法
CN113582131A (zh) * 2021-07-27 2021-11-02 绍兴中芯集成电路制造股份有限公司 晶圆级封装方法及晶圆级封装结构

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102014221546A1 (de) 2014-10-23 2016-04-28 Robert Bosch Gmbh Mikroelektronische Bauelementanordnung mit einer Mehrzahl von Substraten und entsprechendes Herstellungsverfahren
FR3099953B1 (fr) * 2019-08-14 2021-07-30 Elichens Procédé de fabrication collective d'un détecteur pyroélectrique

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EP1333494A2 (fr) * 2002-01-25 2003-08-06 Texas Instruments Incorporated Dispositif à semi-conducteur et procédé de fabrication d'un assemblage semi-conducteur
US20040157407A1 (en) * 2003-02-07 2004-08-12 Ziptronix Room temperature metal direct bonding
US20060125084A1 (en) * 2004-12-15 2006-06-15 Fazzio Ronald S Integration of micro-electro mechanical systems and active circuitry
WO2006084028A2 (fr) * 2005-02-03 2006-08-10 Analog Devices, Inc. Liaison conductrice pour interconnexion transversale de plaquette
EP1071126B1 (fr) * 1999-07-23 2006-12-06 Agilent Technologies, Inc. (a Delaware corporation) Boîtier à l'échelle d'une plaquette semiconductrice comprenant un micro-capuchon avec des vias
US20070090536A1 (en) * 2005-10-21 2007-04-26 Denso Corporation Sensor having semiconductor chip and circuit chip
US7276789B1 (en) * 1999-10-12 2007-10-02 Microassembly Technologies, Inc. Microelectromechanical systems using thermocompression bonding
US20080245843A1 (en) * 2004-01-22 2008-10-09 Bondtech Inc. Joining Method and Device Produced by this Method and Joining Unit

Patent Citations (8)

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Publication number Priority date Publication date Assignee Title
EP1071126B1 (fr) * 1999-07-23 2006-12-06 Agilent Technologies, Inc. (a Delaware corporation) Boîtier à l'échelle d'une plaquette semiconductrice comprenant un micro-capuchon avec des vias
US7276789B1 (en) * 1999-10-12 2007-10-02 Microassembly Technologies, Inc. Microelectromechanical systems using thermocompression bonding
EP1333494A2 (fr) * 2002-01-25 2003-08-06 Texas Instruments Incorporated Dispositif à semi-conducteur et procédé de fabrication d'un assemblage semi-conducteur
US20040157407A1 (en) * 2003-02-07 2004-08-12 Ziptronix Room temperature metal direct bonding
US20080245843A1 (en) * 2004-01-22 2008-10-09 Bondtech Inc. Joining Method and Device Produced by this Method and Joining Unit
US20060125084A1 (en) * 2004-12-15 2006-06-15 Fazzio Ronald S Integration of micro-electro mechanical systems and active circuitry
WO2006084028A2 (fr) * 2005-02-03 2006-08-10 Analog Devices, Inc. Liaison conductrice pour interconnexion transversale de plaquette
US20070090536A1 (en) * 2005-10-21 2007-04-26 Denso Corporation Sensor having semiconductor chip and circuit chip

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015534642A (ja) * 2012-09-18 2015-12-03 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツングＲｏｂｅｒｔ Ｂｏｓｃｈ Ｇｍｂｈ 電磁波を検出するための少なくとも２つのウェハを有する装置、および、当該装置の製造方法
US10270001B2 (en) 2012-09-18 2019-04-23 Robert Bosch Gmbh Device having at least two wafers for detecting electromagnetic radiation and method for producing said device
CN113582131A (zh) * 2021-07-27 2021-11-02 绍兴中芯集成电路制造股份有限公司 晶圆级封装方法及晶圆级封装结构

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Publication number Publication date
DE102008043735A1 (de) 2010-05-20
TW201019402A (en) 2010-05-16

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