WO2010065100A2 - Procédé et appareil de transmission et de réception d'en-têtes de trames fec - Google Patents

Procédé et appareil de transmission et de réception d'en-têtes de trames fec Download PDF

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Publication number
WO2010065100A2
WO2010065100A2 PCT/US2009/006330 US2009006330W WO2010065100A2 WO 2010065100 A2 WO2010065100 A2 WO 2010065100A2 US 2009006330 W US2009006330 W US 2009006330W WO 2010065100 A2 WO2010065100 A2 WO 2010065100A2
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WIPO (PCT)
Prior art keywords
header information
binary sequence
produce
header
fec
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Ceased
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PCT/US2009/006330
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WO2010065100A3 (fr
Inventor
Hou-Shin Chen
Wen Gao
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Thomson Licensing SAS
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Thomson Licensing SAS
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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/136—Reed-Muller [RM] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6522—Intended application, e.g. transmission or communication standard
    • H03M13/6555—DVB-C2
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0072—Error control for data other than payload data, e.g. control data
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/20—Modulator circuits; Transmitter circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22—Demodulator circuits; Receiver circuits

Definitions

  • the present principles relate to cable transmission systems and techniques. More particularly, it relates to an FEC header design for cable television transmissions.
  • LDPC Low Density Parity Check
  • FEC Forward Error Correction
  • DVB-S2 LDPC codes family which were originally designed for forward error control in satellite communications, have also been used by DVB-T2 (Second Generation DVB Standard for Terrestrial Channels), and are strongly recommended for DVB-C2 (Second Generation DVB Standard for Cable Channels). OFDM modulation will be adopted as well as the coding technique (BCH+LDPC) specified in DVB-T2 Standard.
  • DVB-T2 Standard is designed for use in the terrestrial wireless channel while the DVB-C2 Standard is designed for use in the cable channel.
  • the signal frame structure and preambles used in DVB-T2 may not be suitable to be reused in DVB-C2 Standard.
  • a frame header of Forward Error Correction is designed for use in the DVB-C2 Standard.
  • the FEC data block is composed of a Bose-Chaudhuri- Hocquenghem (BCH) outer code and a Low-Density-Parity-Check (LDPC) inner code.
  • BCH Bose-Chaudhuri- Hocquenghem
  • LDPC Low-Density-Parity-Check
  • Two dimensional interleaving is also performed. Interleaving is a procedure for rearranging the order of a sequence to fulfill different objectives. For channels subject to selective fading over time and frequency domains, bit and/or symbol interleaving have been used in conjunction with channel coding to distribute the error bursts.
  • a frame header is attached in front of each FEC frame to indicate the coding rate, modulation type and physical layer pipe identifier. Besides the signaling of physical layer related information, the FEC frame header has to provide a structure so that it can be easily and reliably detected in the
  • An efficient and reliable FEC frame header for digital cable television transmission is provided in at least one implementation in this specification.
  • a method of detecting the FEC header is described.
  • An exemplary implementation is shown, using the DVB-C2 standard as an example.
  • An efficient and reliable FEC frame header for DVB-C2 Standard is provided in at least one implementation in this specification.
  • ACM Adaptive Coding and Modulation
  • VCM Variable Coding and Modulation
  • a frame header is attached in front of each FEC frame to indicate a receiver as to the coding rate, modulation type and physical layer pipe identifier. Besides signaling physical layer related information, it is desirable for the FEC frame header to provide a structure so that it can be easily and reliably detected in the receiver.
  • a method of detecting the FEC header is described.
  • the number of symbols of FEC frame header in an exemplary implementation in this specification is 32 which is less than other methods having 45 symbols.
  • the FEC frame header uses Reed-Muller (32,16) Code (RM(32,16)) to protect signaling bits while the FEC frame header of prior methods use BCH (45,18) code.
  • RM(32,16) code can be decoded by majority-logic decoding which requires less complexity than previous decoding methods.
  • the decoding complexity of the FEC frame header in an implementation according to the present principles is much less than decoding of a FEC frame header according to other known arrangements.
  • the Reed-Muller code has a symmetric code structure during majority- logic decoding process.
  • the detection of FEC frame header can be performed by taking advantage of this symmetric structure.
  • Figure 1 shows the frame structure of the frequency-domain DVB-C2 signals.
  • Figure 2 shows Generation of 32-Symbol FEC Frame Header.
  • Figure 3 shows Generation of 16-Symbol FEC Frame Header.
  • Figure 4 shows the Generator Matrix of RM(32,16) code.
  • Figure 5 shows a conceptual framework for 32-Symbol FEC frame header detection.
  • Figure 6 shows a conceptual framework for 16-Symbol FEC frame header detection.
  • Figure 7 shows a method for encoding a header using the principles described herein.
  • Figure 8 shows an apparatus for encoding a header according to the principles herein.
  • Figure 9 shows a first method of decoding the encoded header information according to the principles described herein.
  • Figure 10 shows a first apparatus for decoding the encoded header information according to the principles described herein.
  • Figure 11 shows a second method decoding the encoded header information according to the principles described herein.
  • Figure 12 shows a second apparatus for decoding the encoded header information according to the principles described herein.
  • the DVB-C2 Standard is the next generation digital cable transmission system being developed by the DVB Project.
  • the DVB-C2 Standard uses aspects of the DVB- T2 terrestrial transmission standard as much as possible.
  • OFDM modulation will be adopted as well as the coding technique (BCH+LDPC) specified in DVB-T2 Standard.
  • BCH+LDPC the coding technique specified in DVB-T2 Standard.
  • DVB-T2 Standard is designed for use in the terrestrial wireless channel while the DVB-C2 Standard is designed for use in the cable channel.
  • Cable channels differ from wireless channels because the cable channel is a high quality, high Signal-to-Noise Ratio (SNR) channel with only a few weak echoes and because the wireless spectrum assigned for TV broadcasting is generally defined by a governmental agency, such as the FCC 1 while the spectrum of the cable networks can be used with somewhat fewer limitations. Consequently, the signal frame structure and preambles used in DVB-T2 may not be suitable to be used in DVB-C2 Standard.
  • the principles described herein allow an FEC frame header to be detected under noisy channel conditions with minimal receiver complexity.
  • Data Slice Packets are formed from one or two FEC Frame cells. These Data Slice Packets can either be Data Slice Type 1 or Data Slice Type 2. Data Slice Type 1 packets only transmit the FEC Frame data and use a pointer within the Level 1 Signaling Part 2 to detect their start. Data Slice Type 2 packets carry a 16-bit FEC Frame header that allows for synchronization to the Data Slice Packets without further information being transmitted. This header carries information regarding the modulation, coding parameters, PLP identifiers, and number of FEC Frames (one or two) following the header. Encoding of the header information must ensure that the header can be properly synchronized and decoded.
  • FEC frame header In the DVB-C2 Standard, in order to support ACM or VCM over each FEC frame, a FEC frame header is attached to each FEC frame.
  • the FEC frame structure is shown in Figure 1.
  • Each FEC-coded frame is Quadrature Amplitude Modulation (QAM) modulated with different order and coding rate. These two critical parameters are carried in the FEC frame header that precedes each FEC frame.
  • QAM Quadrature Amplitude Modulation
  • the FEC frame header contains 16 signaling bits as described below:
  • PGP Physical Layer Pipe
  • Header Change Indicator or parity check bit- 1 bit when the bit is Header Change Indicator, the value of "1" indicates the first 4 parts of the FEC header of next FEC frame will be modified while the value of "0" indicates no change. The receiver will know if the bit is the header change indicator or parity check bit based on layer-1 signaling.
  • the signaling bits are protected by RM code which can be decoded with a low- complexity majority-logic decoding method.
  • the RM(32,16) code is selected and thus 16 message bits are coded into 32 codeword bits.
  • a PRBS (Pseudo-Random Binary Sequence) of length 32 is embedded in the FEC frame header structure to enable frame header detection in the receiver.
  • An example of the 32 PRBS bit is F8261 D92 in hex notation. It is a section from a PRBS having a generator polynomial of X 11 + ⁇ +!
  • Two frame header structures with different length are designed in at least one implementation in this specification.
  • the frame header structure with shorter length is provided for use in a high SNR environment.
  • FIG. 2 A conceptual framework for generating a 32-Symbol FEC frame header is shown in Figure 2.
  • the 16 signaling bits are coded by RM(32,16) code.
  • the resulting 32 codeword bits are modulated by in-phase BPSK or quadrature BPSK in a modulator using a PRBS.
  • the in-phase BPSK is used if the corresponding PRBS bit is 1. Otherwise, the quadrature BPSK is used.
  • FIG. 3 A conceptual framework for generating a 16-Symbol FEC frame header is shown in Figure 3.
  • the 16 signaling bits are coded by RM(32,16) code.
  • the resulting 32 codeword bits and 32 PRBS bits are 16-QAM modulated into 16 symbols by a 16-QAM modulator after every two codeword bits are paired with two PRBS bits.
  • Each 16-QAM symbol is produced from two codeword bits in the two most significant bits and two PRBS bits in the two least significant bits.
  • the two codeword bits determine the quadrant and the two PRBS bits determine the position in the quadrant.
  • the two most significant bits carry the codeword bits and the two least significant bits carry the PRBS bits.
  • the detection of the FEC frame header is performed by a two step method.
  • the first step is the correlation of the transmitted PRBS and received bit-stream.
  • the correlation with a given index / is given by
  • the second step is based on the RM(32,16) code structure.
  • the RM(32,16) code is not a first order Reed-Muller code, its codeword does not have a symmetric structure. However, during the majority-logic decoding process, after the first layer decoding, the modified codeword has a symmetry structure. This can be explained as follows:
  • the majority-logic decoding consists of 3 stages.
  • r (1) (r 0 (1) , r ⁇ ... , r 31 (1) ) is the modified received vector
  • x (1) (xo (1 ) , Xi (1 ) ,... , *3i (1 ) ) be its corresponding transmitted modified code vector. It can be seen that x (1) is a linear combination of the first 6 rows of the generator matrix of RM(32,16) code as shown in Figure 4. It can be easily verified that x (1) has a symmetric structure.
  • the sub-code vectors (x 0 (1 ) , xi (1 ) ,.. - , Xi5 (1) ) and (xie (1) , Xi7 (1) .- - - , *31 (1) ) are either the same or flipped. This kind of symmetry happens in sub-code vectors (xo (1) , Xi (1 ) ,...
  • RM symmetry measure as
  • the conceptual framework for detection of 32-Symbol FEC frame headers is shown in Figure 5.
  • the conceptual framework for detection of 16-symbol FEC frame headers is shown in Figure 6.
  • the only difference is in demodulating the information bits.
  • the bit stream for PRBS correlation is decoded by comparing the amplitudes of real part and imaginary part of the received signal.
  • the bit stream is from the 2 LSB of 16-QAM demodulator.
  • a 32- bit PRBS correlation is then performed.
  • the further RM correlation measure is performed only for those index / ' for which R RM ( ⁇ ) is greater than a threshold. This threshold is adjustable in the receiver.
  • Another variation for frame header detection is that the estimated frame header position is given by
  • ⁇ 0 argmaxl (5 (if + 4- T /iM (i)) (8)
  • FIG. 7 illustrates the method 700 for encoding the FEC header information under the present principles.
  • FEC Encoding is performed in step 710, using for example, RM(32,16) coding.
  • Modulation with a pseudo-random binary sequence is then performed in step 720.
  • Figure 8 illustrates an apparatus for encoding the FEC header information under the principles described herein.
  • Header information is received at the input of encoder 810.
  • the output is sent to the input of modulator 820, where the FEC encoded header information is modulated with a pseudo-random binary sequence.
  • Figure 9 illustrates a first method 900 of decoding the encoded FEC header information.
  • Header information is received in step 910.
  • the real and imaginary parts of the received header information are compared and a logical one is output when the real part has magnitude greater than or equal to the imaginary magnitude, and a logical zero is output otherwise in step 920.
  • This result is then correlated with a pseudorandom binary sequence in step 930 to produce a correlation result.
  • the correlation result is compared to a threshold in step 940. If the correlation result of step 930 is greater than the threshold, demodulation and symmetry detection is performed in step 950, producing a symmetry measure. If the correlation result is not greater than the threshold, the process is reinitiated by receiving header information in step 910.
  • Figure 10 illustrates an apparatus 1000 for performing this first method of decoding the encoded FEC header information.
  • Comparator 1010 compares the real and imaginary portions of the received header information and outputs the correct bits as detailed above.
  • Correlator 1020 correlates the result with a pseudo-random binary sequence to produce a correlation result.
  • the correlation result is input to demodulator 1030, which compares it to a threshold and, if greater than the threshold, demodulator 1030 demodulates the header information, followed by symmetry detection of the header information performed by block 1040, which outputs a symmetry measure.
  • Figure 11 illustrates a second method 1100 of decoding the encoded FEC header information. Header information is received in step 1110 and demodulated in step 1120.
  • the demodulated symbol produces 4 bits for 16-QAM.
  • the two least significant bits are correlated with a pseudo-random binary sequence in step 1130 to produce a correlation result.
  • the correlation result is compared to a threshold in step 1140. If the correlation result is greater than the threshold, symmetry detection is performed on the two most significant bits of the demodulated symbol information in step 1150. If the correlation result is not greater than the threshold, the process is reinitiated by receiving header information in step 1110.
  • Figure 12 illustrates an apparatus to perform this second method of decoding the encoded FEC header information.
  • Demodulator 1210 demodulates header symbols.
  • Correlator 1220 correlates the two least significant bits with a pseudo-random binary sequence.
  • Symmetry detector 1230 checks the correlation result against a threshold, and if the correlation result is greater than the threshold, symmetry detection is performed using, for example, majority decoding if a second order Reed-Muller code was used. The output of symmetry detector 1230 produces a symmetry measure.
  • the implementations described herein may be implemented in, for example, a method or process, an apparatus, or a software program. Even if only discussed in the context of a single form of implementation (for example, discussed only as a method), the implementation or features discussed may also be implemented in other forms (for example, an apparatus or program).
  • An apparatus may be implemented in, for example, appropriate hardware, software, and firmware.
  • the methods may be implemented in, for example, an apparatus such as, for example, a computer or other processing device. Additionally, the methods may be implemented by instructions being performed by a processing device or other apparatus, and such instructions may be stored on a computer readable medium such as, for example, a CD, or other computer readable storage device, or an integrated circuit. Further, a computer readable medium may store the data values produced by an implementation.
  • implementations may also produce a signal formatted to carry information that may be, for example, stored or transmitted.
  • the information may include, for example, instructions for performing a method, or data produced by one of the described implementations.
  • implementations may be implemented in one or more of an encoder, a pre-processor to an encoder, a decoder, or a post-processor to a decoder.
  • the implementations described or contemplated may be used in a variety of different applications and products.
  • Some examples of applications or products include set-top boxes, cell phones, personal digital assistants (PDAs), televisions, personal recording devices (for example, PVRs, computers running recording software, VHS recording devices), camcorders, streaming of data over the Internet or other communication links, and video-on-demand.
  • implementations are contemplated by this specification.
  • additional implementations may be created by combining, deleting, modifying, or supplementing various features of the disclosed implementations.
  • any switches shown in the figures are conceptual only. Their function may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the implementer as more specifically understood from the context.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Error Detection And Correction (AREA)

Abstract

L'invention concerne un en-tête de trame FEC (Forward Error Correction) permettant une utilisation dans la norme DVB-C2. Dans la norme DVB-C2, on applique des techniques de codage et de modulation adaptatifs (ACM, Adaptive Coding and Modulation) ou de codage et de modulation variables (VCM, Variable Coding and Modulation) à chaque bloc FEC, pour fournir autant de souplesse que possible. En conséquence, on joint un en-tête de trame devant chaque trame FEC pour indiquer le taux de codage, le type de modulation et l'identifiant du tuyau de couche physique. Outre la signalisation des informations relatives à la couche physique, l'en-tête de trame FEC doit fournir une structure susceptible d'être détectée facilement et de façon fiable au niveau du récepteur. En réponse au besoin de la norme DVB-C2, un en-tête FEC efficace et fiable adapté à la norme DVB-C2 est fourni dans au moins une mise en œuvre de l'invention. En outre, la méthode de détection de l'en-tête FEC est décrite.
PCT/US2009/006330 2008-12-02 2009-12-01 Procédé et appareil de transmission et de réception d'en-têtes de trames fec Ceased WO2010065100A2 (fr)

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US20066708P 2008-12-02 2008-12-02
US61/200,667 2008-12-02

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011008238A3 (fr) * 2009-06-29 2011-03-24 Thomson Licensing Procédé et appareil permettant une récupération d'en-tête de trame fec robuste et à haute efficacité
EP3122013A4 (fr) * 2014-04-17 2017-03-22 Huawei Technologies Co., Ltd. Procédé, appareil et système de modulation et de démodulation de code

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6031865A (en) * 1997-08-04 2000-02-29 Motorola, Inc. Rapidly decorrelating spreading sequences for DS-CDMA transceivers
US6865236B1 (en) * 2000-06-01 2005-03-08 Nokia Corporation Apparatus, and associated method, for coding and decoding multi-dimensional biorthogonal codes
US7352797B2 (en) * 2003-06-30 2008-04-01 Conexant Systems, Inc. Procedure for BPSK modulation with reduced envelope peaking

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011008238A3 (fr) * 2009-06-29 2011-03-24 Thomson Licensing Procédé et appareil permettant une récupération d'en-tête de trame fec robuste et à haute efficacité
JP2012532488A (ja) * 2009-06-29 2012-12-13 トムソン ライセンシング ロバスト及び高効率のｆｅｃフレームヘッダの回復の方法及び装置
US8532227B2 (en) 2009-06-29 2013-09-10 Thomson Licensing Method and apparatus for robust and high efficiency FEC frame header recovery
EP3122013A4 (fr) * 2014-04-17 2017-03-22 Huawei Technologies Co., Ltd. Procédé, appareil et système de modulation et de démodulation de code
US9762427B2 (en) 2014-04-17 2017-09-12 Huawei Technologies Co., Ltd. Code modulation and demodulation methods, apparatuses, and system

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