WO2010077802A1 - Amélioration de gravure à sec d'éléments à grand rapport de forme à l'aide de fluor - Google Patents

Amélioration de gravure à sec d'éléments à grand rapport de forme à l'aide de fluor Download PDF

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Publication number
WO2010077802A1
WO2010077802A1 PCT/US2009/067834 US2009067834W WO2010077802A1 WO 2010077802 A1 WO2010077802 A1 WO 2010077802A1 US 2009067834 W US2009067834 W US 2009067834W WO 2010077802 A1 WO2010077802 A1 WO 2010077802A1
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WO
WIPO (PCT)
Prior art keywords
gas
etching
etch
bosch
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2009/067834
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English (en)
Inventor
Souvik Banerjee
Paul Alan Stockman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Linde GmbH
Original Assignee
Linde GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Linde GmbH filed Critical Linde GmbH
Priority to SG2011043031A priority Critical patent/SG172119A1/en
Publication of WO2010077802A1 publication Critical patent/WO2010077802A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H10P50/244—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials comprising alternated and repeated etching and passivation steps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means

Definitions

  • the present invention relates to processes and apparatus for the dry etching of silicon and particularly to the dry etching of high aspect ratio vias or holes in silicon substrates for use in semiconductor or other electronic devices.
  • the existing method for dry etching of high aspect ratio features, e.g. vias or holes, in silicon substrates, is know as the Bosch process.
  • the Bosch process also known as pulsed or time-multipiexed etching, was originally designed for use in MEMs etching, but has been used successfully in the formation of off-chip interconnect holes.
  • the Bosch process employs repeated cycles of an alternating step process to achieve nearly vertical etched holes.
  • the first step comprises a plasma etch, wherein plasma containing some ions that attack the silicon substrate in a nearly vertical direction is used.
  • the most common plasma ions are sulfur hexafluoride (SF 6 ).
  • the second step in the Bosch process comprises deposition of a chemically inert passivation layer, most commonly using a C 4 F 8 source gas. Each step fasts for several seconds.
  • the passivation layer serves to protect the entire substrate from further chemical attack in subsequent etching steps. However, the directional ions bombard the substrate and etch through the passivation layer at the bottom of the hole formed by the prior etch step to ultimately expose and further etch the substrate.
  • the passivation layer along the sides of the hole helps to protect against further etching and to create the vertical holes.
  • Each cycle of etch and passivation results in a very small further etching at the bottom of the previously etched holes. After repeated cycles of etch and passivation, a high aspect via can be achieved.
  • vias can then be lined with a dielectric layer; e.g. SiO 2 , a metai barrier layer; e.g. Ta/TaN, and a copper seed layer.
  • a dielectric layer e.g. SiO 2
  • a metai barrier layer e.g. Ta/TaN
  • a copper seed layer e.g. copper seed layer.
  • the vias are then completely filled with copper to serve as off- chip interconnects between dies.
  • etching and passivation are carried out in a continuous process until the entire via is etched, rather than the alternating cycles of the Bosch process.
  • the etching gas for non-Bosch processes is the same, i.e. SF 6 , but passivation gases are usually O 2 or HBr.
  • passivation gases are usually O 2 or HBr.
  • O 2 as the passivation gas
  • a layer of SiO 2 is formed on the sidewall of the via, which is more resistant to etch by SF 6 than the silicon substrate.
  • the present invention addresses the disadvantages noted above regarding the Bosch process and non-Bosch processes by the addition of F 2 gas into the etch chamber.
  • the F 2 is highly reactive with silicon and reacts at the silicon surface in either its molecular state or in an activated state.
  • etch rates can be increased without degradation of the sidewalls of the via holes.
  • the etch cycle can be significantly reduced and less undercutting occurs. Therefore, the amount of scalloping of the sidewaNs is also reduced. This in turn leads to shorter overall process times and lower costs, without sacrifice of the integrity of the via being formed.
  • use of F 2 allows for a reduction in the use Of SF 6 .
  • the present invention provides advantages in the technology of dry etching of high aspect features; e.g. vias or holes, in a silicon substrate.
  • the present invention provides improvements over the standard Bosch and non-Bosch processes and overcomes the disadvantages noted above with respect to such processes.
  • the advantages of the present invention are accomplished by adding F 2 gas into the etch chamber.
  • the addition of F 2 to the etch chamber can be done in accordance with several different embodiments.
  • the F 2 gas is added with SF 6 into a plasma source as a percentage of the SF 6 flow rate.
  • the sum of partial pressures of F 2 and SF 6 is maintained at the same level as that when using SF 6 gas alone. This results in a reduction in the amount of SF 6 used.
  • SF 6 gas is completely replaced with a mixture of F 2 and a diluent gas such as N 2 , Ar, He, etc. The F 2 and diluent gas are then supplied as the plasma source for etching.
  • Another embodiment of the present invention combines F 2 in molecular state with either a diluent gases or with a reduced amount of plasma activated SF 6 .
  • a still further embodiment provides for the use of F 2 as the etchant gas and C 4 F 8 or another fluorocarbon gas as the passivation gas. Other combinations using F 2 are also possible.
  • F 2 in accordance with the present invention provides numerous advantages over the standard Bosch and non-Bosch processes.
  • F 2 at least as a component of the etching gas
  • etch rates can be increased. This increase of etch rate can be accomplished without degradation of the sidewalls of the via holes resulting in smooth via holes.
  • the increased etch rate allows for shorter overall process times and corresponding lower processing costs.
  • the use of F 2 allows for a reduction or elimination of the use of SF 6 .
  • the reduction or eiimination of SF 6 also reduces process costs, by reducing or eliminating the expense related to the abatement thereof. This will also help semiconductor manufacturing facilities meet the restrictions imposed by the Kyoto Protocol and guidelines established in the Chemical Restrictions Table of the International Technology Roadmap for Semiconductors.
  • the present invention has been described with respect to improvements to the Bosch and non-Bosch processes for the etching of vias or holes in silicon substrates.
  • the present invention may also be applied in plasma thinning of wafers where isotropic etching is required.
  • the advantages for wafer thinning are again reduction of time and cost of the process as well as the reduction or elimination of the use of the global warming gas SF 6 .
  • the process of the present invention can be used to etch other films or stacks than the silicon substrate described.
  • the present invention can be use for etching films of silicon dioxide, silicon nitride, doped silicon dioxide, low k dielectrics, copper, tungsten, silicon carbide and others. Etching of can be carried out on such films by themselves, in conjunction with silicon, or in a stack of various film layers.

Landscapes

  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Selon l'invention, les procédés Bosch et non Bosch classiques pour former des trous d'interconnexion à grand rapport de forme dans des substrats en silicium présentent plusieurs inconvénients, comprenant un traitement lent et coûteux et l'utilisation de quantités importantes de SF6, un gaz de réchauffement planétaire, en tant que gaz de gravure. La présente invention s'attaque à ces inconvénients en ajoutant un gaz F2 à la chambre de gravure. Le F2 peut être ajouté soit à l'état moléculaire soit dans un état dissocié et sert à augmenter les vitesses de gravure sans dégrader la qualité des trous d'interconnexion. Cela permet d'obtenir des temps de traitement globaux plus courts et des coûts plus bas sans sacrifier l'intégrité du trou d'interconnexion formé. De plus, l'utilisation de F2 permet de réduire ou de supprimer l'utilisation de SF6.
PCT/US2009/067834 2008-12-15 2009-12-14 Amélioration de gravure à sec d'éléments à grand rapport de forme à l'aide de fluor Ceased WO2010077802A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SG2011043031A SG172119A1 (en) 2008-12-15 2009-12-14 Enhancement of dry etch of high aspect ratio features using fluorine

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12249408P 2008-12-15 2008-12-15
US61/122,494 2008-12-15

Publications (1)

Publication Number Publication Date
WO2010077802A1 true WO2010077802A1 (fr) 2010-07-08

Family

ID=42310131

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2009/067834 Ceased WO2010077802A1 (fr) 2008-12-15 2009-12-14 Amélioration de gravure à sec d'éléments à grand rapport de forme à l'aide de fluor

Country Status (4)

Country Link
KR (1) KR20110100277A (fr)
SG (1) SG172119A1 (fr)
TW (1) TW201110226A (fr)
WO (1) WO2010077802A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6403491B1 (en) * 2000-11-01 2002-06-11 Applied Materials, Inc. Etch method using a dielectric etch chamber with expanded process window
US6426014B1 (en) * 1999-03-16 2002-07-30 Silverbrook Research Pty Ltd. Method of manufacturing a thermal bend actuator
US7226868B2 (en) * 2001-10-31 2007-06-05 Tokyo Electron Limited Method of etching high aspect ratio features

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6426014B1 (en) * 1999-03-16 2002-07-30 Silverbrook Research Pty Ltd. Method of manufacturing a thermal bend actuator
US6403491B1 (en) * 2000-11-01 2002-06-11 Applied Materials, Inc. Etch method using a dielectric etch chamber with expanded process window
US7226868B2 (en) * 2001-10-31 2007-06-05 Tokyo Electron Limited Method of etching high aspect ratio features

Also Published As

Publication number Publication date
TW201110226A (en) 2011-03-16
SG172119A1 (en) 2011-07-28
KR20110100277A (ko) 2011-09-09

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