WO2010120475A2 - Récupération de données dans un système de stockage à semi-conducteurs - Google Patents

Récupération de données dans un système de stockage à semi-conducteurs Download PDF

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Publication number
WO2010120475A2
WO2010120475A2 PCT/US2010/028853 US2010028853W WO2010120475A2 WO 2010120475 A2 WO2010120475 A2 WO 2010120475A2 US 2010028853 W US2010028853 W US 2010028853W WO 2010120475 A2 WO2010120475 A2 WO 2010120475A2
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Prior art keywords
memory
data
raid
targets
target
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Ceased
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PCT/US2010/028853
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WO2010120475A3 (fr
Inventor
Troy Larsen
Martin Culley
Troy Manning
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Micron Technology Inc
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Micron Technology Inc
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Publication of WO2010120475A3 publication Critical patent/WO2010120475A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G06F11/108—Parity data distribution in semiconductor storages, e.g. in SSD
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 

Definitions

  • the present invention relates generally to memory and in a particular embodiment the present invention relates to non- volatile memory.
  • RAM random access memory
  • ROM read only memory
  • DRAM dynamic random access memory
  • SDRAM synchronous dynamic random access memory
  • a flash memory is a type of memory that can be erased and reprogrammed in blocks instead of one byte at a time.
  • a typical flash memory comprises a memory array that includes a large number of memory cells. Each of the memory cells includes a floating gate fleld- effect transistor capable of holding a charge.
  • the cells are usually grouped into blocks of 64 pages of single level cells (SLC) or 128 pages of multilevel cells (MLC), where each page is typically 2048 bytes of data on 32 word lines.
  • SLC single level cells
  • MLC multilevel cells
  • Each of the cells within a block can be electrically programmed on a random basis by charging the floating gate.
  • Non- volatile memory can be incorporated into solid state storage devices such as solid state drives.
  • Solid state drives incorporating a large number of individual non- volatile memory devices, such as a large number of memory die, can be used to replace the hard disk drives in computers that typically use magnetic or optical disks for storing large amounts of data.
  • a solid state drive does not use moving parts whereas a hard disk drive requires a complex and sensitive drive and read/write head assembly to interact with the magnetic/optical disk.
  • the solid state drives are more resistant to damage and loss of data through vibration and impacts.
  • non-volatile memory can have a number of failed memory locations (e.g., bad cells, bad pages, bad blocks, etc.).
  • the failed memory locations may be defectively fabricated or can also fail during use. If a memory location fails during operation, the data stored in that location or locations may be lost.
  • Figure 1 shows a block diagram of one embodiment of a solid state storage system.
  • Figure 2 shows a block diagram of one embodiment of a memory communication channel coupled to a plurality of memory devices in accordance with the solid state storage system of Figure 1.
  • Figure 3 shows a block diagram of one embodiment of a non- volatile memory device that uses a memory communication channel.
  • Figure 4 shows a schematic diagram of one embodiment of a portion of a nonvolatile memory array in accordance with a non- volatile memory device of Figure 3.
  • Figure 5 shows a conceptual block diagram of one embodiment of a data programming operation utilizing RAID functions.
  • Figure 6 shows a conceptual block diagram of one embodiment of a RAID read page and data reconstruction.
  • Figure 7 shows a flowchart of one embodiment of a method for data recovery in a solid state storage system in accordance with the system of Figure 1.
  • FIG. 1 illustrates a block diagram of one embodiment of a solid state storage system, such as a solid state drive, that incorporates non- volatile memory.
  • the memory system is comprised of a system controller 101 that controls operation of the solid state storage system and enables the system to emulate a hard disk drive as well as perform other tasks.
  • the controller 101 has a plurality of communication channels that allow it to communicate with and control a plurality of memory targets. In the illustrated embodiment, the controller 101 has 16 communication channels and each communication channel is comprised of eight chip enables (i.e., CEO - CE7 ).
  • the controller 101 is coupled to an I/O interface 103 such as a peripheral component interconnect express (PCIe) interface or some other interface.
  • I/O interface 103 enables the controller 101 to communicate with external systems, such as a computer system, by handling standardized bus communication signals between the solid state storage system and the external system.
  • the controller 101 is also coupled to a plurality of expander blocks 104 - 106 that expand the communication channels usable by the controller 101.
  • Each communication channel from the controller 101 can be coupled to a respective one of eight different expander blocks.
  • Each expander block, such as blocks 104 - 106, has multiple communication channels 100, where each of the expander block communication channels 100 can be coupled to multiple memory targets.
  • One example of such an expander block communication channel 100 is illustrated in Figure 2 that is described subsequently.
  • An expander block communication channel might contain a plurality of distinct chip enable signals, such as CEO - CE7 . Each of these chip enable signals may in turn be coupled to a respective one of a plurality of memory targets 201-208.
  • a memory target can refer to one or more logical units (LUNs) of memory.
  • LUNs logical units
  • a memory target might be a single memory package that includes multiple LUNs.
  • a LUN corresponds to a single memory device, such as a single die.
  • FIG. 2 depicts an embodiment where an expander block communication channel 100 consists of eight chip enable signals respectively coupled to eight memory targets 201- 208, where each of the depicted memory targets corresponds to a single memory device.
  • LUN can also contain multiple planes of memory device dies.
  • the multiple LUNs may operate in parallel on different commands at the same time.
  • Each expander block 104 - 106 incorporates an extra communication channel 110 — 112 that is used as a RAID channel by the controller 101.
  • the RAID channel is coupled to one or more additional memory targets that are used by the system controller 101 for storing data redundant to that stored in other targets coupled to that expander block for each of the other communication channels coupled to that expander block.
  • addresses are loaded through a five-cycle sequence during command processing.
  • Two address types are used: a column address and a row address.
  • the column address is used to access bytes or words within a page.
  • the row address is used to address pages, blocks, and/or LUNs.
  • the row address structure in one embodiment, is comprised of lower order row address bits for page addressing, middle row address bits for block addressing, and the most significant row address bits for LUN addressing.
  • FIG. 2 illustrates a block diagram of one embodiment of an expander block communication channel 100 comprising a plurality of memory targets 201 - 208.
  • This figure shows the address/data bus 210, Read/ Write control signal 211, and chip enable signals 212 that make up one of the expander block communication channels.
  • the illustrated embodiment includes eight separate memory targets so that eight chip enable signals ( CEO - CE7 ) are used.
  • each of the memory targets are depicted as respective memory device 201 - 208 (e.g., respective separate die) which may be stacked with one or more of the other memory devices.
  • a solid state storage system may use only one memory device 201 or multiple memory devices.
  • a solid state storage system could be comprised of thousands of non- volatile memory devices organized into groups of non- volatile memory devices 201 , 202 in which each memory device in the target shares a single chip enable line. Each of the plurality of chip enable lines are coupled to a different group of non- volatile memory devices.
  • Figure 3 illustrates a functional block diagram of a single LUN, such as a nonvolatile memory device 300 that can be incorporated on an integrated circuit die.
  • the non- volatile memory device 300 in one embodiment, is a NAND flash memory.
  • the non- volatile memory device 300 has been simplified to focus on features of the memory that are helpful in understanding the present programming embodiments.
  • the non- volatile memory device 300 includes an array 330 of non- volatile memory cells such as the floating gate memory cells that are illustrated in Figure 4 and discussed previously.
  • the memory array 330 is arranged in banks of access line (e.g., word line) rows and data line (e.g., bit line) columns.
  • the columns of the memory array 330 are comprised of series strings of memory cells.
  • the connections of the cells to the bit lines determines whether the array is a NAND architecture, an AND architecture, or a NOR architecture.
  • the memory array 330 can be organized into memory blocks. The quantity of memory blocks is typically determined by the size of the memory device (i.e., 512 MB, IGB).
  • each memory block can be organized into 64 pages of single level cells (SLC). In an alternate embodiment, each memory block can be organized into 128 pages of multiple level cells (MLC). Each page of data, in one embodiment, can be comprised of 2048 bytes of data on 32 word lines.
  • Address buffer circuitry 340 is provided to latch address signals provided through the I/O circuitry 360. Address signals are received and decoded by a row decoder 344 and a column decoder 346 to access the memory array 330. It will be appreciated by those skilled in the art, with the benefit of the present description, that the number of address input connections depends on the density and architecture of the memory array 330. That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts. Data is also input and output through the I/O circuitry 360 based on the timing of the control signals provided on control bus 372.
  • the non- volatile memory device 300 reads data in the memory array 330 by a sense operation that senses voltage or current changes in the memory array columns using sense circuitry 350.
  • the sense circuitry 350 in one embodiment, is coupled to read and latch a row of data from the memory array 330.
  • Data input and output buffer circuitry 360 is included for bidirectional data communication as well as address communication over a plurality of data connections 362 with an external controller.
  • Write circuitry 355 is provided to write data to the memory array.
  • the memory control circuitry 370 decodes signals provided on control bus 372 from an external controller and/or expander block.
  • These signals can include read/write (R/ W ), chip enable (CE), command latch enable (CLE), address latch enable (ALE) as well as other control signals that are used to control the operations on the memory array 330 as well as other circuitry of the memory device 300. In one embodiment, these signals are active low but alternate embodiments can use active high signals.
  • the memory control circuitry 370 may be a state machine, a sequencer, or some other type of controller to generate the memory control signals.
  • the non-volatile memory device 300 communicates with an external controller and/or expander block over a channel 390.
  • the channel 390 is comprised of the memory address, data, and control signals between the external controller and/or expander block and the memory device 300.
  • the embodiment of Figure 3 shows the address and data being coupled as one bus to the I/O circuitry 360.
  • the address and data buses are separate inputs/outputs with the memory device 300.
  • Figure 4 illustrates a schematic diagram of a portion of a NAND architecture memory array comprising series strings of non- volatile memory cells. While the subsequent discussions refer to a NAND memory device, the present embodiments are not limited to such an architecture.
  • the memory array is comprised of an array of non- volatile memory cells 401 (e.g., floating gate) arranged in columns such as series strings 404, 405. Each of the cells 401 are coupled drain to source in each series string 404, 405.
  • a word line WLO - WL31 that spans across multiple series strings 404, 405 is connected to the control gates of each memory cell in a row in order to bias the control gates of the memory cells in the row.
  • Bit lines BLl, BL2 are eventually connected to sense circuitry (not shown) that detect the state of each cell by sensing current on a particular bit line.
  • Each series string 404, 405 of memory cells is coupled to a source line 406 by a source select gate 416, 417 and to an individual bit line BLl, BL2 by a drain select gate 412, 413.
  • the source select gates 416, 417 are controlled by a source select gate control line SG(S) 418 coupled to their control gates.
  • the drain select gates 412, 413 are controlled by a drain select gate control line SG(D) 414.
  • Each memory cell can be programmed as an SLC device or an MLC device.
  • Each cell's threshold voltage (V t ) is indicative of the data that is stored in the cell. For example, in an SLC, a V t of 0.5V might indicate a programmed cell while a V t of -0.5 V might indicate an erased cell.
  • the MLC may have multiple V t ranges that each indicate a different state. Multiple level cells can take advantage of the analog nature of a traditional flash cell by assigning a bit pattern to a specific voltage range stored on the cell. This technology permits the storage of two or more bits per cell, depending on the quantity of voltage ranges assigned to the cell.
  • Redundant Array of Independent Disks is a technology that employs the simultaneous use of two or more media (e.g., non- volatile memory devices) to achieve greater levels of performance, reliability, and/or larger data volume sizes.
  • the RAID support provided by the solid state storage system of Figure 1 divides and/or replicates data among multiple memory targets that are addressed in unison.
  • the multiple memory targets are seen by a computer operating system coupled to the solid state storage system of Figure 1 as one single hard disk drive.
  • the solid state storage system of Figure 1 can use a page addressing mode so that the expander blocks provide data protection by employing RAID-type hardware support.
  • RAID With the RAID function, corresponding pages in multiple memory targets are addressed in unison. These pages may not be located at the same physical address within each of the memory targets but the translated (i.e., logical) address at which the controller has positioned the data are associated together so that they are programmed and read in unison. There is a one-to-one correspondence across the RAID codeword.
  • the system uses the RAID functions to provide data back-up in that if a failure is experienced in one memory target, the data that was stored in that memory target can be recovered, for example, by using the corresponding page data and the associated RAID data (e.g., redundancy data) in the corresponding memory targets.
  • the failed target is identified.
  • the error detection is accomplished by memory control circuitry receiving an error correction coding error that is not correctable after subsequent failed attempts to read the bad page.
  • FIG. 5 illustrates a conceptual block diagram of a data programming operation utilizing the RAID functions of Figure 1.
  • each data register 0 - n (501 - 504) represents a different expander block communication channel coupled to a separate group of memory targets.
  • Each group of memory targets 510 - 513 is associated with a different expander block communication channel.
  • RAID channel register 500 is part of the RAID channel that stores the RAID redundancy data.
  • This RAID channel has its own associated group of memory targets 520 for storing the RAID redundancy data.
  • Figure 5 shows that as the data to be programmed to a respective memory target in each of groups 510 - 513 is sequentially written into the expander registers 501 - 504, the RAID redundancy data is calculated and stored in RAID channel register 500. After all of the page data is received and moved to the expander registers 501 - 504, the same addresses in the corresponding memory targets are programmed in unison. The programming can be performed on only a subset of the memory targets and is not required to be performed on all of the memory targets of the system.
  • a typical error condition may not include an entire memory target experiencing the failure.
  • a failure may simply be only a page or block of a location that cannot be read.
  • the target control circuitry can set and clear the notification to its associated expander. If an entire memory device/die/LUN is found to be unreadable, the error notification may be left on continuously when the failed location is being accessed.
  • the defective data is corrected by using the remaining good data, including the data from the RAID channels, and performing a bit- wise exclusive OR (XOR) operation of the same memory addresses in each memory target. Since the failed memory location is known, it is excluded from the XOR operation.
  • XOR bit- wise exclusive OR
  • the data from each corresponding memory target in each of groups 510 — 513 can be substantially simultaneously written into the expander registers 501 - 504.
  • the RAID redundancy data from the memory target in RAID group 520 is also written into the RAID channel register 500 at this time.
  • the XOR operation 650 is performed on the data from corresponding locations in each accessed memory target, including the corresponding memory target in RAID group 520.
  • the XOR operation is performed on the pages of data starting at location 003Fh of each of the other groups 510, 511, 513, and 520 coupled to the expander block.
  • the XOR operation can be performed by data reconstruction logic 650 or a controller performing an XOR operation.
  • the reconstructed data can then be passed to the system controller through the combination logic 630 - 633 with the other data.
  • the expander block associated with the failed memory device is notified of the failed read operation. In one embodiment, this is accomplished by the associated expander block receiving a command that specifically identifies the particular channel that is associated with the memory device that cannot be read. Once the associated expander block is informed of the failed channel, the memory control circuitry of the memory device that has failed can issue a re-read of the failed page. The data can then be read without regard to the fact that data for the failed memory device will be reconstructed by the expander block. There is no impact on performance when reading reconstructed data.
  • FIG 7 illustrates a flowchart of one embodiment of a method for data recovery in a solid state storage system, such as the system of Figure 1.
  • the method can be executed by the solid state storage system controller, any of the individual memory device control circuitry, or any other controller.
  • the method involves detection by a controller that the data stored in a particular memory target cannot be correctly read back out and has too many errors for correction by an error correction coding (ECC) scheme (e.g., Hamming code, BCH code, Turbo code, LDPC code, Reed-Muller code, Binary Golay code, Trellis Code Modulation).
  • ECC error correction coding
  • the method begins by reading data into the appropriate controller 701. In one embodiment, a page of data is read into the controller. Alternate embodiments might read in other amounts of data.
  • the controller determines if the data is correct 703. This determination can be performed by an ECC verification, a parity check or some other error checking scheme.
  • the method is done 704. If the data has errors, it is determined if the errors can be corrected by an ECC 705. If the number of errors is less than or equal to the ECC threshold, the errors are corrected 707. If the number of errors in the data is more than can be corrected by the ECC scheme, the controller and the associated expander block are informed that the data has been found to be unrecoverable 709. This can be accomplished by setting a bit in a control register, sending a command to the control circuitry of the memory target in which the defective data is stored, and/or sending an error indication to the system controller. The error indication can inform the controller that a particular cell is bad, a particular page is bad, a particular block is bad, or an entire memory device is bad.
  • the defective data is reconstructed by performing a bit- wise XOR operation on the remaining good data and the RAID redundancy data 711 as described with reference to Figure 6.
  • the location of the defective data can be used by the controller performing the operation to know which target's data stream to exclude from the XOR operation and to which page the regenerated data should be associated.
  • the same addresses of each corresponding memory target coupled to a particular expander block are XOR'ed during the data regeneration process.
  • one or more embodiments of the present invention provide a method for recovering defective data in a memory system such as a solid state drive. Once the location of the defective data is known, good data can be XOR'ed with RAID data to reconstruct the defective data. The defective data is excluded from this logical combining operation.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

La présente invention concerne des procédés de récupération de données ainsi que des systèmes de mémoire. Selon au moins un procédé de l'invention, lorsque des données défectueuses sont lues dans un emplacement de la mémoire, les données sont récupérées par une opération OU EXCLUSIF effectuée sur les données valides restantes et les données RAID associées afin de reconstruire les données défectueuses. Les données défectueuses sont exclues de l'opération OU EXCLUSIF.
PCT/US2010/028853 2009-04-16 2010-03-26 Récupération de données dans un système de stockage à semi-conducteurs Ceased WO2010120475A2 (fr)

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US12/424,766 US8327224B2 (en) 2009-04-16 2009-04-16 Data recovery in a solid state storage system
US12/424,766 2009-04-16

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TWI442407B (zh) 2014-06-21
US20100268985A1 (en) 2010-10-21
US20130080860A1 (en) 2013-03-28
US8732549B2 (en) 2014-05-20
TW201044409A (en) 2010-12-16
US20140298090A1 (en) 2014-10-02
US8327224B2 (en) 2012-12-04
WO2010120475A3 (fr) 2011-01-13
US9201718B2 (en) 2015-12-01

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