WO2010142342A1 - Dispositif à semi-conducteurs de puissance - Google Patents

Dispositif à semi-conducteurs de puissance Download PDF

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Publication number
WO2010142342A1
WO2010142342A1 PCT/EP2009/057261 EP2009057261W WO2010142342A1 WO 2010142342 A1 WO2010142342 A1 WO 2010142342A1 EP 2009057261 W EP2009057261 W EP 2009057261W WO 2010142342 A1 WO2010142342 A1 WO 2010142342A1
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Prior art keywords
layer
pillar
semiconductor device
base region
base
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Ceased
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PCT/EP2009/057261
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English (en)
Inventor
Marina Antoniou
Florin Udrea
Friedhelm Bauer-Holzer
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ABB Research Ltd Switzerland
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ABB Research Ltd Switzerland
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Priority to PCT/EP2009/057261 priority Critical patent/WO2010142342A1/fr
Publication of WO2010142342A1 publication Critical patent/WO2010142342A1/fr
Anticipated expiration legal-status Critical
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/211—Gated diodes
    • H10D12/212—Gated diodes having PN junction gates, e.g. field controlled diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/141—Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs
    • H10D62/142—Anode regions of thyristors or collector regions of gated bipolar-mode devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/343—Gate regions of field-effect devices having PN junction gates

Definitions

  • the invention relates to the field of power electronics and more particularly to a power semiconductor device according to the preamble of claim 1.
  • IGBTs above 3.3 kV
  • SOA safe operating area
  • a dominant failure mode in high voltage IGBTs is the cosmic ray induced breakdown: when operated continuously at the rail voltage, which voltage is about half of the rated breakdown voltage, some devices start to loose their blocking capability far below the rated maximum blocking voltage.
  • the failure in time (FIT) rate is highly dependent on the peak electric field in the drift region and increases with the applied blocking voltage as shown in the documents "Cosmic Ray induced failures in high power semiconductor devices", Solid State Electron 1995 38(12): 2041 - 2046, by Zeller HR. Therefore, engineering the base layer to minimize the peak field under DC rail voltage is essential.
  • the super junction bipolar transistor a new silicon power device concept for ultra low loss switching applications at medium to high voltages
  • the Superjunction Insulated Gate Bipolar Transistor (SJ-IGBT) can open new paths to surpass the limitations of current state-of-the-art silicon IGBTs with respect to the on-state and the turn-off performance.
  • FIG. 1 shows a prior art superjunction IGBT 11 as described in "The super junction bipolar transistor: a new silicon power device concept for ultra low loss switching applications at medium to high voltages", Solid State Electronics, vol. 48, pp. 705-714, 2004, F. Bauer. It comprises a semiconductor wafer 10 and a cathode electrode 8', which is formed on a cathode side 101' of the wafer, and an anode electrode 9', which is formed on an anode side 102' of the wafer opposite the cathode side 101 '.
  • the semiconductor wafer 10 comprises a structure with a plurality of layers of different conductivity types:
  • a base layer 4 which comprises n doped first pillars 41 and p doped second pillars 42, the first and second pillars 41 , 42 being arranged alternately in the same plane,
  • planar gate electrode 5 which is electrically insulated by an insulation layer 51 from the source region 2 and the base region 3, and a buffer layer 62, which is arranged on the anode side 9' of the wafer.
  • the p doped second pillars 42 contact the p doped base region 3.
  • FIG. 2 shows a prior art semi superjunction IGBT 12 as it is for example described in "A Simulation Study on Novel Field Stop IGBTs Using
  • a first n doped layer 44 is arranged, which is a continuous layer ranging over the whole plane of the wafer 10.
  • Trench FS-IGBTs Another concept for achieving low losses are Trench FS-IGBTs, with which an on state plasma distribution can be realized, which allows to achieve a better trade off between on-state and turn-off losses.
  • This further makes it possible to introduce a transparent anode, which again is advantageous for the on-state and switching.
  • the trench gate brings with it a more natural 1 D current distribution, eliminates the parasitic JFET effect, enhances the PIN diode effect, i.e. the electron injection into the top side of the base layer, minimizes the MOS channel resistance and increases the immunity against latch-up.
  • Fig. 3 shows the structure of such a Trench Field Stop IGBT 13.
  • the Trench FS IGBT comprises a gate electrode 5, which is arranged in the same plane as the base region 3 and adjacent to the source region 2, separated from each other by an insulation layer 51 , which also separates the gate electrode 5 from the base layer 10 and the first electrical contact 8.
  • the trench gate IGBT has limits caused by the high electric field around the trench corners which can degrade its reliability and SOA performance. Further on, it is more difficult to achieve low short circuit currents in this particular IGBT geometry.
  • the inventive power semiconductor device 1 comprises a semiconductor wafer 10 and a first electrical contact 8, which is formed on a first main side 101 of the wafer, and a second electrical contact 9, which is formed on a second main side 102 of the wafer opposite the first main side 101.
  • the semiconductor wafer 10 comprises a structure with a plurality of layers of different conductivity types:
  • a base layer 4 which comprises at least one first pillar 41 of the first conductivity type and at least one second pillar 42 of the second conductivity type, the first and second pillars 41 , 42 being arranged alternately in the same plane, - a gate electrode 5, 5', which is electrically insulated by an insulation layer 51 from the source region 2 and the base region 3.
  • Each source region 2 is arranged on the first main side 101 of the wafer and separated from the base layer 4 by a base region 3. At least one second pillar 42 is not in contact with the base region 3.
  • the cosmic radiation induced breakdown rate is significantly improved in the inventive IGBT as the electric field at the first main side of the base layer is effectively flattened (Fig. 19). This means that the peak of the electric field in the structure is reduced (at the given rail voltage - i.e. half of the rated voltage).
  • FIG. 18 shows the improvement in reducing overvoltages during switching in the inventive semiconductor devices (an inventive device with a planar gate electrode has been used) compared to a prior art superjunction
  • the inventive IGBT offers significant improvement in the on-state and switching trade-off compared to both prior art Field Stop (FS) Trench IGBT and the SJ IGBT or semi SJ IGBT. Especially for small on-state voltages, the inventive devices have much lower turn-off switching losses than the prior art devices as is shown in Fig. 17. Furthermore, the inventive devices can be operated at smaller absolute on-state voltages than the prior art SJ- IGBTs (90 ⁇ m pillar height) or semi SJ-IGBTs (10 and 50 ⁇ m pillar height).
  • FS Field Stop
  • Such an inventive semiconductor device maintains a high static and dynamic avalanche breakdown while at the same time improving dramatically (by one to two orders of magnitude) the FIT rate under cosmic ray exposure.
  • the device offers considerably better robustness against cosmic rays when compared to a conventional FS IGBT. This can be proved via analytical modeling that the FIT (Failure in Time) levels can be improved by one to two orders of magnitude (see FIG. 20). All devices for the modeling have a wafer height of 400 ⁇ m and the inventive device has a pillar doping concentration of 2 * 10 15 cm "3 .
  • p doped second pillars 42 are separated from the base region 3 by an n doped part of the base layer 4 (e.g. by a disconnection layer 43 or by an n doped first pillar 41 ) so that there is no direct connection between the p doped second pillar 42 and the p doped base region 3 and the second pillar 42 is thereby separated from the base region 3.
  • the inventive semiconductor device may comprise only one active cell with one or more separated second pillars 42.
  • the device may also comprise a plurality of cells with one, a plurality or all of the second pillars 42 being separated from, i.e. not being in contact to, the p base region 3 of the corresponding cell.
  • the at least one second pillar 42 is separated from the p doped base region 3 by a part of the base layer 4 of the first conductivity type.
  • the holes have a direct path through the second pillar 42 to the base region 3.
  • this path is controlled in the inventive IGBT by the gate setting the base current of the afore-mentioned PNP transistor.
  • the second pillar 42 acts as an emitter for the second carrier type
  • the disconnection layer and part of the first pillar 41 form the base of the PNP transistor and the base region 3 achieves the role of the collector layer.
  • the PNP base current has vanished - the first carrier type is extracted from the base layer 4 (41 , 42) via the anode layer 9. Accordingly, anode layer 9 can no longer inject carriers of the second type and the second pillar 42 will cease to act as emitter.
  • the switching losses of the Semi-SJIGBT are found to be substantially lower than the standard Trench FS IGBT. Comparing the technology curves of a Trench Field Stop IGBT to an inventive Semi-SJ- IGBT with a first and second pillar height of 10 ⁇ m, 50 ⁇ m and 90 ⁇ m, the switching-off losses as a function of the on-state voltage are lower for the inventive devices as shown in FIG. 16. Furthermore, the figure shows the differences of the switching-off losses for second pillars being limited to an area below the trench gate electrode (designated in Fig. 16 as "contrench IGBT") and for second pillars, being arranged below the base region, but separated from it by a disconnection layer (designated in the figure as "trench IGBT").
  • FIG 1 shows a prior art superjunction IGBT
  • FIG 2 shows a prior art semi superjunction IGBT
  • FIG 3 shows a prior art fieldstop IGBT
  • FIG 4 shows a first embodiment of an inventive IGBT with a planar gate electrode
  • FIGs 5 to 8 show further embodiments of inventive IGBTs with a planar gate electrode
  • FIG 9 and 10 show other embodiments of inventive IGBTs with a trench gate electrode
  • FIGs 11 and 12 show other embodiments of inventive IGBTs with a planar gate electrode
  • FIG 13 and 14 show other embodiment of inventive JFEBTs (junction field effect bipolar transistor) with a planar gate electrode
  • FIG 15 shows a comparison of the switching losses versus on-state voltage for inventive IGBTs with pillar heights of 10, 50 and 90 ⁇ m with planar gate electrodes or trench gate electrodes and a prior art trench FS IGBT;
  • FIG 16 shows a comparison of the switching losses versus on-state voltage for inventive IGBTs with pillar heights of 10, 50 and 90 ⁇ m with trench gate electrodes and second pillars being arranged directly below the trench gate electrode and such devices, in which no second pillar is arranged below the trench gate electrode;
  • FIG 17 shows a comparison of the switching losses versus on-state voltage for inventive IGBTs with pillar heights of 10, 50 and 90 ⁇ m with planar gate electrodes and prior art SJ IGBTs;
  • FIG 18 shows a comparison of the voltages during switching-off versus time for inventive IGBTs with pillar heights of 50 ⁇ m with planar gate electrodes and prior art SJ IGBTs;
  • FIG 19 shows the electric field for a prior art FS IGBT and for inventive devices with pillar heights of 50 and 150 ⁇ m, the device comprising a first layer;
  • FIG 20 shows a plot of the room temperature cosmic ray induced failure rate as a function of the V an ode for the Trench FieldStop IGBT and inventive Semi-SJ IGBT with second pillar doping concentration of 2*10 15 cm "3 and a wafer height equal to 400 ⁇ m;
  • FIG 21 shows a plot of the switching-off losses at room temperature as a function of the on-state voltage for a prior art Trench Field Stop IGBT and an inventive Semi SJ-IGBT with p-doped second pillar doping concentration of 1 *10 15 cm “3 and 2*10 15 cm “3 , a wafer height equal to 400 ⁇ m, a pillar height equal to 50 ⁇ m and a cell width of 5 ⁇ m; and
  • FIG. 4 shows an inventive insulated gate bipolar transistor with a semiconductor wafer 10 and a first electrical contact 8 formed on a first main side 101 of the wafer and a second electrical contact 9 formed on a second main side 102 of the wafer opposite the first main side 101.
  • the first main side 101 is the cathode side, on which a cathode electrode as the first electrical contact 8 is arranged
  • the second main side 102 is the anode side of the device, on which an anode electrode as the second electrical contact 9 is arranged.
  • the inventive IGBT comprises n doped source regions 2 contacting the cathode electrode, and a p doped base region 3 also contacting the cathode electrode. It further comprises a base layer 4, with first n doped pillars 41 and p doped second pillars 42, the first and second pillars 41 , 42 being arranged alternately in the same plane.
  • a gate electrode 5, 5' which is electrically insulated by an insulation layer 51 from the source region 2 and the base region 3, is arranged on the cathode side.
  • the inventive IGBT comprises a p doped anode layer 6, on which the anode electrode is arranged.
  • the source regions 2 are arranged on the cathode side of the wafer and separated from the base layer 4 by the base region 3.
  • the second pillars 42 are separated from the base region 3, i.e. the second p doped pillars 42 are not in contact with the base region 3.
  • the doping of anode layer is higher than the doping of second pillar 42, preferably about one order of magnitude higher than the doping of second pillar 42.
  • the base layer 4 further comprises an n doped disconnection layer 43, which is arranged between the base region 3 and the first and second pillars 41 , 42 as shown in FIG. 5.
  • the disconnection layer 43 can be a continuous region over the whole wafer plane. Alternatively, the disconnection layer 43 can be a laterally limited region.
  • the positions of the first and second pillars 41 , 42 can also be switched as shown in FIG. 14 or shifted to a side, i.e. the first and second pillars 41 , 42 do not necessarily have to be positioned symmetrical to the other layers of the device, e.g. to the cathode electrode or the gate electrode.
  • One, a plurality of or all of the second pillars 42 are separated from the base region 3.
  • the disconnection layer 43 typically has a doping concentration of at maximum 1 * 10 17 cm "3 .
  • the doping concentration of the disconnection layer is equal to or less than the doping concentration of the first pillars 41.
  • the height of the disconnection layer is at maximum 20 ⁇ m and in yet another embodiment the height of the disconnection layer is at maximum 3 ⁇ m.
  • the height of the disconnection layer is at minimum 0.1 ⁇ m.
  • the disconnection layer 43 one or a combination or all of the above disclosed features can be present.
  • the width 411 multiplied by the doping concentration of the first pillar is either equal to or differs by at maximum +/- 5 % from the width 421 multiplied by the doping concentration of the second pillar (in all figures the width is indicated by a dashed line; this line is not meant to show the real pillar width, e.g. the second pillars 42 in Fig. 4 continue beyond the sides of the device section shown in the figure).
  • the Figs. 21 and 22 show the influence of doping concentration and pillar height on the on-state voltage and switching losses compared to a standard prior art Trench FS IGBT.
  • the properties of the device improve with higher doping concentration and with base layers 4, which comprise "moderate" pillar heights 412, 422 together with n doped first layers 44, i.e. semi superjunction devices, which are explained in the paragraph below.
  • the base layer 4 may also comprise an n doped first layer 44, which is arranged as a continuous layer over the whole plane of the wafer on the first and second pillars 41 , 42 on the side towards the anode electrode (FIG. 6).
  • a first layer 44 may have a doping concentration, which is lower than the doping concentration of the first pillar.
  • a semi superjunction semiconductor device is provided.
  • Such a design with first and second pillars 41 , 42 over a smaller depth than the total depth of the base layer 4 can be more easily fabricated. This makes the device superior for power semiconductor devices, for high voltages, e.g. for 3.3 kV or even greater voltage ranges (e.g. 6.5 kV).
  • the dynamic avalanche breakdown is avoided as the doping of the second main side 102 of the base layer 4 is kept low.
  • the height of the first pillar 412, of the second pillar 422 or of any of the first and second pillar 412, 422 may be as low as 1 % of the total wafer height or in another embodiment at least 10 % of the total wafer height.
  • the IGBT may further comprise an n doped buffer layer 62, which is arranged between the anode layer 65 and base layer 4.
  • n doped buffer layer 62 Such an inventive device is shown in FIG. 8.
  • the buffer layer has a higher doping concentration than the first layer 44, typically the doping concentration is two or three orders of magnitude higher than of the first layer.
  • the gate electrode may be formed as a planar gate electrode 5 as shown in FIG. 4.
  • the electrically insulating insulation layer 51 is arranged on top of the cathode side of the wafer.
  • the gate electrode 5 is completely embedded in the insulation layer 51 and thus, the gate electrode 5 is electrically separated from the source regions 2, the base region 3, the base layer 4 and the cathode electrode.
  • the gate electrode 5 is typically made of a heavily doped polysilicon or a metal like aluminum.
  • the gate electrode may be formed as a trench gate electrode 5' as shown in the FIGs. 10 and 11.
  • the trench gate electrode 5' is arranged in the same plane as the source regions 2 and the base region 3 and adjacent to the latter. They are separated from each other by the insulation layer 51 , which also separates the gate electrode 5' from the base layer 4.
  • the trench gate electrode 5' is typically completely embedded in the insulation layer 51 , thus insulating the trench gate electrode 5' from the cathode electrode.
  • FIG. 15 shows the switch ing-off losses as a function of the on-state voltage for a prior art trench FS IGBT and for inventive devices with planar gate electrode 5 or trench gate electrode 5' respectively.
  • the prior art FS IGBT has the highest switching-off losses for a given on-state voltage.
  • the on-state voltage for the inventive IGBT can be reduced by at least 0.7 V even for the case of a pillar height of merely 10 ⁇ m.
  • both losses and on-state voltage are lower for all conditions shown in FIG. 15.
  • smaller on-state voltages cannot be achieved for the trench FS IGBT, because of insufficient excess base charge in the base layer 4 towards the cathode 101.
  • the inventive devices with trench gate electrodes 5' have lower switching-off losses than devices with planar gate electrodes 5.
  • the second pillar 42 is limited to a region below the insulation layer 51 of the trench gate electrode 5' as shown in FIG. 10.
  • the base layer 4 may also comprise p doped fourth layers 45 and n doped fifth layers 46, each of which having a width, which is smaller than the width of the first and second pillars (Fig. 11 ).
  • the doping concentration of the fifth layer is in an exemplary embodiment higher than the doping concentration of the first pillar.
  • the doping concentration of the fourth layer is also preferably higher than the doping concentration of the second pillar.
  • the doping concentration of the fourth and fifth layers are higher than the doping concentration of the second and first pillar, respectively.
  • Such fourth and fifth layers may also be used in any prior art superjunction or semi superjunction power semiconductor device, i.e. in any device with planar or trench gate electrode, like IGBTs or reverse conducting IGBTs.
  • the fourth and fifth layers 45, 46 can be arranged on the side of the base layer 4 towards the first electrical contact 8, between the first and second pillars 41 , 42 and the disconnection layer 43.
  • the fourth and fifth layers 45, 46 can be arranged in any appropriate plane within the base layer 4, e.g. on the pillars 41 , 42 or even on the first layer 44 on the side towards the second main electrode 9, or within the plane of the pillars 41 , 42, of the first layer 44 or the disconnection layer 43.
  • the fourth and fifth layers 45, 46 can furthermore be arranged over the whole plane of the device or only over a part of the plane, e.g. without the termination region of the device.
  • the inventive semiconductor device is shown in form of a Junction field effect bipolar transistor (JFEBT).
  • the base region 3 comprises a first base region 31 , which is arranged below the cathode electrode and which is in electrical contact with the source region 2 and the cathode electrode, a second base region 32 with a second base region width, which second base region 32 is arranged below the source regions 2 and in contact to the first base region 31 and which has a greater second base region width than the first base region width.
  • the device further comprises at least one p doped first gate region 33, which is in electrical contact to the planar gate electrode 5 and which is separated from the first and second base region 31 , 32 by a part of the base layer 4 of the first conductivity type, i.e. by a first pillar 41 and/or the disconnection layer 43.
  • the second base region 32 may be partly arranged below the first gate region 33, but separated from it by an n doped part of the base layer 4 as shown in FIG. 13 (i.e. disconnection layer 43 or n doped first pillar 41 ). Alternatively, no part of the second base region 32 is arranged below the first gate region 33 as shown in FIG. 12 (vertical JFEBT).
  • the inventive semiconductor device may also be a reverse conducting IGBT, which comprises the same layers as disclosed above for the IGBT and which further comprises an n doped third layer 45, which is arranged in the same plane as the p doped anode layer 6 (i.e. on the second main side 102 of the wafer) and alternately to it (FIG. 7).
  • the total area of the third layers 45 is less than 25 %, less than 10 % of the total wafer area or even less than 5 %
  • the second pillar may be limited to a region below the second base region, separated from it by the disconnection layer.
  • the conductivity types of the layers are switched, i.e. all layers of the first conductivity type are p type (e.g. the source region) and all layers of the second conductivity type are n type (e.g. the base region).

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un dispositif à semi-conducteurs de puissance (1) comprenant une tranche semi-conductrice (10), un premier contact électrique (8) formé sur un premier côté principal (101) de la tranche et un second contact électrique (9) formé sur un second côté principal (102) de la tranche opposé au premier côté principal (101). Ladite tranche (10) comprend une structure dotée d'une pluralité de couches de différents types de conductivité, à savoir : au moins une région source (2) d'un premier type de conductivité en contact avec le premier contact électrique (8), au moins une région de base (3) d'un second type de conductivité en contact avec le premier contact électrique (8), une couche de base (4) et une électrode de grille qui est isolée électriquement d'une couche d'isolation (51) à partir de la région source (2) et de la région de base (3). La couche de base (4) comprend au moins un premier montant (41) du premier type de conductivité et au moins un second montant (42) du second type de conductivité, le premier et le second montant (41, 42) étant agencés alternativement dans le même plan. Au moins le second montant (42) n'est pas en contact avec la région de base (3).
PCT/EP2009/057261 2009-06-12 2009-06-12 Dispositif à semi-conducteurs de puissance Ceased WO2010142342A1 (fr)

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Cited By (2)

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Publication number Priority date Publication date Assignee Title
WO2017146997A1 (fr) * 2016-02-24 2017-08-31 General Electric Company Conception et fabrication de dispositifs à semi-conducteurs présentant des notations de rayons cosmiques terrestres (tcr) spécifiques
KR20200069047A (ko) * 2018-12-06 2020-06-16 현대오트론 주식회사 전력 반도체 소자 및 그 제조방법

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WO2017146997A1 (fr) * 2016-02-24 2017-08-31 General Electric Company Conception et fabrication de dispositifs à semi-conducteurs présentant des notations de rayons cosmiques terrestres (tcr) spécifiques
CN108780807A (zh) * 2016-02-24 2018-11-09 通用电气公司 设计和制作带有特定地球宇宙射线(tcr)额定值的半导体装置
US10403711B2 (en) 2016-02-24 2019-09-03 General Electric Company Designing and fabricating semiconductor devices with specific terrestrial cosmic ray (TCR) ratings
KR20200069047A (ko) * 2018-12-06 2020-06-16 현대오트론 주식회사 전력 반도체 소자 및 그 제조방법
KR102163665B1 (ko) * 2018-12-06 2020-10-08 현대오트론 주식회사 전력 반도체 소자 및 그 제조방법

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