WO2010143597A1 - Procédé de fabrication d'une carte de circuit imprimé, carte de circuit imprimé fabriquée au moyen du procédé et substrat de base utilisé pour la carte de circuit imprimé - Google Patents

Procédé de fabrication d'une carte de circuit imprimé, carte de circuit imprimé fabriquée au moyen du procédé et substrat de base utilisé pour la carte de circuit imprimé Download PDF

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Publication number
WO2010143597A1
WO2010143597A1 PCT/JP2010/059569 JP2010059569W WO2010143597A1 WO 2010143597 A1 WO2010143597 A1 WO 2010143597A1 JP 2010059569 W JP2010059569 W JP 2010059569W WO 2010143597 A1 WO2010143597 A1 WO 2010143597A1
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WO
WIPO (PCT)
Prior art keywords
circuit board
hole
sealing
circuit
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2010/059569
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English (en)
Japanese (ja)
Inventor
河浦茂裕
井田誠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Carbide Industries Co Inc
Original Assignee
Nippon Carbide Industries Co Inc
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Filing date
Publication date
Application filed by Nippon Carbide Industries Co Inc filed Critical Nippon Carbide Industries Co Inc
Priority to JP2011518522A priority Critical patent/JP5566383B2/ja
Publication of WO2010143597A1 publication Critical patent/WO2010143597A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01Manufacture or treatment
    • H10W70/05Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65Shapes or dispositions of interconnections
    • H10W70/657Shapes or dispositions of interconnections on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1377Protective layers
    • H05K2203/1394Covering open PTHs, e.g. by dry film resist or by metal disc
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0044Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/284Applying non-metallic protective coatings for encapsulating mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/85Packages
    • H10H20/857Interconnections, e.g. lead-frames, bond wires or solder balls
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65Shapes or dispositions of interconnections
    • H10W70/654Top-view layouts
    • H10W70/655Fan-out layouts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present invention relates to a method for manufacturing a circuit board, a circuit board manufactured thereby, and a mother board for a circuit board used therefor.
  • a circuit board mother board having a plurality of circuit areas and capable of obtaining a plurality of circuit boards, a circuit board manufacturing method using the circuit mother board, and a circuit board manufacturing method using the circuit board mother board.
  • a circuit board manufacturing method capable of obtaining a circuit board in which castellation electrodes are appropriately exposed by a simple method, and a circuit board manufactured thereby, and The present invention relates to a circuit board mother board to be used.
  • circuit board is generally mounted on a mounting board in a state where electronic components are mounted.
  • the circuit board may have a castellation structure in order to appropriately solder the circuit board.
  • the castellation structure is a structure in which a concave portion is formed on the side surface of the substrate, and an electrode is formed on the wall surface of the concave portion, and this electrode is sometimes called a castellation electrode or simply castellation.
  • FIG. 1 is a cross-sectional view of a circuit board having a conventional castellation structure.
  • the circuit board 100 has a base 105 made of an insulating material.
  • the substrate 105 is provided with a wiring conductor 102 for connecting to the electronic component 101 on the front surface, and a wiring conductor 107 for connecting to the mounting substrate on which the circuit board 100 is mounted on the back surface.
  • the base body 105 is provided with through conductors (through holes, via holes, etc.) for connecting the wiring conductors 102 and 107 on the front surface and the back surface.
  • a castellation electrode 106 connected to the wiring conductor 107 on the back surface of the base 105 is provided on the side surface of the base 105.
  • the electronic component 101 installed on the base 105 is connected to the wiring conductor by a bonding wire or directly connected to the wiring conductor 102 as shown in FIG. Is hermetically protected.
  • circuit board 100 Since such a circuit board 100 is miniaturized as described above, in order to facilitate handling and increase productivity, a circuit board in which a large number of circuit areas are arranged vertically and horizontally and a large number of circuit boards can be obtained. It may be manufactured from a mother board. That is, in each circuit area of the circuit board mother board, after providing electronic components with wiring conductors and through conductors, divided into individual substrates along the dividing lines formed on the outer edge of each circuit area, Manufacturing circuit boards has been performed. When the circuit board has the castellation structure described above, a through hole is provided on a dividing line provided on the outer edge of each circuit area of the circuit board mother board, and the through hole is divided so that a caster is obtained. The formation of a ration electrode has been performed.
  • the sealing resin may enter the through hole and leak to the back surface of the circuit board mother board.
  • the sealing resin adheres to the inner wall surface of the through hole.
  • the castellation electrode of the circuit board is covered with the sealing resin, and the castellation electrode may not be properly exposed, so that proper soldering may not be performed.
  • the substrate has a multilayer structure as shown in FIG. 1, or a barrier layer is provided around the electronic component.
  • these methods are not preferable because the manufacturing process becomes complicated, and a simple method for preventing the sealing resin from leaking from the through hole is required.
  • the present invention provides a circuit board manufacturing method capable of obtaining a circuit board in which castellation electrodes are appropriately exposed by a simple method, a circuit board manufactured thereby, and a circuit used therefor
  • An object is to provide a mother board for a board.
  • a method for manufacturing a circuit board according to the present invention includes a preparation step of preparing a circuit board mother board having a plurality of circuit regions and a plurality of through holes, and an opening in each through hole.
  • the sealing composition is a glass composition
  • the glass paste is applied by applying a glass paste to the circuit board mother board. Further, it is preferable to fire the circuit board mother board.
  • the glass composition has high strength, according to such a circuit board mother board, when the circuit region is sealed with the sealing resin in the circuit sealing process, the sealing on the sealing composition is performed. Even if pressure is applied to the resin, the sealing resin can be prevented from entering the through hole. In addition, since the glass composition is brittle, it can be easily broken when the circuit board mother board is divided in the dividing step, and the circuit board can be easily manufactured. In addition, after dividing the glass composition, it is possible to produce a circuit board having a clean divided section and a good finish.
  • the sealing composition preferably has a thickness at a position in contact with an inner wall surface of the through hole larger than a thickness at a central portion in the radial direction of the through hole.
  • the sealing composition in the through hole has a thickest portion formed at a position in contact with the inner wall surface of the through hole.
  • the sealing composition in the through hole has a thinnest portion formed at a central portion in the radial direction of the through hole.
  • the sealing composition is easily divided at the central portion in the radial direction of the through hole, and the seal remaining on the circuit board.
  • the stopping composition can be made substantially the same for each circuit board, and a homogeneous circuit board can be obtained.
  • the circuit board mother board may be made of the ceramic.
  • the circuit board mother board may be a single-layer board.
  • circuit board of the present invention is manufactured by any one of the above-described circuit board manufacturing methods.
  • the castellation electrode can be appropriately exposed.
  • a circuit board mother board of the present invention has a plurality of circuit regions and a plurality of through holes, and is divided along the plurality of through holes. In each of the through holes, only one side of the opening is sealed with a sealing composition.
  • circuit board mother board since only one side of the opening in the through hole is sealed with the sealing composition, even when sealing a plurality of circuit regions with a sealing resin, It is possible to prevent the sealing resin from entering the through hole. And since the other side of the opening in the through hole is not sealed with the sealing composition, the wall surface is exposed. Therefore, by dividing the circuit board mother board along the plurality of through holes, a circuit board in which castellation electrodes are appropriately exposed can be obtained.
  • the sealing composition is preferably a glass composition.
  • the sealing resin penetrates into the through hole even when pressure is applied when the circuit area is sealed with the sealing resin. Can be prevented. Further, since the glass composition is brittle, according to such a circuit board mother board, it can be easily broken when the circuit board mother board is divided, and the circuit board can be easily manufactured. Can do. Further, after dividing the glass composition, the divided cross section is clean, and according to such a circuit board mother board, a circuit board having a good finish can be manufactured.
  • the sealing composition preferably has a thickness at a position in contact with an inner wall surface of the through hole larger than a thickness at a central portion in the radial direction of the through hole.
  • the contact area between the inner wall surface of the through hole and the sealing composition can be increased, and the sealing composition can be prevented from being unnecessarily peeled off. it can.
  • the sealing composition in the through hole has a thickest portion formed at a position in contact with the inner wall surface of the through hole.
  • the sealing composition can be most prevented from peeling off unnecessarily.
  • the sealing composition in the through hole has a thinnest part formed at the center in the radial direction of the through hole.
  • circuit board mother board when the circuit board mother board is divided, the sealing composition is easily divided at the central portion in the radial direction of the through hole, and the sealing composition remaining on the circuit board is reduced.
  • Each circuit board can be made substantially the same, and a uniform circuit board can be obtained.
  • dividing lines are formed along positions overlapping with the plurality of through holes.
  • circuit board mother board According to such a circuit board mother board, it is only necessary to divide the circuit board mother board along the dividing line, so that the circuit board mother board can be easily divided.
  • a dividing groove is formed on at least one surface along the dividing line.
  • the circuit board mother board can be easily divided by dividing the circuit board mother board along the dividing grooves.
  • the circuit board mother board may be made of ceramic.
  • the circuit board mother board may be a single-layer board.
  • a circuit board manufacturing method capable of obtaining a circuit board in which castellation electrodes are appropriately exposed by a simple method, and a circuit board manufactured thereby, and A mother board for a circuit board used therefor is provided.
  • FIG. 1 is a perspective view of a circuit board according to an embodiment of the present invention. It is a figure which shows the structure of the cross section in the surface which passes the castellation electrode of FIG. It is a side view in the vicinity of the castellation electrode of the circuit board of FIG. It is a figure which shows a mode that the electronic component was mounted in the circuit board and sealed with sealing resin. It is a figure which shows the mode of the castellation electrode with which the circuit board shown in FIG. 2 is mounted. It is a flowchart which shows the manufacturing method of a circuit board. It is a figure which shows the mode of the board
  • FIG. 2 is a perspective view of a circuit board manufactured by the circuit board mother board and the circuit board manufacturing method according to the present embodiment.
  • the circuit board 20 includes a substantially rectangular parallelepiped base 9, a circuit region 21 formed on one surface of the base 9, and a wiring conductor at least partially formed in the circuit region 21. 2, a castellation electrode 6 provided on the side surface of the substrate 9, a wiring conductor 7 formed on the other surface of the substrate 9, and a sealing composition 8 at least partially formed on the wiring conductor 2 And at least a sealing resin for sealing the circuit region 21 as a main configuration.
  • FIG. 3 is a diagram showing a cross-sectional structure in a plane passing through the castellation electrode 6 of FIG. 2 and 3, the sealing resin is omitted for easy understanding.
  • the base body 9 has a substantially rectangular parallelepiped shape as described above, and a plurality of a pair of side surfaces facing each other are cut into a substantially semicylindrical shape to form a recess.
  • a castellation electrode 6 is provided on the surface of each recess, and each castellation electrode 6 extends from one surface of the base 9 to the other surface along the recess. That is, the castellation electrode 6 has a shape in which the through hole is divided along the length direction of the hole, and has a concave shape with respect to the side surface of the base 9. Further, the castellation electrode 6 is connected to the wiring conductor 2 provided on one surface of the base 9, and is further connected to the wiring conductor 7 provided on the other surface of the base 9.
  • Each wiring conductor 2 connected to each castellation electrode 6 has a rectangular shape in which a part of the wiring conductor 2 is cut into an arc shape by a recess provided in the base 9 on one surface of the base 9. I am doing. Similarly, each of the wiring conductors 7 connected to the respective castellation electrodes 6 was partially cut into an arc shape by a recess provided in the base 9 on the other surface of the base 9. It has a rectangular shape.
  • the circuit region 21 is formed on one surface of the base 9, and at least a part of the wiring conductor 2 extends into the circuit region 21.
  • the circuit region 21 includes at least a wiring conductor 2 for connecting to an electronic component mounted on the circuit board 20, and further includes any of a wiring conductor, a through hole, and a via hole for connecting the circuit board and the mounting board. May have.
  • FIG. 4 is a side view in the vicinity of the castellation electrode 6 of the circuit board 20 of FIG.
  • a part of each wiring conductor 2 and a part of each castellation electrode 6 are covered with a sealing composition 8.
  • the sealing composition 8 is filled in the concave portions only on one surface side of each castellation electrode 6.
  • the sealing composition 8 which has entered the recess is the thinnest portion at the approximate center of the recess, and the thickness is a.
  • the sealing composition 8 is the thickest portion at the position in contact with the castellation electrode 6 and the thickness is b.
  • the sealing composition 8 has a thickness f on the wiring conductor 2.
  • FIG. 5 is a view showing a state in which the electronic component 1 is mounted on the circuit board 20 and sealed with the sealing resin 13.
  • the electronic component 1 is fixed on one surface of the base 9 by means (not shown), and is electrically connected to the wiring conductor 2 by a bonding wire 11.
  • the sealing resin 13 has a surface substantially parallel to the surface of the circuit board 20 formed in a substantially flat shape. The sealing resin 13 seals from the circuit region 21 of the circuit board 20 to the surface of the sealing composition 8.
  • FIG. 6 is a diagram showing a state of the castellation electrode on which the circuit board shown in FIG. 2 is mounted.
  • the circuit board 20 is disposed on the mounting board, and the terminals 12 of the mounting board, the wiring conductors 7 and the castellation electrodes 6 are connected by solder 15.
  • the solder may be sucked up to the wiring conductor 2 side of the circuit board 20 through the castellation electrode 6, but the solder 15 is used for the wiring of the circuit board 20 by the sealing composition 8. Reaching the conductor 2 is prevented. Therefore, according to such a circuit board 20, an unnecessary short circuit due to solder or the like is not required during mounting without having a complicated structure in which the base has a multilayer structure or a barrier layer is provided around the electronic component. Can be prevented.
  • FIG. 7 is a flowchart showing a method for manufacturing the circuit board 20.
  • the method of manufacturing the circuit board 20 includes a preparation step P1 for preparing a circuit board mother board having a plurality of circuit regions 21 and a plurality of through holes, and one of openings in each through hole.
  • Through-hole sealing step P2 for sealing only the side with the sealing composition 8
  • component placement step P3 for placing the electronic component 1 on the circuit region, and sealing each circuit region 21 with the sealing resin 13
  • a circuit sealing process P4 to be performed and a dividing process P5 for dividing the circuit board mother board along the plurality of through holes are provided as main processes.
  • the component placement step P3 is not necessary.
  • the preparation process P1 includes a substrate preparation process P1a, a drilling process P1b, and a conductor formation process P1c.
  • substrate preparation process P1a First, a substrate 31 serving as a base for a circuit board mother board is prepared. This substrate finally becomes the base 9 of the circuit board 20.
  • the material of the substrate 31 examples include materials used for general wiring substrates such as polyimide, glass epoxy, BT resin (registered trademark of Mitsubishi Gas Chemical Co., Ltd.), and ceramics.
  • substrate 31 it is preferable to use ceramics, such as an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body, glass ceramics, from a durable point.
  • the thickness of the substrate 31 in the present invention is not particularly limited, but is preferably 100 ⁇ m to 5,000 ⁇ m in view of strength and circuit board size.
  • the substrate 31 may be either a single layer substrate or a multilayer substrate, but it is preferable to use a single layer substrate from the viewpoint that the manufacturing process can be simplified.
  • the substrate 31 is preferably provided with a dividing line L so that the dividing operation is facilitated in the subsequent dividing step P5.
  • the dividing line indicates a position where the circuit board mother board having the plurality of circuit areas 21 is divided into individual circuit areas in the dividing step P5.
  • a plurality of through holes 32 are formed in the prepared substrate 31 for forming a plurality of through holes.
  • the through hole 32 is opened on the dividing line L so that the center is located.
  • the through hole 32 can be formed in the substrate by punching, drilling, laser processing, or the like.
  • a part of substrate preparation process P1a and a part of drilling process P1b can be performed simultaneously.
  • the substrate 31 having a plurality of through holes 32 is formed by punching through holes in the green sheet before firing, and then firing the punched holes.
  • the sintered alumina substrate can be drilled with the through holes 32 by laser or drilling. In this way, a substrate 31 having a plurality of through holes 32 shown in FIG. 8 is obtained.
  • a conductor is formed around the through hole 32 on the side surface of the through hole 32 and the surface of the substrate 31 formed by the drilling step P1b.
  • the conductive material for forming the through hole and the wiring conductors 2 and 7 is not particularly limited, but tungsten (W), molybdenum (Mo), nickel (Ni), copper (Cu), silver (Ag), gold Metals such as (Au), palladium (Pd), and platinum (Pt) can be used.
  • the conductor can be formed by being deposited on the substrate 31 by plating, printing, vapor deposition, or the like.
  • the thickness of the conductor is preferably 1 to 30 ⁇ m.
  • a metal having excellent corrosion resistance such as Ni, Au, Pt or the like on the surface of the conductor to a thickness of about 1 to 20 ⁇ m.
  • the material of such a sealing composition is not particularly limited, and examples thereof include conductive materials such as metals, and insulating materials such as glass and insulating resin. Among them, insulating materials are used. It is particularly preferable to use a glass composition from the viewpoint of workability and durability.
  • a thermoplastic resin or a thermosetting resin may be used.
  • a thermoplastic resin is used as the sealing composition, the resin plasticized by heating is applied from one opening side of the through hole and then solidified by cooling to seal the through hole Can do.
  • a thermosetting resin is used as the sealing composition, an uncured resin is applied from one opening side of the through hole and then solidified by heating to seal the through hole. be able to.
  • the insulating resin When such an insulating resin is used as the sealing composition, the insulating resin is constant so that the insulating resin does not flow down to the opposite side of the substrate through the through hole when the insulating resin is applied. It adjusts so that it may have the following viscosity.
  • a glass paste containing glass powder, a binder, a solvent, etc. is applied from one opening side of the through hole, and then dried and solidified to seal the through hole. can do.
  • the glass paste can contain fillers such as silicon oxide and alumina.
  • FIG. 11 is a view showing a state of a cross section in the through hole of the circuit board mother board 30 of FIG. Specifically, FIGS. 11A to 11C show states in which the shape of the sealing composition 8 in the cross section of the through hole is different, and FIG. 11A shows the sealing composition 8. 11 (B) shows a state where the bottom surface of the sealing composition 8 is lowered, and FIG. 11 (C) shows a state where the sealing composition 8 is a through-hole. Shown off center.
  • the inner wall surface of the through hole 32 provided in the dividing line L and the substrate 31 ( The distance c that is farthest from the outer peripheral surface of the conductor of the through hole is preferably 50 to 300 ⁇ m. If the maximum distance between the dividing line L and the inner wall surface of the through hole 32 is 50 ⁇ m or more, the through hole 32 is prevented from being sealed with a conductor that forms a through hole in the conductor forming step P1c. If the through hole 32 is sealed with a conductor that forms a through hole, the through hole conductor may be peeled off from the substrate when the circuit board mother board 30 is divided in the subsequent division step P5. Absent. On the other hand, if the maximum distance between the dividing line L and the inner wall surface of the through hole is 300 ⁇ m or less, it is preferable because the through hole can be more appropriately sealed with the sealing composition 8 in the through hole sealing step P2.
  • the thinnest portion a of the sealing composition 8 in the through hole is preferably 5 to 500 ⁇ m thick. If the thinnest part a of the sealing composition 8 that seals the through hole is 5 ⁇ m or more, the sealing composition is applied when applying a sealing resin that hermetically protects electronic components and the like in the subsequent circuit sealing step P4. It is possible to appropriately prevent the thinnest part of the object 8 from breaking. On the other hand, if the thinnest part a of the sealing composition 8 for sealing the through hole is 500 ⁇ m or less, it is preferable because the circuit board mother board 30 can be easily divided in the subsequent dividing step P5.
  • the thinnest part a of the sealing composition 8 for sealing the through-hole is to divide the circuit board mother board 30 into each circuit area as shown in FIGS. In order to facilitate, it is preferable that it exists in the vicinity of the dividing line L, and it is more preferable that it exists on the dividing line.
  • the thickest portion b of the sealing composition 8 for sealing the through hole is preferably in the vicinity of the inner wall portion of the through hole. b is preferably present at a position in contact with the inner wall surface of the through hole. If the thickest part b of the sealing composition 8 is present at a position in contact with the inner wall surface of the through hole, the contact area between the sealing composition 8 and the inner wall surface of the through hole is increased. Adhesion with the inner wall surface of the hole can be increased, and the sealing composition 8 can be prevented from peeling off from the inner wall surface of the through-hole when the circuit board mother board 30 is divided in the subsequent dividing step P5. Can do.
  • the sealing composition 8 adhering in the through hole is 1% or more of the through hole in the depth direction, the sealing composition 8 and the inner wall surface of the through hole Adhesion can be sufficiently secured. Therefore, in the circuit sealing step P4, when applying a sealing resin that hermetically protects electronic components and the like, it is possible to more appropriately prevent the sealing composition 8 from dropping from the inner wall surface of the through hole. Furthermore, in the dividing step P5, it is possible to more appropriately prevent the sealing composition 8 from peeling from the inner wall surface of the through hole when the circuit board mother board 30 is divided. On the other hand, if the sealing composition 8 adhering in the through hole is 85% or less of the through hole in the depth direction, the castellation electrode 6 of the circuit board 20 is more sufficiently formed after the dividing step P5. Can be exposed to.
  • the sealing composition 8 is preferably attached to the inner wall surface of the 5 to 500 ⁇ m through hole in the depth direction from the end of the through hole. As shown in FIG. 2, if the sealing composition 8 filled in the through hole adheres to the opening from one side of the through hole by 5 ⁇ m or more, the sealing composition 8 and the inner wall surface of the through hole Adhesion can be sufficiently secured. Therefore, in the circuit sealing step P4, when applying a sealing resin that hermetically protects electronic components and the like, it is possible to more appropriately prevent the sealing composition from dropping from the inner wall surface of the through hole. In the dividing step P5, it is possible to more appropriately prevent the sealing composition 8 from being peeled off from the inner wall surface of the through hole when the circuit board mother board 30 is divided.
  • the caster of the circuit board 20 is obtained after the dividing step P5.
  • the exposure electrode 6 can be exposed more sufficiently.
  • the portion where the depth of the sealing composition 8 filled in the through hole is maximum is preferably in the vicinity of the inner wall portion of the through hole. Further, as shown in FIG. It is preferable that the portion where the depth of the sealing composition 8 filled in the hole is maximum coincides with the thickest portion b of the sealing composition 8 that seals the through hole. In this case, the adhesiveness between the sealing composition 8 and the inner wall surface of the through hole is increased, and the sealing composition 8 is peeled off from the inner wall portion of the through hole when the circuit board mother board 30 is divided in the dividing step P5. Can be prevented.
  • the sealing composition 8 for sealing the through holes is provided so as to cover a part of the wiring conductor 2 on the surface of the circuit board mother board 30. It is desirable. By covering a part of the wiring conductor 2 with the sealing composition 8, the adhesion between the sealing resin for sealing the circuit region 21 and the wiring conductor 2 is improved, and the sealing resin is prevented from peeling off. Can do. In particular, when the surface of the wiring conductor 2 is Au, the adhesiveness between the sealing resin and the wiring conductor 2 can be remarkably improved by covering a part of the wiring conductor 2 with the sealing composition 8.
  • Part placement process P3 when it is necessary to arrange an electronic component in the circuit area 21, the electronic component is arranged.
  • the terminal of the electronic component and the wiring conductor 2 are electrically connected.
  • the terminal of the electronic component and the wiring conductor 2 may be connected by wire bonding, and the terminal of the electronic component is placed on the wiring conductor 2 to form a conductive paste. You may connect with solder.
  • circuit sealing process P4 Next, the circuit region 21 is sealed with a sealing resin.
  • the resin used for the sealing resin include thermoplastic resins, thermosetting resins, and ultraviolet curable resins. Specifically, epoxy resins, silicone resins, polyolefin resins, polyamide resins, Examples thereof include resins such as polyimide resins and urethane resins.
  • the circuit area 21 is sealed by applying a thermoplastic resin that has been heated and plasticized to the circuit area 21, and then cooling and solidifying.
  • the circuit region 21 is sealed by applying an uncured thermosetting resin to the circuit region 21 and then solidifying by heating.
  • an ultraviolet curable resin which is a precursor of the ultraviolet curable resin, is applied to the circuit region 21 and then solidified by irradiation with ultraviolet rays, thereby sealing the circuit region 21. Do. Thus, a circuit board mother board in which the circuit region 21 is sealed with the sealing resin is obtained.
  • division process P5 Next, only one side of the through hole 32 of the through hole divides the circuit board mother board 30 sealed with the sealing composition 8.
  • the division may be divided into a plurality of circuit regions by laser or dicing so as to pass through the through holes.
  • the circuit board mother board 30 When the circuit board mother board 30 is divided, it may be divided along the dividing line L by laser or dicing as described above. Further, it is preferable that a dividing groove is formed along the dividing line L on at least one surface of the circuit board mother board 30.
  • the substrate 31 having the dividing grooves may be prepared in the substrate preparation step P1a.
  • a method of dividing in the case where the dividing grooves are provided in this way there is a method of breaking the circuit board mother board 30 along the provided dividing grooves.
  • the circuit board 20 shown in FIG. 2 is obtained by dividing the circuit board mother board 30 into the respective circuit boards 20.
  • Example 1 A circuit board for mounting electronic components was manufactured as follows. As a substrate, an alumina substrate (Hokuriku Ceramic Co., Ltd.) having V-shaped dividing grooves with a depth of 0.15 mm provided as dividing lines at intervals of 5 mm and having a through hole of ⁇ 0.3 mm formed on the dividing lines in advance. Manufactured: alumina purity 96%, thickness 0.5 mm, size 60 mm ⁇ 70 mm). A conductor paste (manufactured by Kyoto Elex, grade name “DD1130”) was applied by screen printing at a position where the wiring conductor and through-hole conductor of the alumina substrate were provided.
  • alumina substrate Hokuriku Ceramic Co., Ltd.
  • a conductor paste manufactured by Kyoto Elex, grade name “DD1130” was applied by screen printing at a position where the wiring conductor and through-hole conductor of the alumina substrate were provided.
  • the through-hole conductor was applied while sucking from the surface opposite to the surface to be printed of the substrate during screen printing.
  • the substrate is dried at a temperature of 50 ° C. for 10 minutes, and then fired by holding the substrate at a maximum temperature of 850 ° C. for 10 minutes to obtain a mother board for a circuit board having a silver wiring conductor having a thickness of 12 ⁇ m.
  • a substrate was produced.
  • a glass paste (made by Asahi Glass Co., grade name “AP5700”) is applied to the position where the sealing composition for the substrate is provided (including the position where the opening of the through hole is formed), and the temperature is 150 ° C. Dry for 20 minutes. Thereafter, the substrate was fired by raising the temperature and holding it at a maximum temperature of 850 ° C. for 10 minutes to obtain a mother board for circuit board on which a glass layer having a thickness of 35 ⁇ m was formed as a sealing composition.
  • the substrate was free of burrs, and the glass layer was almost split in the center of the through-hole and had good splitting ability. Met. Furthermore, when the divided cross section was observed with a microscope, it was confirmed that the through hole was sealed from one side by the glass layer.
  • Example 2 The ceramic plate used as the base was the same as in Example 1 except that a substrate having a thickness of 0.3 mm, a through-hole diameter of 0.2 mm, and a V-shaped dividing groove interval of 3 mm was used. Thus, a circuit board mother board was produced. When this substrate was divided into circuit substrates along the V-shaped dividing grooves, there was no burr on the substrate, and the glass also had good crack division at the center of the through hole.
  • an LED was mounted as an electronic component on the circuit board mother board produced in Example 1 and Example 2, and connected to the wiring conductor with a bonding wire.
  • the epoxy sealing resin was mold printed to seal the LED.
  • the mother board was divided for a circuit board along a V-shaped dividing groove, and the divided cross section was observed with a microscope. As a result, it was confirmed that no adhesion of the epoxy-based sealing resin was observed at the site serving as the castellation electrode, and leakage of the sealing resin was prevented by the glass layer. Furthermore, when the circuit board was soldered to the mounting board, a good solder fillet was formed.
  • a circuit board manufacturing method capable of obtaining a circuit board in which castellation electrodes are appropriately exposed by a simple method, a circuit board manufactured thereby, and a circuit used therefor A mother board for a substrate is provided.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structure Of Printed Boards (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

La présente invention a trait à un procédé de fabrication de cartes de circuit imprimé, au moyen duquel une carte de circuit imprimé dotée d'une électrode crénelée exposée de façon appropriée à partir de celle-ci peut être obtenue à l'aide d'un procédé simple. La présente invention a également trait à la carte de circuit imprimé fabriquée au moyen du procédé et au substrat de base utilisé pour la carte de circuit imprimé. Le substrat de base (30) destiné à la carte de circuit imprimé est pourvu d'une pluralité de régions de circuit et d'une pluralité de trous traversants et est divisé le long des trous traversants. Chaque trou traversant n'est scellé que d'un côté de l'ouverture au moyen d'une composition d'étanchéité (8). Par conséquent, y compris si la pluralité de régions de circuit est scellée au moyen de la résine d'étanchéité, il est fait en sorte que cette résine d'étanchéité n'entre pas dans les trous traversants.
PCT/JP2010/059569 2009-06-08 2010-06-06 Procédé de fabrication d'une carte de circuit imprimé, carte de circuit imprimé fabriquée au moyen du procédé et substrat de base utilisé pour la carte de circuit imprimé Ceased WO2010143597A1 (fr)

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