WO2011065687A2 - Cellule solaire cristallisée faisant intervenir une couche de semi-conducteur microcristalline et procédé de production associé - Google Patents

Cellule solaire cristallisée faisant intervenir une couche de semi-conducteur microcristalline et procédé de production associé Download PDF

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Publication number
WO2011065687A2
WO2011065687A2 PCT/KR2010/007868 KR2010007868W WO2011065687A2 WO 2011065687 A2 WO2011065687 A2 WO 2011065687A2 KR 2010007868 W KR2010007868 W KR 2010007868W WO 2011065687 A2 WO2011065687 A2 WO 2011065687A2
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Prior art keywords
semiconductor layer
solar cell
layer
silicon layer
amorphous silicon
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English (en)
Korean (ko)
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WO2011065687A3 (fr
Inventor
이시우
이유진
김동제
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TG Solar Corp
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TG Solar Corp
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Priority claimed from KR1020090113758A external-priority patent/KR101084650B1/ko
Priority claimed from KR1020090116094A external-priority patent/KR101084652B1/ko
Application filed by TG Solar Corp filed Critical TG Solar Corp
Publication of WO2011065687A2 publication Critical patent/WO2011065687A2/fr
Publication of WO2011065687A3 publication Critical patent/WO2011065687A3/fr
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/16—Material structures, e.g. crystalline structures, film structures or crystal plane orientations
    • H10F77/162—Non-monocrystalline materials, e.g. semiconductor particles embedded in insulating materials
    • H10F77/164—Polycrystalline semiconductors
    • H10F77/1642—Polycrystalline semiconductors including only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/17—Photovoltaic cells having only PIN junction potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/16—Material structures, e.g. crystalline structures, film structures or crystal plane orientations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/16—Material structures, e.g. crystalline structures, film structures or crystal plane orientations
    • H10F77/162—Non-monocrystalline materials, e.g. semiconductor particles embedded in insulating materials
    • H10F77/164—Polycrystalline semiconductors
    • H10F77/1642—Polycrystalline semiconductors including only Group IV materials
    • H10F77/1645—Polycrystalline semiconductors including only Group IV materials including microcrystalline silicon
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/545—Microcrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/546—Polycrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/548—Amorphous silicon PV cells

Definitions

  • the present invention relates to a solar cell crystallized using a microcrystalline semiconductor layer and a method of manufacturing the same. More specifically, the present invention relates to a polycrystalline solar cell capable of crystallizing an amorphous semiconductor layer at low temperature (for example, 600 degrees or less) using a microcrystalline semiconductor layer, and a method of manufacturing the same.
  • a solar cell using amorphous silicon has a very low diffusion length of a carrier compared to monocrystalline silicon or polycrystalline silicon (p-si) due to the characteristics of the amorphous silicon material itself. Therefore, when the amorphous silicon (a-Si) solar cell is manufactured with a pn junction structure, the collection efficiency of electron-hole pairs generated by light is very low, and deterioration occurs after prolonged exposure to light. As time goes by, the photoelectric conversion efficiency is lowered.
  • an amorphous silicon pin structure formed between p-type and n-type having a high impurity doping concentration by using an intrinsic semiconductor layer containing no impurity as a light absorbing layer, and heat treatment at high temperature For example, a solar cell having a polycrystalline silicon pin structure which crystallizes to polycrystalline silicon (p-si) at 600 degrees or more has been proposed.
  • a depletion region is formed at the junction between the i-layer, which is a light absorbing layer, and the p-layer and the n-layer, which have a high impurity doping concentration, to generate an electric field therein. Therefore, the electron-hole pair generated by the incident light in the i layer is a drift in which electrons (-) move to the n-type silicon layer and holes (+) move to the p-type silicon layer according to the internal electric field, not diffusion. Current can flow.
  • the heat treatment temperature is required to be higher than 600 degrees at the time of crystallization of the amorphous silicon, the substrate is deformed (for example, the warpage of the substrate) during the heat treatment process and impurities are formed in the silicon layer (especially, optical Diffused into the absorption layer), thereby lowering the photoelectric conversion efficiency.
  • ⁇ c-Si microcrystalline Si
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • the present invention has been made to solve the above problems of the prior art, and provides a solar cell and a method of manufacturing the same that can easily crystallize the amorphous semiconductor even at low temperatures by using the characteristics of the microcrystalline semiconductor. have.
  • Another object of the present invention is to provide a solar cell and a method of manufacturing the same, which may have grain boundaries grown in the same direction as the direction of movement of electrons and holes generated in the light absorption layer.
  • Another object of the present invention is to provide a solar cell and a method of manufacturing the same, which can improve the photoelectric conversion efficiency by efficiently controlling the crystallization of the amorphous semiconductor layer.
  • Another object of the present invention is to provide a solar cell and a method of manufacturing the same, which can crystallize only the upper optoelectronic device by using characteristics of a microcrystalline semiconductor among multiple photoelectric devices.
  • the photoelectric conversion efficiency of the solar cell can be improved by forming grain boundaries in the same direction as the direction of movement of electrons and holes generated in the light absorbing layer to improve the mobility of electrons and holes.
  • only the upper photoelectric device of the multi-junction photoelectric device can be crystallized to polycrystalline silicon having excellent characteristics even at low temperature by using fine crystalline silicon.
  • FIG. 1 to 5 are views illustrating a manufacturing process of a solar cell crystallized using the microcrystalline semiconductor layer according to the first embodiment of the present invention.
  • FIGS. 6 to 10 are views illustrating a manufacturing process of a stacked solar cell crystallized using the microcrystalline semiconductor layer according to the second embodiment of the present invention.
  • 300, 300P Optoelectronic device (lower optoelectronic device)
  • first amorphous silicon layer (lower first amorphous silicon layer)
  • third amorphous silicon layer (lower third amorphous silicon layer)
  • the object of the present invention is a substrate; A lower electrode formed on the substrate; An optoelectronic device formed on the lower electrode and including a polycrystalline semiconductor layer having a grain boundary grown in the same direction as the movement direction of electrons or holes; And it is achieved by a solar cell comprising an upper electrode formed on the optoelectronic device.
  • the above object of the present invention (a) forming a microcrystalline semiconductor layer between the stacked amorphous semiconductor layer; And (b) forming a photovoltaic device comprising a polycrystalline semiconductor layer formed by crystallizing at least a portion of the microcrystalline semiconductor layer and the amorphous semiconductor layer by performing a heat treatment process. It is also achieved by the method.
  • the step (a) (a1) forming a first amorphous semiconductor layer on the lower electrode on the substrate; (a2) forming a lower second amorphous semiconductor layer on the first amorphous semiconductor layer; (a3) forming the microcrystalline semiconductor layer on the lower second amorphous semiconductor layer; (a4) forming an upper second amorphous semiconductor layer on the microcrystalline semiconductor layer; And (a5) forming a third amorphous semiconductor layer on the upper second amorphous semiconductor layer.
  • silicon (Si) most commonly used as a material of a semiconductor layer is described as an example, but the present invention is not limited thereto, and known materials having semiconductor characteristics may be used without limitation.
  • FIG. 1 to 5 are views illustrating a manufacturing process of a solar cell crystallized using the microcrystalline semiconductor layer according to the first embodiment of the present invention.
  • a substrate 100 may be provided.
  • the material of the substrate 100 may be a transparent glass substrate, but is not necessarily limited thereto.
  • the substrate 100 may be formed of a transparent material such as glass or plastic, silicon, or metal [eg, SUS (Stainless) according to a direction in which a solar cell receives light. Steel)] can be used for all opaque materials.
  • roughness may be formed by performing a texturing process on the surface of the substrate 100.
  • the texturing is to prevent the phenomenon that the characteristic is degraded by the optical reflection of light incident on the substrate surface of the solar cell is reflected. That is, forming a roughness pattern on the substrate surface by making the surface of the substrate rough.
  • the surface of the substrate is roughened by texturing, the light reflected once from the surface may be reflected back toward the solar cell, thereby reducing the loss of light and increasing the amount of light trapping, thereby improving the photoelectric conversion efficiency of the solar cell. You can.
  • the texturing process may be performed by using a sand blasting method, which includes both dry blasting for spraying etching particles with compressed air and wet blasting for spraying etching particles with liquid.
  • Etching particles used in sand blasting can be used without limitation, such as sand, small metals, particles that can form irregularities on the substrate by physical impact.
  • the texturing process may be omitted if necessary.
  • an antireflection layer (not shown) may be formed on the substrate 100.
  • the anti-reflection layer may serve to prevent a phenomenon in which solar light incident through the substrate 100 is not absorbed by the silicon layer and is directly reflected to the outside, thereby lowering the efficiency of the solar cell.
  • the material of the anti-reflection layer may be silicon oxide (SiO x ) or silicon nitride (SiN x ), which are transparent insulating layers, but are not limited thereto.
  • the method of forming the reflective ring layer may include chemical vapor deposition (CVD), such as Low Pressure Chemical Vapor Deposition (LPCVD) and Plasma Enhanced Chemical Vapor Deposition (PECVD). Can be.
  • CVD chemical vapor deposition
  • LPCVD Low Pressure Chemical Vapor Deposition
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • a lower electrode 200 of a conductive material may be formed on the substrate 100.
  • the material of the lower electrode 200 may use a transparent conductive oxide (TCO) having low contact resistance and transparent properties.
  • TCO transparent conductive oxide
  • the transparent electrode TCO may be any one of AZO (ZnO: Al), ITO (Indium-Tin-Oxide), GZO (ZnO: Ga), BZO (ZnO: B), and FTO (SnO 2 : F). have.
  • the lower electrode 200 may be formed using physical vapor deposition (PVD), LPCVD, PECVD, metal organic chemistry such as thermal evaporation, e-beam evaporation, and sputtering.
  • PVD physical vapor deposition
  • PECVD PECVD
  • metal organic chemistry such as thermal evaporation, e-beam evaporation, and sputtering.
  • MOCVD Metal Organic Chemical Vapor Deposition
  • p-type, i-type, n-type (particularly, p + type, i-type, n + type), n-type, i-type, p-type (particularly, n + type, type i, p +), p, n, n (especially p +, p-, n +) or n, n, p (especially n +, n-, p +)
  • a silicon layer having a conductivity type of can be formed in this order.
  • n + is higher doped than n-. If there is no indication of + or-, there is no particular restriction on the doping concentration.
  • An i-type silicon layer located between p-type and n-type functions as a light absorbing layer.
  • p-type, i-type, and n-type silicon layers 310, 320, and 330 are sequentially formed on the lower electrode 200.
  • the p-type first amorphous silicon layer 310 is formed on the lower electrode 200, and then the i-type second amorphous silicon layer 320 is formed on the first amorphous silicon layer 310.
  • an n-type third amorphous silicon layer 330 may be formed on the second amorphous silicon layer 320 to form one optoelectronic device 300.
  • a fine crystalline silicon layer 322 is further formed between the 2-1 amorphous silicon layer 321 and the 2-2 amorphous silicon layer 323.
  • the 2-1 amorphous silicon layer 321 is formed on the first amorphous silicon layer 310, and then the fine crystalline silicon layer 322 is formed on the 2-1 amorphous silicon layer 321.
  • the second-2 amorphous silicon layer 323 may be formed on the microcrystalline silicon layer 322.
  • the microcrystalline silicon layer 322 may function to induce crystallization of adjacent amorphous silicon layers 321 and 323.
  • the fine crystalline silicon layer 322 is not limited to the above-described arrangement, and between the first amorphous silicon layer 310 and the second amorphous silicon layer 320, or the second amorphous silicon layer 320 and the first It may be formed between the three amorphous silicon layer 330.
  • the first 310, the second 320 (321, 323) and the third amorphous silicon layer 330 and the microcrystalline silicon layer 322 may be preferably formed using PECVD.
  • SiH 4 (or Si 2 H 6 ) which is a source gas, is formed. It can be formed by adjusting the mixing ratio of H 2 as an auxiliary gas. That is, the ratio of H 2 to SiH 4 (or Si 2 H 6 ) may be decreased (H 2 may be 0) to form the 2-1 and 2-2 amorphous silicon layers 321 and 323.
  • the ratio of H 2 to SiH 4 may be increased to form the microcrystalline silicon layer 322.
  • the technique for controlling the crystallinity of the silicon layer formed by adjusting the mixing ratio of the source gas and the auxiliary gas in PECVD is a known method, detailed description thereof will be omitted.
  • the first, second and third amorphous silicon layer (310, 320, 330) when forming the first, second and third amorphous silicon layer (310, 320, 330) by PECVD, it is preferable to use an in situ method that proceeds sequentially in a single process in a single chamber.
  • the first, second and third amorphous silicon layers 310, 320, and 330, which constitute the optoelectronic device 300 are formed without being exposed to the external environment, the reliability of the solar cell is improved.
  • the manufacturing process is simplified and the manufacturing time is shortened to increase the productivity of the solar cell.
  • the microcrystalline silicon layer 322 may be crystallized into the polycrystalline silicon layer 322P by performing a heat treatment process at a predetermined temperature.
  • the microcrystalline silicon has a microstructure in the middle of the amorphous silicon and polycrystalline silicon.
  • fine crystalline silicon can be crystallized into polycrystalline silicon at a lower temperature than amorphous silicon.
  • the temperature for crystallizing amorphous silicon is 600 ° C. or more
  • the fine crystalline silicon may be crystallized to polycrystalline silicon even at a low temperature of 600 ° C. or less (eg, 550 ° C.).
  • the 2-1 and 2-2 amorphous silicon layers 321 and 323 and the microcrystalline silicon layer 322 may be formed.
  • the 2-1 and 2-2 amorphous silicon layers 321 and 323 may also be sequentially crystallized around the interface to become the 2-1 and 2-2 polycrystalline silicon layers 321P and 323P.
  • the second amorphous silicon layer 320 is grown in the direction perpendicular to the interface.
  • the process may be the first polycrystalline silicon layer 310P and the third polycrystalline silicon layer 330P. That is, the first, second, and third amorphous silicon layers 310, 320, and 330 may be formed into the first, second, and third polycrystalline silicon layers 310P, even by a low temperature heat treatment of 600 ° C. or lower, using fine crystalline silicon as a seed. 320P, 330P) layer can be crystallized. Therefore, deformation of the substrate 100 due to high temperature heat treatment (for example, warpage of the substrate) can be prevented.
  • high temperature heat treatment for example, warpage of the substrate
  • the first amorphous silicon layer 310 and the third amorphous silicon layer 330 are separately provided.
  • the metal layer (not shown) may be formed so that the first amorphous silicon layer 310 and the third amorphous silicon layer 330 may be crystallized by a metal induced crystallization (MIC) method.
  • MIC metal induced crystallization
  • the component of the metal layer may include any one of Ni, Al, Ti, Ag, Au, Co, Sb, Pd, Cu, or a combination of two or more thereof.
  • the metal layer may be formed by a low pressure chemical vapor deposition method, a plasma chemical vapor deposition method, an atomic unit layer deposition method, a sputtering method, or the like. Since the method of crystallizing amorphous silicon by the metal-induced crystallization method is a known technique, a detailed description thereof will be omitted herein.
  • the upper electrode 500 of the conductive material may be formed on the photoelectric device 300P including the first, second, and third polycrystalline silicon layers 310P, 320P, and 330P. have.
  • the material of the upper electrode 500 may be a transparent electrode (TCO), or may include copper (Cu), aluminum (Al), titanium (Ti), silver (Ag), and alloys thereof, which are conventional conductive materials. It is not limited to this.
  • the method of forming the upper electrode 500 may include a physical vapor deposition method such as sputtering and a chemical vapor deposition method such as LPCVD, PECVD, and MOCVD.
  • the polycrystalline silicon solar cell 10 having excellent photoelectric conversion efficiency, reliability, and productivity using the microcrystalline silicon layer may be implemented.
  • a tandem solar cell refers to a structure in which photovoltaic devices are stacked in a multi junction, and in the following description, a tandem solar cell stacked in a double junction is described. Although the description will be made in the center, the present invention is not limited thereto, and the concept may include a solar cell having a laminated structure of triple junction or more.
  • the present embodiment is different from the first embodiment in that it is a double-junction stacked solar cell, and the description of this embodiment will be omitted.
  • FIGS. 6 to 10 are views illustrating a manufacturing process of a stacked solar cell crystallized using the microcrystalline semiconductor layer according to the second embodiment of the present invention.
  • a substrate 100 is provided, and a lower electrode 200 is formed on the substrate 100.
  • p-type, i-type, and n-type silicon layers 310, 320, and 330 are sequentially formed on the lower electrode 200.
  • the p-type lower first amorphous silicon layer 310 is formed on the lower electrode 200
  • the i-type lower second amorphous silicon layer is formed on the lower first amorphous silicon layer 310.
  • a lower photovoltaic device in which the lower silicon layers 310, 320, and 330 are stacked by forming an n-type lower third amorphous silicon layer 330 on the lower second amorphous silicon layer 320. 300 can be configured.
  • p-type, i-type, and n-type silicon layers 410, 420, and 430 are sequentially formed on the lower photoelectric device 300.
  • the p-type upper first amorphous silicon layer 410 is formed on the lower photoelectric device 300, and then the i-type upper second amorphous silicon is formed on the upper first amorphous silicon layer 410.
  • the device 400 may be configured.
  • a fine crystalline silicon layer 422 is further added between the upper 2-1 amorphous silicon layer 421 and the upper 2-2 amorphous silicon layer 423.
  • the upper 2-1 amorphous silicon layer 421 is formed on the lower third amorphous silicon layer 330, and then the fine crystalline silicon layer is formed on the upper 2-1 amorphous silicon layer 421.
  • 422 may be formed, and then an upper second-second amorphous silicon layer 423 may be formed on the microcrystalline silicon layer 422.
  • the microcrystalline silicon layer 422 may function to induce crystallization of adjacent amorphous silicon layers 421 and 423.
  • the microcrystalline silicon layer 422 is not limited to the above-described arrangement, and is disposed between the upper first amorphous silicon layer 410 and the upper second amorphous silicon layer 420 or the upper second amorphous silicon layer 420. ) And the upper third amorphous silicon layer 430 may be formed.
  • the microcrystalline silicon layer 422 may be crystallized into the polycrystalline silicon layer 422P by performing a heat treatment process at a predetermined temperature.
  • the microcrystalline silicon may be crystallized into polycrystalline silicon at a low temperature (for example, 550 ° C) of 600 ° C. or less as in the first embodiment, and in this process, the microcrystalline silicon may be seeded for crystallization of amorphous silicon. seed) to act on the interface between the upper 2-1 and upper 2-2 amorphous silicon layers 421 and 423 and the microcrystalline silicon layer 422, and the upper 2-1 and upper 2-2 amorphous layers.
  • the silicon layers 421 and 423 may also be sequentially crystallized to become the 2-1 and 2-2 polycrystalline silicon layers 421P and 423P.
  • the upper first amorphous silicon layer 410 and the upper third amorphous silicon layer 430 may be continuously formed according to the degree of performance (eg, the heat treatment time) of the heat treatment process of FIG. 8. Crystallization may proceed to form the upper first polycrystalline silicon layer 410P and the upper third polycrystalline silicon layer 430P. That is, the upper first, upper second, and upper third amorphous silicon layers 410, 420, and 430 may be formed of the upper first, upper second, and upper third layers even at a low temperature heat treatment of 600 ° C. or lower using fine crystalline silicon as a seed. Crystallization may be performed using the polycrystalline silicon layers 410P, 420P, and 430P.
  • a transparent conductor is formed between the lower optoelectronic device 300 and the upper optoelectronic device 400, and more specifically, between the lower third amorphous silicon layer 330 and the upper first amorphous silicon layer 410.
  • a blocking layer (not shown) may be further formed. In the blocking layer, crystallization using the fine crystalline silicon layer 422 as a seed proceeds only to the upper first amorphous silicon layer 410, and the layer below the lower third amorphous silicon layer 330, that is, the lower photoelectric device 300.
  • Amorphous silicon layers 310, 320, and 330 constituting the block serves to block the progress of crystallization.
  • the blocking layer may make an ohmic contact between the lower third amorphous silicon layer 330 and the upper first polycrystalline silicon layer 410P, and as a result, improve the photoelectric conversion efficiency of the solar cell. It may be.
  • the blocking layer is preferably AZO (ZnO: Al) in which a small amount of Al is added to ZnO, but is not necessarily limited thereto, and transparent conductive materials such as conventional ITO, ZnO, IZO, FTO (SnO 2 : F), and BZO. Can be used without any special restrictions.
  • an upper electrode 500 of a conductive material is formed on the upper photoelectric device 400P.
  • a tandem polycrystalline silicon solar cell 20 having a double junction structure having excellent photoelectric conversion efficiency, reliability, and productivity may be implemented using the microcrystalline silicon layer as in the first embodiment.

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Abstract

L'invention concerne une cellule solaire cristallisée faisant intervenir une couche de semi-conducteur microcristalline et un procédé de production pour ladite cellule solaire. La cellule solaire décrite faisant intervenir une couche de semi-conducteur microcristalline est pourvue : d'un substrat (100) ; d'une électrode inférieure (200) qui est formée sur le substrat (100) ; d'un élément photoélectrique (300) qui comprend une couche de semi-conducteur polycristalline (320) qui est formée sur l'électrode inférieure (200) et qui comporte des particules cristallines (30) s'étendant dans la même direction que la direction de mouvement des électrons ou des trous d'électrons ; et d'une électrode supérieure (500) qui est formée sur l'élément photoélectrique (300).
PCT/KR2010/007868 2009-11-24 2010-11-09 Cellule solaire cristallisée faisant intervenir une couche de semi-conducteur microcristalline et procédé de production associé Ceased WO2011065687A2 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR1020090113758A KR101084650B1 (ko) 2009-11-24 2009-11-24 미세 결정질 반도체층을 이용하여 결정화된 태양전지 및 그 제조방법
KR10-2009-0113758 2009-11-24
KR1020090116094A KR101084652B1 (ko) 2009-11-27 2009-11-27 미세 결정질 반도체층을 이용하여 결정화된 적층형 태양전지 및 그 제조방법
KR10-2009-0116094 2009-11-27

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WO2011065687A2 true WO2011065687A2 (fr) 2011-06-03
WO2011065687A3 WO2011065687A3 (fr) 2011-09-29

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US9559245B2 (en) 2015-03-23 2017-01-31 Sunpower Corporation Blister-free polycrystalline silicon for solar cells

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JP3754815B2 (ja) * 1997-02-19 2006-03-15 キヤノン株式会社 光起電力素子、光電変換素子、光起電力素子の製造方法及び光電変換素子の製造方法
US20040231590A1 (en) * 2003-05-19 2004-11-25 Ovshinsky Stanford R. Deposition apparatus for the formation of polycrystalline materials on mobile substrates
KR100965778B1 (ko) * 2008-01-16 2010-06-24 서울대학교산학협력단 고효율 다결정 실리콘 태양전지 및 그 제조방법

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